93 lines
3.4 KiB
Rust
93 lines
3.4 KiB
Rust
use cortex_ar::{
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asm::dsb,
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cache::{
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clean_and_invalidate_data_cache_line_to_poc, clean_data_cache_line_to_poc,
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invalidate_data_cache_line_to_poc,
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},
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};
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use zynq7000::l2_cache::{L2Cache, MmioL2Cache};
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#[derive(Debug, Clone, Copy, PartialEq, Eq, thiserror::Error)]
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#[error("alignment error, addresses and lengths must be aligned to 32 byte cache line length")]
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pub struct AlignmentError;
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pub fn clean_and_invalidate_l2c_line(l2c: &mut MmioL2Cache<'static>, addr: u32) {
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l2c.write_clean_by_pa(addr);
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l2c.write_invalidate_by_pa(addr);
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}
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/// Invalidate an address range.
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///
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/// This function invalidates both the L1 and L2 cache. The L2C must be enabled and set up
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/// correctly for this function to work correctly.
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///
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/// The provided address and the range to invalidate must both be aligned to the 32 byte cache line
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/// length.
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pub fn invalidate_data_cache_range(addr: u32, len: usize) -> Result<(), AlignmentError> {
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if addr % 32 != 0 || len % 32 != 0 {
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return Err(AlignmentError);
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}
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let mut l2c = unsafe { L2Cache::new_mmio_fixed() };
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let mut current_addr = addr;
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// Invalidate outer caches lines first, see chapter 3.3.10 of the L2C technical reference manual.
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while current_addr < addr + len as u32 {
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l2c.write_clean_by_pa(current_addr);
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current_addr += 32;
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}
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while l2c.read_cache_sync().busy() {}
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// Invalidate inner cache lines.
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current_addr = addr;
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while current_addr < addr + len as u32 {
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invalidate_data_cache_line_to_poc(addr);
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current_addr += 32;
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}
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// Synchronize the cache maintenance.
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dsb();
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Ok(())
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}
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/// Clean and then invalidate an address range.
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///
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/// This is commonly also called cache flushing. This function cleans and invalidates both L1
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/// and L2 cache. The L2C must be enabled and set up correctly for this function to work correctly.
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pub fn clean_and_invalidate_data_cache_range(addr: u32, len: usize) -> Result<(), AlignmentError> {
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if addr % 32 != 0 || len % 32 != 0 {
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return Err(AlignmentError);
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}
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// For details on the following section, see chapter 3.3.10 of the L2C technical reference
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// manual.
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// Clean inner cache lines first.
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let mut current_addr = addr;
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while current_addr < addr + len as u32 {
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clean_data_cache_line_to_poc(current_addr);
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current_addr += 32;
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}
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dsb();
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// Clean and invalidates outer cache.
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let mut l2c = unsafe { L2Cache::new_mmio_fixed() };
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current_addr = addr;
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while current_addr < addr + len as u32 {
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// ARM errate 588369 specifies that clean and invalidate need to be separate, but the
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// current revision of the L2C on the Zynq7000 seems to be revision 8 (r3p2), and the
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// errata was fixed in r2p0. Both Xilinx and zynq-rs use the clean and invalidate operation,
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// so it should be fine. Considering the debug control in Xilinx code which disable
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// linefills and write-backs, zynq-rs does not appear to do that and it should not be
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// necessary.. I think this was related to the errata.
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l2c.write_clean_invalidate_by_pa(current_addr);
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current_addr += 32;
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}
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while l2c.read_cache_sync().busy() {}
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// Now clean and invalidate inner cache.
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current_addr = addr;
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while current_addr < addr + len as u32 {
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clean_and_invalidate_data_cache_line_to_poc(current_addr);
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current_addr += 32;
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}
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dsb();
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Ok(())
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}
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