Robin Mueller
893d2e870e
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411 lines
11 KiB
Rust
411 lines
11 KiB
Rust
//! # Triple-timer counter (TTC) high-level driver
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//!
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//! This module also contains support for PWM and output waveform generation.
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//!
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//! ## Examples
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//!
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//! - [PWM](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/embassy/src/bin/pwm.rs)
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#![deny(missing_docs)]
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use core::convert::Infallible;
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use arbitrary_int::{prelude::*, u3, u4};
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use zynq7000::ttc::{MmioRegisters, TTC_0_BASE_ADDR, TTC_1_BASE_ADDR};
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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use crate::gpio::mio::{Mio16, Mio17, Mio18, Mio19, Mio40, Mio41, Mio42, Mio43};
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use crate::{
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clocks::ArmClocks,
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gpio::{
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IoPeriphPin,
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mio::{Mio28, Mio29, Mio30, Mio31, MioPin, MuxConfig, Pin},
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},
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time::Hertz,
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};
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/// Each TTC consists of three independent timers/counters.
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#[derive(Debug, Copy, Clone)]
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pub enum TtcId {
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/// TTC 0.
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Ttc0 = 0,
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/// TTC 1.
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Ttc1 = 1,
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}
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/// Each TTC has 3 channels.
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#[derive(Debug, Copy, Clone)]
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pub enum ChannelId {
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/// Channel 0.
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Ch0 = 0,
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/// Channel 1.
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Ch1 = 1,
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/// Channel 2.
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Ch2 = 2,
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}
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/// Common trait for TTC register blocks.
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pub trait PsTtc {
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/// Register block.
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fn reg_block(&self) -> MmioRegisters<'static>;
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/// ID.
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fn id(&self) -> Option<TtcId>;
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}
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impl PsTtc for MmioRegisters<'static> {
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#[inline]
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fn reg_block(&self) -> MmioRegisters<'static> {
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unsafe { self.clone() }
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}
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#[inline]
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fn id(&self) -> Option<TtcId> {
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let base_addr = unsafe { self.ptr() } as usize;
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if base_addr == TTC_0_BASE_ADDR {
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return Some(TtcId::Ttc0);
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} else if base_addr == TTC_1_BASE_ADDR {
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return Some(TtcId::Ttc1);
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}
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None
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}
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}
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/// TTC pin configuration
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pub const TTC_MUX_CONF: MuxConfig = MuxConfig::new_with_l3(u3::new(0b110));
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/// Input clock pin trait.
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pub trait ClockInPin: MioPin {
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/// TTC ID.
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const ID: TtcId;
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}
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/// Output wave pin trait.
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pub trait WaveOutPin: MioPin {
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/// TTC ID.
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const ID: TtcId;
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}
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// TTC0 pin trait implementations.
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impl ClockInPin for Pin<Mio19> {
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const ID: TtcId = TtcId::Ttc0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl ClockInPin for Pin<Mio31> {
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const ID: TtcId = TtcId::Ttc0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl ClockInPin for Pin<Mio43> {
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const ID: TtcId = TtcId::Ttc0;
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}
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impl WaveOutPin for Pin<Mio18> {
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const ID: TtcId = TtcId::Ttc0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl WaveOutPin for Pin<Mio30> {
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const ID: TtcId = TtcId::Ttc0;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl WaveOutPin for Pin<Mio42> {
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const ID: TtcId = TtcId::Ttc0;
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}
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// TTC1 pin trait implementations.
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impl ClockInPin for Pin<Mio17> {
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const ID: TtcId = TtcId::Ttc1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl ClockInPin for Pin<Mio29> {
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const ID: TtcId = TtcId::Ttc1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl ClockInPin for Pin<Mio41> {
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const ID: TtcId = TtcId::Ttc1;
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}
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impl WaveOutPin for Pin<Mio16> {
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const ID: TtcId = TtcId::Ttc1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl WaveOutPin for Pin<Mio28> {
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const ID: TtcId = TtcId::Ttc1;
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}
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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impl WaveOutPin for Pin<Mio40> {
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const ID: TtcId = TtcId::Ttc1;
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}
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/// Triple-timer counter (TTC) peripheral.
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pub struct Ttc {
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/// TTC channel 0.
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pub ch0: TtcChannel,
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/// TTC channel 1.
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pub ch1: TtcChannel,
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/// TTC channel 2.
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pub ch2: TtcChannel,
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}
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impl Ttc {
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/// Create a new TTC instance. The passed TTC peripheral instance MUST point to a valid
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/// processing system TTC peripheral.
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///
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/// Returns [None] if the passed peripheral block does not have a valid PS TTC address.
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pub fn new(ps_ttc: impl PsTtc) -> Option<Self> {
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ps_ttc.id()?;
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let regs = ps_ttc.reg_block();
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let ch0 = TtcChannel {
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regs: unsafe { regs.clone() },
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id: ChannelId::Ch0,
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};
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let ch1 = TtcChannel {
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regs: unsafe { regs.clone() },
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id: ChannelId::Ch1,
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};
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let ch2 = TtcChannel {
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regs,
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id: ChannelId::Ch2,
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};
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Some(Self { ch0, ch1, ch2 })
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}
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}
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/// Single TTC channel.
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pub struct TtcChannel {
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regs: MmioRegisters<'static>,
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id: ChannelId,
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}
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impl TtcChannel {
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/// Raw access to the TTC MMIO registers.
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#[inline]
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pub fn regs_mut(&mut self) -> &mut MmioRegisters<'static> {
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&mut self.regs
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}
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/// Read the current counter value.
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#[inline]
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pub fn read_counter(&self) -> u16 {
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self.regs
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.read_current_counter(self.id as usize)
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.unwrap()
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.count()
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}
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/// Channel ID.
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#[inline]
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pub fn id(&self) -> ChannelId {
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self.id
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}
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}
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/// Invalid TTC pin configuration error.
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#[derive(Debug, thiserror::Error)]
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#[error("invalid TTC pin configuration")]
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pub struct InvalidTtcPinConfigError(pub MuxConfig);
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/// Frequency is zero error.
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#[derive(Debug, thiserror::Error)]
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#[error("frequency is zero")]
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pub struct FrequencyIsZeroError;
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/// TTC construction error.
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#[derive(Debug, thiserror::Error)]
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pub enum TtcConstructionError {
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/// Invalid TTC pin configuration.
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#[error("invalid TTC pin configuration")]
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InvalidTtcPinConfig(#[from] InvalidTtcPinConfigError),
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/// Frequency is zero.
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#[error("frequency is zero")]
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FrequencyIsZero(#[from] FrequencyIsZeroError),
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}
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/// Calculate prescaler register value and interval ticks for a given reference clock and
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/// frequency.
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pub fn calc_prescaler_reg_and_interval_ticks(mut ref_clk: Hertz, freq: Hertz) -> (Option<u4>, u16) {
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// TODO: Can this be optimized?
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let mut prescaler: Option<u32> = None;
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let mut tick_val = ref_clk / freq;
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while tick_val > u16::MAX as u32 {
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ref_clk /= 2;
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match prescaler {
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Some(val) => {
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if val == u4::MAX.as_u32() {
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break;
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}
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prescaler = Some(val + 1);
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}
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None => prescaler = Some(0),
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}
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tick_val = ref_clk / freq;
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}
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(prescaler.map(|v| u4::new(v as u8)), tick_val as u16)
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}
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/// PWM driver using a TTC channel.
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pub struct Pwm {
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channel: TtcChannel,
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ref_clk: Hertz,
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}
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impl Pwm {
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/// Create a new PWM instance which uses the CPU 1x clock as the clock source and also uses
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/// a MIO output pin for the waveform output.
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pub fn new_with_cpu_clk_and_mio_waveout(
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channel: TtcChannel,
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arm_clocks: &ArmClocks,
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freq: Hertz,
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wave_out: impl WaveOutPin,
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) -> Result<Self, TtcConstructionError> {
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IoPeriphPin::new(wave_out, TTC_MUX_CONF, None);
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Ok(Self::new_with_cpu_clk(channel, arm_clocks, freq)?)
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}
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/// Create a new PWM instance which uses the CPU 1x clock as the clock source.
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pub fn new_with_cpu_clk(
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channel: TtcChannel,
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arm_clocks: &ArmClocks,
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freq: Hertz,
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) -> Result<Self, FrequencyIsZeroError> {
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Self::new_generic(channel, arm_clocks.cpu_1x_clk(), freq)
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}
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/// Create a new PWM instance based on a reference clock source.
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pub fn new_generic(
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channel: TtcChannel,
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ref_clk: Hertz,
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freq: Hertz,
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) -> Result<Self, FrequencyIsZeroError> {
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if freq.raw() == 0 {
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return Err(FrequencyIsZeroError);
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}
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let (prescaler_reg, tick_val) = calc_prescaler_reg_and_interval_ticks(ref_clk, freq);
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let id = channel.id() as usize;
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let mut pwm = Self { channel, ref_clk };
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pwm.set_up_and_configure_pwm(id, prescaler_reg, tick_val);
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Ok(pwm)
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}
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/// Set a new frequency for the PWM cycle.
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///
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/// This resets the duty cycle to 0%.
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pub fn set_frequency(&mut self, freq: Hertz) -> Result<(), FrequencyIsZeroError> {
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if freq.raw() == 0 {
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return Err(FrequencyIsZeroError);
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}
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let id = self.channel.id() as usize;
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let (prescaler_reg, tick_val) = calc_prescaler_reg_and_interval_ticks(self.ref_clk, freq);
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self.set_up_and_configure_pwm(id, prescaler_reg, tick_val);
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Ok(())
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}
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/// Mutable access to the underlying TTC channel.
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#[inline]
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pub fn ttc_channel_mut(&mut self) -> &mut TtcChannel {
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&mut self.channel
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}
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/// Maximum duty cycle value.
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#[inline]
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pub fn max_duty_cycle(&self) -> u16 {
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self.channel
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.regs
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.read_interval_value(self.channel.id() as usize)
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.unwrap()
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.value()
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}
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/// Set duty cycle value.
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#[inline]
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pub fn set_duty_cycle(&mut self, duty: u16) {
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let id = self.channel.id() as usize;
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self.channel
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.regs
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.modify_cnt_ctrl(id, |mut val| {
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val.set_disable(true);
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val
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})
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.unwrap();
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self.channel
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.regs
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.write_match_value_0(
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self.channel.id() as usize,
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zynq7000::ttc::RwValue::new_with_raw_value(duty as u32),
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)
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.unwrap();
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self.channel
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.regs
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.modify_cnt_ctrl(id, |mut val| {
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val.set_disable(false);
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val.set_reset(true);
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val
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})
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.unwrap();
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}
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fn set_up_and_configure_pwm(&mut self, id: usize, prescaler_reg: Option<u4>, tick_val: u16) {
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// Disable the counter first.
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self.channel
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.regs
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.write_cnt_ctrl(id, zynq7000::ttc::CounterControl::new_with_raw_value(1))
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.unwrap();
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// Clock configuration
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self.channel
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.regs
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.write_clk_cntr(
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id,
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zynq7000::ttc::ClockControl::builder()
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.with_ext_clk_edge(false)
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.with_clk_src(zynq7000::ttc::ClockSource::Pclk)
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.with_prescaler(prescaler_reg.unwrap_or(u4::new(0)))
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.with_prescale_enable(prescaler_reg.is_some())
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.build(),
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)
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.unwrap();
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self.channel
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.regs
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.write_interval_value(
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id,
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zynq7000::ttc::RwValue::new_with_raw_value(tick_val as u32),
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)
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.unwrap();
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// Corresponds to duty cycle 0.
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self.channel
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.regs
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.write_match_value_0(id, zynq7000::ttc::RwValue::new_with_raw_value(0))
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.unwrap();
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self.channel
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.regs
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.write_cnt_ctrl(
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id,
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zynq7000::ttc::CounterControl::builder()
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.with_wave_polarity(zynq7000::ttc::WavePolarity::LowToHighOnMatch1)
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.with_wave_enable_n(zynq7000::ttc::WaveEnable::Enable)
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.with_reset(true)
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.with_match_enable(true)
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.with_decrementing(false)
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.with_mode(zynq7000::ttc::Mode::Interval)
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.with_disable(false)
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.build(),
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)
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.unwrap();
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}
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}
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impl embedded_hal::pwm::ErrorType for Pwm {
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type Error = Infallible;
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}
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impl embedded_hal::pwm::SetDutyCycle for Pwm {
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#[inline]
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fn max_duty_cycle(&self) -> u16 {
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self.max_duty_cycle()
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}
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#[inline]
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fn set_duty_cycle(&mut self, duty: u16) -> Result<(), Self::Error> {
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self.set_duty_cycle(duty);
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Ok(())
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}
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}
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