203 lines
5.7 KiB
Rust
203 lines
5.7 KiB
Rust
//! # GIC (Generic Interrupt Controller) register module.
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pub use crate::mpcore::{GICC_BASE_ADDR, GICD_BASE_ADDR};
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use arbitrary_int::{u3, u5, u10};
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use static_assertions::const_assert_eq;
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/// Distributor Control Register
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct Dcr {
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#[bit(1, rw)]
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enable_non_secure: bool,
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#[bit(0, rw)]
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enable_secure: bool,
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}
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/// Read only bit. This register only returns fixed constants.
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#[bitbybit::bitfield(u32)]
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pub struct TypeRegister {
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#[bits(11..=15, r)]
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lspi: u5,
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#[bit(10, r)]
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security_extension: bool,
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#[bits(5..=7, r)]
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cpu_number: u3,
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#[bits(0..=4, r)]
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it_lines_number: u5,
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}
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impl TypeRegister {
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pub const SECURITY_EXTNS_BIT: bool = true;
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/// 31 LSPIs.
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pub const NUM_LSPI: usize = 0x1f;
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/// Encoding: 0b001 means that the Cortex-A9 MPCore has 2 processors.
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pub const CPU_NUMBER_BITS: u8 = 0b001;
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/// The distributor provides 96 interrupts.
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pub const IT_LINES_NUMBER: u8 = 0x2;
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pub const NUM_OF_CPUS: usize = 2;
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pub const NUM_OF_INTERRUPTS: usize = 96;
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}
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pub type Typer = TypeRegister;
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/// GIC Distributor registers.
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#[derive(derive_mmio::Mmio)]
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#[repr(C, align(8))]
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pub struct Gicd {
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/// Distributor Control Register
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pub dcr: Dcr,
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/// Interrupt Controller Type Register
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#[mmio(PureRead)]
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pub ictr: Typer,
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/// Distributor Implementer Identification Register
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#[mmio(PureRead)]
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pub iidr: u32,
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_reserved_0: [u32; 0x1D],
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/// Interrupt security registers
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pub isr: [u32; 3],
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_reserved_1: [u32; 0x1D],
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/// Interrupt Set-Enable Registers
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pub iser: [u32; 0x3],
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_reserved_3: [u32; 0x1D],
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/// Interrupt Clear-Enable Registers
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pub icer: [u32; 0x3],
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_reserved_4: [u32; 0x1D],
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/// Interrupt Set-Pending Registers
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pub ispr: [u32; 0x3],
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_reserved_5: [u32; 0x1D],
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/// Interrupt Clear-Pending Registers
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pub icpr: [u32; 0x3],
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_reserved_6: [u32; 0x1D],
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/// Active Bit Registers
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pub abr: [u32; 0x3],
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_reserved_10: [u32; 0x3D],
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/// Interrupt Priority Registers
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pub ipr: [u32; 0x18],
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_reserved_11: [u32; 0xE8],
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/// Interrupt Processor Targes Registers
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pub iptr_sgi: [u32; 0x4],
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// TODO: Mark those read-only as soon as that works for arrays.
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pub iptr_ppi: [u32; 0x4],
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pub iptr_spi: [u32; 0x10],
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// Those are split in the ARM documentation for some reason..
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_reserved_12: [u32; 0xE8],
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/// Interrupt Configuration Registers
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/// Interupt sensitivity register for software generated interrupts (SGI)
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pub icfr_0_sgi: u32,
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/// Interupt sensitivity register for private peripheral interrupts (PPI)
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pub icfr_1_ppi: u32,
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pub icfr_2_spi: u32,
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pub icfr_3_spi: u32,
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pub icfr_4_spi: u32,
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pub icfr_5_spi: u32,
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_reserved_13: [u32; 0x3A],
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pub ppi_status: u32,
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pub spi_status_0: u32,
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pub spi_status_1: u32,
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_reserved_14: [u32; 0x7D],
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/// Software Generated Interrupt Register.
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pub sgir: u32,
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_reserved_15: [u32; 0x33],
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pub pidr_4: u32,
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pub pidr_5: u32,
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pub pidr_6: u32,
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pub pidr_7: u32,
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pub pidr_0: u32,
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pub pidr_1: u32,
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pub pidr_2: u32,
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pub pidr_3: u32,
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pub cidr: [u32; 4],
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}
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const_assert_eq!(core::mem::size_of::<Gicd>(), 0x1000);
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impl Gicd {
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/// Create a new Global Interrupt Controller Distributor MMIO instance at the fixed address of
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/// the processing system.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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#[inline]
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pub const unsafe fn new_mmio_fixed() -> MmioGicd<'static> {
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unsafe { Self::new_mmio_at(GICD_BASE_ADDR) }
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}
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}
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/// CPU interface control register.
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#[bitbybit::bitfield(u32, default = 0x0)]
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pub struct Icr {
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#[bit(4, rw)]
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sbpr: bool,
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#[bit(3, rw)]
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fiq_en: bool,
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#[bit(2, rw)]
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ack_ctrl: bool,
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#[bit(1, rw)]
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enable_non_secure: bool,
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#[bit(0, rw)]
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enable_secure: bool,
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}
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/// Priority Mask Register
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#[bitbybit::bitfield(u32)]
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pub struct PriorityRegister {
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#[bits(0..=7, rw)]
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priority: u8,
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}
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/// Interrupt acknowledge register.
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptSignalRegister {
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#[bits(10..=12, rw)]
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cpu_id: u3,
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#[bits(0..=9, rw)]
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ack_int_id: u10,
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}
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/// GIC CPU interface registers.
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#[derive(derive_mmio::Mmio)]
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#[repr(C, align(8))]
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pub struct Gicc {
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/// CPU Interface Control Register.
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pub icr: Icr,
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/// Interrupt Priority Mask Register.
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pub pmr: PriorityRegister,
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/// Binary Point Register.
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pub bpr: u32,
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/// Interrupt Acknowledge Register.
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pub iar: InterruptSignalRegister,
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/// End of Interrupt Register.
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pub eoir: InterruptSignalRegister,
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/// Running Priority Register.
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pub rpr: PriorityRegister,
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/// Highest Pending Interrupt Register.
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pub hpir: InterruptSignalRegister,
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/// Aliased Binary Point Register
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pub abpr: u32,
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_reserved_0: [u32; 0x37],
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/// CPU Interface Identification Register.
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#[mmio(PureRead)]
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pub iidr: u32,
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}
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const_assert_eq!(core::mem::size_of::<Gicc>(), 0x100);
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impl Gicc {
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/// Create a new Global Interrupt Controller CPU MMIO instance at the fixed address of the
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/// processing system.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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#[inline]
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pub const unsafe fn new_mmio_fixed() -> MmioGicc<'static> {
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unsafe { Self::new_mmio_at(GICC_BASE_ADDR) }
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}
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}
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