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342 lines
18 KiB
Rust
342 lines
18 KiB
Rust
use std::{collections::HashMap, ops::RangeInclusive, path::Path};
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use clap::Parser as _;
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use simple_logger::SimpleLogger;
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const DDRC_ADDR_RANGE: RangeInclusive<u32> = 0xf800_6000..=0xf800_62b4;
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const DDRIOB_ADDR_RANGE: RangeInclusive<u32> = 0xf800_0b40..=0xf800_0b68;
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const DDRC_FILE_NAME: &str = "ddrc_config_autogen.rs";
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const DDRIOB_FILE_NAME: &str = "ddriob_config_autogen.rs";
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#[derive(clap::Parser, Debug)]
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#[command(version, about)]
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pub struct Cli {
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/// Path to ps7init.tcl file.
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#[arg(short, long)]
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path: String,
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}
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fn extract_hex_values(line: &str) -> Option<(u32, u32, u32)> {
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let re = regex::Regex::new(r"0[xX]([0-9A-Fa-f]+)").unwrap();
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let captures: Vec<u32> = re
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.captures_iter(line)
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.filter_map(|cap| u32::from_str_radix(&cap[1], 16).ok())
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.collect();
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if captures.len() == 3 {
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Some((captures[0], captures[1], captures[2]))
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} else {
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None
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}
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}
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#[derive(Default)]
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pub struct RegisterToValueMap(pub HashMap<u32, u32>);
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impl RegisterToValueMap {
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fn val_as_token(&self, reg_name: &str, addr: u32) -> proc_macro2::TokenStream {
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let val = self.0.get(&addr).unwrap_or_else(|| {
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panic!(
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"failed to retrieve register value for register {}",
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reg_name
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)
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});
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format!("{:#010x}", val)
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.parse::<proc_macro2::TokenStream>()
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.unwrap()
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}
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}
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enum ParsingMode {
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DdrRev3,
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MioRev3,
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}
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fn main() -> std::io::Result<()> {
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SimpleLogger::new().init().unwrap();
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let cli = Cli::parse();
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let ps7init_tcl = Path::new(&cli.path);
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if !ps7init_tcl.exists() {
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log::error!("File not found: {}", ps7init_tcl.display());
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std::process::exit(1);
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}
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let mut parsing_mode = None;
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let mut reg_to_values = RegisterToValueMap::default();
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for line in std::fs::read_to_string(ps7init_tcl)?.lines() {
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match parsing_mode {
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None => {
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if line.contains("ps7_ddr_init_data_3_0") {
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parsing_mode = Some(ParsingMode::DdrRev3);
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} else if line.contains("ps7_mio_init_data_3_0") {
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parsing_mode = Some(ParsingMode::MioRev3);
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}
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continue;
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}
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Some(ParsingMode::MioRev3) => {
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if line.contains("}") {
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parsing_mode = None;
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continue;
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}
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}
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Some(ParsingMode::DdrRev3) => {
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if line.contains("}") {
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parsing_mode = None;
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continue;
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}
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}
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}
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if let Some((addr, _mask, value)) = extract_hex_values(line)
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&& (DDRC_ADDR_RANGE.contains(&addr) || DDRIOB_ADDR_RANGE.contains(&addr))
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&& addr % 4 == 0
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{
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// Only use first value.
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if reg_to_values.0.contains_key(&addr) {
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if addr != 0xF800_6000 {
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log::warn!("detected duplicate register value for address {}", addr);
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}
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continue;
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}
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reg_to_values.0.insert(addr, value);
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}
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}
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log::info!("generating DDRC config files: {}", DDRC_FILE_NAME);
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generate_ddrc_config(®_to_values, DDRC_FILE_NAME)?;
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log::info!("generating DDRIOB config files: {}", DDRIOB_FILE_NAME);
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generate_ddriob_config(®_to_values, DDRIOB_FILE_NAME)?;
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Ok(())
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}
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fn generate_ddrc_config(
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reg_to_values: &RegisterToValueMap,
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file_name: &str,
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) -> std::io::Result<()> {
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// Format as hex strings
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let ddrc = reg_to_values.val_as_token("DDRC Control", 0xF800_6000);
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let two_rank = reg_to_values.val_as_token("Two Rank", 0xF800_6004);
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let hpr = reg_to_values.val_as_token("HPR", 0xF800_6008);
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let lpr = reg_to_values.val_as_token("LPR", 0xF800_600C);
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let wr = reg_to_values.val_as_token("WR", 0xF800_6010);
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let dram_param_0 = reg_to_values.val_as_token("DRAM Reg0", 0xF800_6014);
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let dram_param_1 = reg_to_values.val_as_token("DRAM Reg1", 0xF800_6018);
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let dram_param_2 = reg_to_values.val_as_token("DRAM Reg2", 0xF800_601C);
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let dram_param_3 = reg_to_values.val_as_token("DRAM Reg3", 0xF800_6020);
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let dram_param_4 = reg_to_values.val_as_token("DRAM Reg4", 0xF800_6024);
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let dram_init_param = reg_to_values.val_as_token("DRAM Init Param", 0xF800_6028);
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let dram_emr = reg_to_values.val_as_token("DRAM EMR", 0xF800_602C);
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let dram_emr_mr = reg_to_values.val_as_token("DRAM EMR MR", 0xF800_6030);
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let dram_burst8_rdwr = reg_to_values.val_as_token("DRAM Burst8 RDWR", 0xF800_6034);
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let dram_disable_dq = reg_to_values.val_as_token("DRAM Disable DQ", 0xF800_6038);
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let dram_addr_map_bank = reg_to_values.val_as_token("DRAM Addr Map Bank", 0xF800_603C);
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let dram_addr_map_col = reg_to_values.val_as_token("DRAM Addr Map Col", 0xF800_6040);
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let dram_addr_map_row = reg_to_values.val_as_token("DRAM Addr Map Row", 0xF800_6044);
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let dram_odt = reg_to_values.val_as_token("DRAM ODT", 0xF800_6048);
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let phy_cmd_timeout_rddata_cpt = reg_to_values.val_as_token("PHY CMD Timeout", 0xF800_6050);
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let dll_calib = reg_to_values.val_as_token("DLL Calib", 0xF800_6058);
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let odt_delay_hold = reg_to_values.val_as_token("ODT Delay Hold", 0xF800_605C);
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let ctrl_reg1 = reg_to_values.val_as_token("CTRL Reg 1", 0xF800_6060);
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let ctrl_reg2 = reg_to_values.val_as_token("CTRL Reg 2", 0xF800_6064);
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let ctrl_reg3 = reg_to_values.val_as_token("CTRL Reg 3", 0xF800_6068);
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let ctrl_reg4 = reg_to_values.val_as_token("CTRL Reg 4", 0xF800_606C);
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let ctrl_reg5 = reg_to_values.val_as_token("CTRL Reg 5", 0xF800_6078);
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let ctrl_reg6 = reg_to_values.val_as_token("CTRL Reg 6", 0xF800_607C);
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let che_t_zq = reg_to_values.val_as_token("CHE T ZQ", 0xF800_60A4);
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let che_t_zq_short_interval_reg =
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reg_to_values.val_as_token("CHE T ZQ Short Interval", 0xF800_60A4);
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let deep_powerdown = reg_to_values.val_as_token("Deep Powerdown", 0xF800_60AC);
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let reg_2c = reg_to_values.val_as_token("Reg 2C", 0xF800_60B0);
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let reg_2d = reg_to_values.val_as_token("Reg 2D", 0xF800_60B4);
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let dfi_timing = reg_to_values.val_as_token("DFI Timing", 0xF800_60B8);
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let che_ecc_ctrl = reg_to_values.val_as_token("CHE ECC CTRL", 0xF800_60C4);
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let ecc_scrub = reg_to_values.val_as_token("ECC Scrub", 0xF800_60F4);
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let phy_receiver_enable = reg_to_values.val_as_token("PHY Receiver Enable", 0xF800_6114);
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let phy_config_0 = reg_to_values.val_as_token("PHY Config 0", 0xF800_6118);
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let phy_config_1 = reg_to_values.val_as_token("PHY Config 1", 0xF800_611C);
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let phy_config_2 = reg_to_values.val_as_token("PHY Config 2", 0xF800_6120);
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let phy_config_3 = reg_to_values.val_as_token("PHY Config 3", 0xF800_6124);
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let phy_init_ratio_0 = reg_to_values.val_as_token("PHY Init Ratio 0", 0xF800_612C);
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let phy_init_ratio_1 = reg_to_values.val_as_token("PHY Init Ratio 1", 0xF800_6130);
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let phy_init_ratio_2 = reg_to_values.val_as_token("PHY Init Ratio 2", 0xF800_6134);
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let phy_init_ratio_3 = reg_to_values.val_as_token("PHY Init Ratio 3", 0xF800_6138);
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let phy_rd_dqs_config_0 = reg_to_values.val_as_token("PHY RD DQS Config 0", 0xF800_6140);
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let phy_rd_dqs_config_1 = reg_to_values.val_as_token("PHY RD DQS Config 1", 0xF800_6144);
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let phy_rd_dqs_config_2 = reg_to_values.val_as_token("PHY RD DQS Config 2", 0xF800_6148);
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let phy_rd_dqs_config_3 = reg_to_values.val_as_token("PHY RD DQS Config 3", 0xF800_614C);
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let phy_wr_dqs_config_0 = reg_to_values.val_as_token("PHY WR DQS Config 0", 0xF800_6154);
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let phy_wr_dqs_config_1 = reg_to_values.val_as_token("PHY WR DQS Config 1", 0xF800_6158);
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let phy_wr_dqs_config_2 = reg_to_values.val_as_token("PHY WR DQS Config 2", 0xF800_615C);
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let phy_wr_dqs_config_3 = reg_to_values.val_as_token("PHY WR DQS Config 3", 0xF800_6160);
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let phy_we_cfg_0 = reg_to_values.val_as_token("PHY WE Config 0", 0xF800_6168);
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let phy_we_cfg_1 = reg_to_values.val_as_token("PHY WE Config 1", 0xF800_616C);
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let phy_we_cfg_2 = reg_to_values.val_as_token("PHY WE Config 2", 0xF800_6170);
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let phy_we_cfg_3 = reg_to_values.val_as_token("PHY WE Config 3", 0xF800_6174);
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let phy_wr_data_slv_0 = reg_to_values.val_as_token("PHY WR Data Slv 0", 0xF800_617C);
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let phy_wr_data_slv_1 = reg_to_values.val_as_token("PHY WR Data Slv 1", 0xF800_6180);
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let phy_wr_data_slv_2 = reg_to_values.val_as_token("PHY WR Data Slv 2", 0xF800_6184);
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let phy_wr_data_slv_3 = reg_to_values.val_as_token("PHY WR Data Slv 3", 0xF800_6188);
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let reg64 = reg_to_values.val_as_token("Reg64", 0xF800_6190);
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let reg65 = reg_to_values.val_as_token("Reg65", 0xF800_6194);
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let page_mask = reg_to_values.val_as_token("Page Mask", 0xF800_6204);
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let axi_priority_wr_port_0 = reg_to_values.val_as_token("AXI Priority WR Port 0", 0xF800_6208);
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let axi_priority_wr_port_1 = reg_to_values.val_as_token("AXI Priority WR Port 1", 0xF800_620C);
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let axi_priority_wr_port_2 = reg_to_values.val_as_token("AXI Priority WR Port 2", 0xF800_6210);
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let axi_priority_wr_port_3 = reg_to_values.val_as_token("AXI Priority WR Port 3", 0xF800_6214);
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let axi_priority_rd_port_0 = reg_to_values.val_as_token("AXI Priority RD Port 0", 0xF800_6218);
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let axi_priority_rd_port_1 = reg_to_values.val_as_token("AXI Priority RD Port 1", 0xF800_621C);
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let axi_priority_rd_port_2 = reg_to_values.val_as_token("AXI Priority RD Port 2", 0xF800_6220);
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let axi_priority_rd_port_3 = reg_to_values.val_as_token("AXI Priority RD Port 3", 0xF800_6224);
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let lpddr_ctrl_0 = reg_to_values.val_as_token("LPDDR CTRL 0", 0xF800_62A8);
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let lpddr_ctrl_1 = reg_to_values.val_as_token("LPDDR CTRL 1", 0xF800_62AC);
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let lpddr_ctrl_2 = reg_to_values.val_as_token("LPDDR CTRL 2", 0xF800_62B0);
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let lpddr_ctrl_3 = reg_to_values.val_as_token("LPDDR CTRL 3", 0xF800_62B4);
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let generated = quote::quote! {
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//!This file was auto-generated by the [zynq7000-ps7init-extract](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/tools/zynq7000-ps7init-extract) program.
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//!
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//!This configuration file contains static DDR configuration parameters extracted from the
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//!AMD ps7init.tcl file
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use zynq7000::ddrc::regs;
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use zynq7000_hal::ddr::DdrcConfigSet;
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pub const DDRC_CONFIG_ZEDBOARD: DdrcConfigSet = DdrcConfigSet {
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ctrl: regs::DdrcControl::new_with_raw_value(#ddrc),
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two_rank: regs::TwoRankConfig::new_with_raw_value(#two_rank),
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hpr: regs::LprHprQueueControl::new_with_raw_value(#hpr),
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lpr: regs::LprHprQueueControl::new_with_raw_value(#lpr),
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wr: regs::WriteQueueControl::new_with_raw_value(#wr),
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dram_param_0: regs::DramParamReg0::new_with_raw_value(#dram_param_0),
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dram_param_1: regs::DramParamReg1::new_with_raw_value(#dram_param_1),
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dram_param_2: regs::DramParamReg2::new_with_raw_value(#dram_param_2),
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dram_param_3: regs::DramParamReg3::new_with_raw_value(#dram_param_3),
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dram_param_4: regs::DramParamReg4::new_with_raw_value(#dram_param_4),
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dram_init_param: regs::DramInitParam::new_with_raw_value(#dram_init_param),
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dram_emr: regs::DramEmr::new_with_raw_value(#dram_emr),
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dram_emr_mr: regs::DramEmrMr::new_with_raw_value(#dram_emr_mr),
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dram_burst8_rdwr: regs::DramBurst8ReadWrite::new_with_raw_value(#dram_burst8_rdwr),
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disable_dq: regs::DisableDq::new_with_raw_value(#dram_disable_dq),
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dram_addr_map_bank: regs::DramAddrMapBank::new_with_raw_value(#dram_addr_map_bank),
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dram_addr_map_col: regs::DramAddrMapColumn::new_with_raw_value(#dram_addr_map_col),
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dram_addr_map_row: regs::DramAddrMapRow::new_with_raw_value(#dram_addr_map_row),
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dram_odt: regs::DramOdt::new_with_raw_value(#dram_odt),
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phy_cmd_timeout_rddata_cpt: regs::PhyCmdTimeoutRdDataCpt::new_with_raw_value(#phy_cmd_timeout_rddata_cpt),
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dll_calib: regs::DllCalib::new_with_raw_value(#dll_calib),
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odt_delay_hold: regs::OdtDelayHold::new_with_raw_value(#odt_delay_hold),
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ctrl_reg1: regs::CtrlReg1::new_with_raw_value(#ctrl_reg1),
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ctrl_reg2: regs::CtrlReg2::new_with_raw_value(#ctrl_reg2),
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ctrl_reg3: regs::CtrlReg3::new_with_raw_value(#ctrl_reg3),
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ctrl_reg4: regs::CtrlReg4::new_with_raw_value(#ctrl_reg4),
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ctrl_reg5: regs::CtrlReg5::new_with_raw_value(#ctrl_reg5),
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ctrl_reg6: regs::CtrlReg6::new_with_raw_value(#ctrl_reg6),
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che_t_zq: regs::CheTZq::new_with_raw_value(#che_t_zq),
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che_t_zq_short_interval_reg: regs::CheTZqShortInterval::new_with_raw_value(#che_t_zq_short_interval_reg),
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deep_powerdown: regs::DeepPowerdown::new_with_raw_value(#deep_powerdown),
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reg_2c: regs::Reg2c::new_with_raw_value(#reg_2c),
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reg_2d: regs::Reg2d::new_with_raw_value(#reg_2d),
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dfi_timing: regs::DfiTiming::new_with_raw_value(#dfi_timing),
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che_ecc_ctrl: regs::CheEccControl::new_with_raw_value(#che_ecc_ctrl),
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ecc_scrub: regs::EccScrub::new_with_raw_value(#ecc_scrub),
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phy_receiver_enable: regs::PhyReceiverEnable::new_with_raw_value(#phy_receiver_enable),
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phy_config: [
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regs::PhyConfig::new_with_raw_value(#phy_config_0),
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regs::PhyConfig::new_with_raw_value(#phy_config_1),
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regs::PhyConfig::new_with_raw_value(#phy_config_2),
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regs::PhyConfig::new_with_raw_value(#phy_config_3),
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],
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phy_init_ratio: [
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regs::PhyInitRatio::new_with_raw_value(#phy_init_ratio_0),
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regs::PhyInitRatio::new_with_raw_value(#phy_init_ratio_1),
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regs::PhyInitRatio::new_with_raw_value(#phy_init_ratio_2),
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regs::PhyInitRatio::new_with_raw_value(#phy_init_ratio_3),
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],
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phy_rd_dqs_config: [
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regs::PhyDqsConfig::new_with_raw_value(#phy_rd_dqs_config_0),
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regs::PhyDqsConfig::new_with_raw_value(#phy_rd_dqs_config_1),
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regs::PhyDqsConfig::new_with_raw_value(#phy_rd_dqs_config_2),
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regs::PhyDqsConfig::new_with_raw_value(#phy_rd_dqs_config_3),
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],
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phy_wr_dqs_config: [
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regs::PhyDqsConfig::new_with_raw_value(#phy_wr_dqs_config_0),
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regs::PhyDqsConfig::new_with_raw_value(#phy_wr_dqs_config_1),
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regs::PhyDqsConfig::new_with_raw_value(#phy_wr_dqs_config_2),
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regs::PhyDqsConfig::new_with_raw_value(#phy_wr_dqs_config_3),
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],
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phy_we_cfg: [
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regs::PhyWriteEnableConfig::new_with_raw_value(#phy_we_cfg_0),
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regs::PhyWriteEnableConfig::new_with_raw_value(#phy_we_cfg_1),
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regs::PhyWriteEnableConfig::new_with_raw_value(#phy_we_cfg_2),
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regs::PhyWriteEnableConfig::new_with_raw_value(#phy_we_cfg_3),
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],
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phy_wr_data_slv: [
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regs::PhyWriteDataSlaveConfig::new_with_raw_value(#phy_wr_data_slv_0),
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regs::PhyWriteDataSlaveConfig::new_with_raw_value(#phy_wr_data_slv_1),
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regs::PhyWriteDataSlaveConfig::new_with_raw_value(#phy_wr_data_slv_2),
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regs::PhyWriteDataSlaveConfig::new_with_raw_value(#phy_wr_data_slv_3),
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],
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reg64: regs::Reg64::new_with_raw_value(#reg64),
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reg65: regs::Reg65::new_with_raw_value(#reg65),
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page_mask: #page_mask,
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axi_priority_wr_port: [
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regs::AxiPriorityWritePort::new_with_raw_value(#axi_priority_wr_port_0),
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regs::AxiPriorityWritePort::new_with_raw_value(#axi_priority_wr_port_1),
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regs::AxiPriorityWritePort::new_with_raw_value(#axi_priority_wr_port_2),
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regs::AxiPriorityWritePort::new_with_raw_value(#axi_priority_wr_port_3),
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],
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axi_priority_rd_port: [
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regs::AxiPriorityReadPort::new_with_raw_value(#axi_priority_rd_port_0),
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regs::AxiPriorityReadPort::new_with_raw_value(#axi_priority_rd_port_1),
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regs::AxiPriorityReadPort::new_with_raw_value(#axi_priority_rd_port_2),
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regs::AxiPriorityReadPort::new_with_raw_value(#axi_priority_rd_port_3),
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],
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lpddr_ctrl_0: regs::LpddrControl0::new_with_raw_value(#lpddr_ctrl_0),
|
|
lpddr_ctrl_1: regs::LpddrControl1::new_with_raw_value(#lpddr_ctrl_1),
|
|
lpddr_ctrl_2: regs::LpddrControl2::new_with_raw_value(#lpddr_ctrl_2),
|
|
lpddr_ctrl_3: regs::LpddrControl3::new_with_raw_value(#lpddr_ctrl_3),
|
|
};
|
|
};
|
|
|
|
std::fs::write(file_name, generated.to_string())?;
|
|
Ok(())
|
|
}
|
|
|
|
fn generate_ddriob_config(
|
|
reg_to_values: &RegisterToValueMap,
|
|
file_name: &str,
|
|
) -> std::io::Result<()> {
|
|
// Format as hex strings
|
|
let addr0 = reg_to_values.val_as_token("DDRIOB Addr 0", 0xF800_0B40);
|
|
let addr1 = reg_to_values.val_as_token("DDRIOB Addr 1", 0xF800_0B44);
|
|
let data0 = reg_to_values.val_as_token("DDRIOB Data 0", 0xF800_0B48);
|
|
let data1 = reg_to_values.val_as_token("DDRIOB Data 1", 0xF800_0B4C);
|
|
let diff0 = reg_to_values.val_as_token("DDRIOB Diff 0", 0xF800_0B50);
|
|
let diff1 = reg_to_values.val_as_token("DDRIOB Diff 1", 0xF800_0B54);
|
|
let clock = reg_to_values.val_as_token("DDRIOB Clock", 0xF800_0B58);
|
|
let generated = quote::quote! {
|
|
//!This file was auto-generated by the [zynq7000-ps7init-extract](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/tools/zynq7000-ps7init-extract) program.
|
|
//!
|
|
//!This configuration file contains static DDRIOB configuration parameters extracted from the
|
|
//!AMD ps7init.tcl file
|
|
use zynq7000::ddrc::regs;
|
|
use zynq7000_hal::ddr::DdriobConfigSet;
|
|
|
|
pub const DDRIOB_CONFIG_SET_ZEDBOARD: DdriobConfigSet = DdriobConfigSet {
|
|
addr0: regs::DdriobConfig::new_with_raw_value(#addr0),
|
|
addr1: regs::DdriobConfig::new_with_raw_value(#addr1),
|
|
data0: regs::DdriobConfig::new_with_raw_value(#data0),
|
|
data1: regs::DdriobConfig::new_with_raw_value(#data1),
|
|
diff0: regs::DdriobConfig::new_with_raw_value(#diff0),
|
|
diff1: regs::DdriobConfig::new_with_raw_value(#diff1),
|
|
clock: regs::DdriobConfig::new_with_raw_value(#clock),
|
|
};
|
|
};
|
|
|
|
std::fs::write(file_name, generated.to_string())?;
|
|
Ok(())
|
|
}
|