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145 lines
2.8 KiB
Rust
145 lines
2.8 KiB
Rust
use arbitrary_int::{u4, u6};
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pub const L2C_BASE_ADDR: usize = 0xF8F0_2000;
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct LockdownRegisters {
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data: u32,
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instruction: u32,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct CacheSync {
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#[bit(0, r)]
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busy: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct DebugControl {
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#[bit(2, rw)]
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spniden: bool,
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#[bit(1, rw)]
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disable_write_back: bool,
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#[bit(0, rw)]
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disable_cache_linefill: bool,
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct CacheId {
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#[bits(24..=31, r)]
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implementer: u8,
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#[bits(10..=15, r)]
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cache_id: u6,
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#[bits(6..=9, r)]
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part_number: u4,
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#[bits(0..=5, r)]
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rtl_release: u6,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct L2Cache {
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#[mmio(PureRead)]
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cache_id: CacheId,
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#[mmio(PureRead)]
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cache_type: u32,
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_reserved: [u32; 0x3E],
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control: u32,
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aux_control: u32,
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tag_ram_control: u32,
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data_ram_control: u32,
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_reserved2: [u32; 0x3C],
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event_counter_control: u32,
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event_counter_1_config: u32,
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event_counter_0_config: u32,
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event_counter_1: u32,
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event_counter_0: u32,
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interrupt_mask: u32,
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#[mmio(PureRead)]
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interrupt_mask_status: u32,
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#[mmio(PureRead)]
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interrupt_raw_status: u32,
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#[mmio(Write)]
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interrupt_clear: u32,
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_reserved3: [u32; 0x143],
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cache_sync: CacheSync,
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_reserved4: [u32; 0xF],
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invalidate_by_pa: u32,
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_reserved5: [u32; 0x2],
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invalidate_by_way: u32,
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_reserved6: [u32; 0xC],
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clean_by_pa: u32,
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_reserved7: u32,
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clean_by_index: u32,
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clean_by_way: u32,
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_reserved8: [u32; 0xC],
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clean_invalidate_by_pa: u32,
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_reserved9: u32,
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clean_invalidate_by_index: u32,
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clean_invalidate_by_way: u32,
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_reserved10: [u32; 0x40],
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#[mmio(Inner)]
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lockdown_regs: [LockdownRegisters; 8],
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_reserved11: [u32; 0x4],
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lockdown_by_line_enable: u32,
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unlock_way: u32,
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_reserved12: [u32; 0xAA],
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addr_filtering_start: u32,
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addr_filtering_end: u32,
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_reserved13: [u32; 0xCE],
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debug_control: DebugControl,
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_reserved14: [u32; 0x7],
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prefetch_control: u32,
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_reserved15: [u32; 0x7],
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power_control: u32,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<L2Cache>(), 0xF84);
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impl L2Cache {
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/// Create a new L2C MMIO instance for for L2 Cache at address [I2C_0_BASE_ADDR].
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed() -> MmioL2Cache<'static> {
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unsafe { Self::new_mmio_at(L2C_BASE_ADDR) }
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}
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}
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