Robin Mueller
5d0f2837d1
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This PR introduces some major features while also changing the project structure to be more flexible for multiple platforms (e.g. host tooling). It also includes a lot of bugfixes, renamings for consistency purposes and dependency updates. Added features: 1. Pure Rust FSBL for the Zedboard. This first variant is simplistic. It is currently only capable of QSPI boot. It searches for a bitstream and ELF file inside the boot binary, flashes them and jumps to them. 2. QSPI flasher for the Zedboard. 3. DDR, QSPI, DEVC, private CPU timer and PLL configuration modules 3. Tooling to auto-generate board specific DDR and DDRIOB config parameters from the vendor provided ps7init.tcl file Changed project structure: 1. All target specific project are inside a dedicated workspace inside the `zynq` folder now. 2. All tool intended to be run on a host are inside a `tools` workspace 3. All other common projects are at the project root Major bugfixes: 1. SPI module: CPOL was not configured properly 2. Logger flush implementation was empty, implemented properly now.
711 lines
31 KiB
Tcl
711 lines
31 KiB
Tcl
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################################################################
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# This is a generated script based on design: zedboard
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2024.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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if { [string compare $scripts_vivado_version $current_vivado_version] > 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2042 -severity "ERROR" " This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Sourcing the script failed since it was created with a future version of Vivado."}
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} else {
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source zedboard_script.tcl
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# The design that will be created by this Tcl script contains the following
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# module references:
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# uart_mux
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# Please add the sources of those modules before sourcing this Tcl script.
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xc7z020clg484-1
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set_property BOARD_PART digilentinc.com:zedboard:part0:1.1 [current_project]
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name zedboard
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:processing_system7:5.5\
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xilinx.com:ip:axi_uartlite:2.0\
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xilinx.com:ip:proc_sys_reset:5.0\
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xilinx.com:ip:axi_uart16550:2.0\
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xilinx.com:ip:xlconcat:2.1\
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xilinx.com:ip:xlslice:1.0\
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xilinx.com:ip:xlconstant:1.1\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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##################################################################
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# CHECK Modules
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##################################################################
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set bCheckModules 1
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if { $bCheckModules == 1 } {
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set list_check_mods "\
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uart_mux\
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"
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set list_mods_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
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foreach mod_vlnv $list_check_mods {
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if { [can_resolve_reference $mod_vlnv] == 0 } {
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lappend list_mods_missing $mod_vlnv
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}
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}
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if { $list_mods_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
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common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
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set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
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# Create ports
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set LEDS [ create_bd_port -dir O -from 7 -to 0 LEDS ]
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set SWITCHES [ create_bd_port -dir I -from 7 -to 0 SWITCHES ]
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set BTTNS [ create_bd_port -dir I -from 4 -to 0 BTTNS ]
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set UART_txd [ create_bd_port -dir O UART_txd ]
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set UART_rxd [ create_bd_port -dir I UART_rxd ]
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set TTC0_WAVEOUT [ create_bd_port -dir O TTC0_WAVEOUT ]
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# Create instance: processing_system7_0, and set properties
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set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
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set_property -dict [list \
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CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \
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CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
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CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
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CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
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CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
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CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
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CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \
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CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \
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CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \
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CONFIG.PCW_CLK0_FREQ {100000000} \
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CONFIG.PCW_CLK1_FREQ {10000000} \
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CONFIG.PCW_CLK2_FREQ {10000000} \
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CONFIG.PCW_CLK3_FREQ {10000000} \
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CONFIG.PCW_CORE0_FIQ_INTR {0} \
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CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
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CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
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CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
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CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
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CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \
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CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
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CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
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CONFIG.PCW_ENET0_RESET_ENABLE {0} \
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CONFIG.PCW_ENET_RESET_ENABLE {1} \
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CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
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CONFIG.PCW_EN_EMIO_GPIO {1} \
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CONFIG.PCW_EN_EMIO_TTC0 {1} \
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CONFIG.PCW_EN_EMIO_TTC1 {0} \
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CONFIG.PCW_EN_EMIO_UART0 {1} \
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CONFIG.PCW_EN_EMIO_WP_SDIO0 {1} \
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CONFIG.PCW_EN_ENET0 {1} \
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CONFIG.PCW_EN_GPIO {1} \
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CONFIG.PCW_EN_QSPI {1} \
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CONFIG.PCW_EN_SDIO0 {1} \
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CONFIG.PCW_EN_TTC0 {1} \
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CONFIG.PCW_EN_TTC1 {0} \
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CONFIG.PCW_EN_UART0 {1} \
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CONFIG.PCW_EN_UART1 {1} \
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CONFIG.PCW_EN_USB0 {1} \
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CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
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CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
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CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
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CONFIG.PCW_GPIO_EMIO_GPIO_IO {64} \
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CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
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CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
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CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
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CONFIG.PCW_I2C_RESET_ENABLE {1} \
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CONFIG.PCW_IRQ_F2P_INTR {1} \
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CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_0_PULLUP {enabled} \
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CONFIG.PCW_MIO_0_SLEW {slow} \
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CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_10_PULLUP {enabled} \
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CONFIG.PCW_MIO_10_SLEW {slow} \
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CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_11_PULLUP {enabled} \
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CONFIG.PCW_MIO_11_SLEW {slow} \
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CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_12_PULLUP {enabled} \
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CONFIG.PCW_MIO_12_SLEW {slow} \
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CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_13_PULLUP {enabled} \
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CONFIG.PCW_MIO_13_SLEW {slow} \
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CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_14_PULLUP {enabled} \
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CONFIG.PCW_MIO_14_SLEW {slow} \
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CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_15_PULLUP {enabled} \
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CONFIG.PCW_MIO_15_SLEW {slow} \
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CONFIG.PCW_MIO_16_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_16_PULLUP {disabled} \
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CONFIG.PCW_MIO_16_SLEW {fast} \
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CONFIG.PCW_MIO_17_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_17_PULLUP {disabled} \
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CONFIG.PCW_MIO_17_SLEW {fast} \
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CONFIG.PCW_MIO_18_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_18_PULLUP {disabled} \
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CONFIG.PCW_MIO_18_SLEW {fast} \
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CONFIG.PCW_MIO_19_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_19_PULLUP {disabled} \
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CONFIG.PCW_MIO_19_SLEW {fast} \
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CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \
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CONFIG.PCW_MIO_1_PULLUP {disabled} \
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CONFIG.PCW_MIO_1_SLEW {fast} \
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CONFIG.PCW_MIO_20_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_20_PULLUP {disabled} \
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CONFIG.PCW_MIO_20_SLEW {fast} \
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CONFIG.PCW_MIO_21_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_21_PULLUP {disabled} \
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CONFIG.PCW_MIO_21_SLEW {fast} \
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CONFIG.PCW_MIO_22_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_22_PULLUP {disabled} \
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CONFIG.PCW_MIO_22_SLEW {fast} \
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CONFIG.PCW_MIO_23_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_23_PULLUP {disabled} \
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CONFIG.PCW_MIO_23_SLEW {fast} \
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CONFIG.PCW_MIO_24_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_24_PULLUP {disabled} \
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CONFIG.PCW_MIO_24_SLEW {fast} \
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CONFIG.PCW_MIO_25_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_25_PULLUP {disabled} \
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CONFIG.PCW_MIO_25_SLEW {fast} \
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CONFIG.PCW_MIO_26_IOTYPE {HSTL 1.8V} \
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CONFIG.PCW_MIO_26_PULLUP {disabled} \
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CONFIG.PCW_MIO_26_SLEW {fast} \
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CONFIG.PCW_MIO_27_IOTYPE {HSTL 1.8V} \
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|
CONFIG.PCW_MIO_27_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_27_SLEW {fast} \
|
|
CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_28_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_28_SLEW {fast} \
|
|
CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_29_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_29_SLEW {fast} \
|
|
CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_2_SLEW {fast} \
|
|
CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_30_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_30_SLEW {fast} \
|
|
CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_31_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_31_SLEW {fast} \
|
|
CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_32_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_32_SLEW {fast} \
|
|
CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_33_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_33_SLEW {fast} \
|
|
CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_34_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_34_SLEW {fast} \
|
|
CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_35_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_35_SLEW {fast} \
|
|
CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_36_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_36_SLEW {fast} \
|
|
CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_37_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_37_SLEW {fast} \
|
|
CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_38_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_38_SLEW {fast} \
|
|
CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_39_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_39_SLEW {fast} \
|
|
CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_3_SLEW {fast} \
|
|
CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_40_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_40_SLEW {fast} \
|
|
CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_41_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_41_SLEW {fast} \
|
|
CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_42_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_42_SLEW {fast} \
|
|
CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_43_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_43_SLEW {fast} \
|
|
CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_44_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_44_SLEW {fast} \
|
|
CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_45_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_45_SLEW {fast} \
|
|
CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_46_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_46_SLEW {slow} \
|
|
CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_47_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_47_SLEW {slow} \
|
|
CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_48_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_48_SLEW {slow} \
|
|
CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_49_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_49_SLEW {slow} \
|
|
CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_4_SLEW {fast} \
|
|
CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_50_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_50_SLEW {slow} \
|
|
CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_51_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_51_SLEW {slow} \
|
|
CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_52_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_52_SLEW {slow} \
|
|
CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_MIO_53_PULLUP {disabled} \
|
|
CONFIG.PCW_MIO_53_SLEW {slow} \
|
|
CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_5_SLEW {fast} \
|
|
CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_6_SLEW {fast} \
|
|
CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_7_SLEW {slow} \
|
|
CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_8_SLEW {fast} \
|
|
CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \
|
|
CONFIG.PCW_MIO_9_PULLUP {enabled} \
|
|
CONFIG.PCW_MIO_9_SLEW {slow} \
|
|
CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0#Enet\
|
|
0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#UART 1#UART 1#GPIO#GPIO#GPIO#GPIO}\
|
|
\
|
|
CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#tx#rx#gpio[50]#gpio[51]#gpio[52]#gpio[53]}\
|
|
\
|
|
CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
|
|
CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \
|
|
CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \
|
|
CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
|
|
CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \
|
|
CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \
|
|
CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \
|
|
CONFIG.PCW_SD0_GRP_WP_ENABLE {1} \
|
|
CONFIG.PCW_SD0_GRP_WP_IO {EMIO} \
|
|
CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \
|
|
CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_TTC0_TTC0_IO {EMIO} \
|
|
CONFIG.PCW_TTC1_PERIPHERAL_ENABLE {0} \
|
|
CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \
|
|
CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_UART0_UART0_IO {EMIO} \
|
|
CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \
|
|
CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \
|
|
CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \
|
|
CONFIG.PCW_UART_PERIPHERAL_VALID {1} \
|
|
CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.176} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.159} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.162} \
|
|
CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.187} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.073} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.034} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.03} \
|
|
CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.082} \
|
|
CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \
|
|
CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K128M16 JT-125} \
|
|
CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \
|
|
CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \
|
|
CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \
|
|
CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \
|
|
CONFIG.PCW_USB0_RESET_ENABLE {1} \
|
|
CONFIG.PCW_USB0_RESET_IO {MIO 46} \
|
|
CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \
|
|
CONFIG.PCW_USB_RESET_ENABLE {1} \
|
|
CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \
|
|
CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
|
|
] $processing_system7_0
|
|
|
|
|
|
# Create instance: axi_uartlite_0, and set properties
|
|
set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.C_BAUDRATE {115200} \
|
|
CONFIG.UARTLITE_BOARD_INTERFACE {Custom} \
|
|
CONFIG.USE_BOARD_FLOW {true} \
|
|
] $axi_uartlite_0
|
|
|
|
|
|
# Create instance: ps7_0_axi_periph, and set properties
|
|
set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ]
|
|
set_property CONFIG.NUM_MI {2} $ps7_0_axi_periph
|
|
|
|
|
|
# Create instance: rst_ps7_0_100M, and set properties
|
|
set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ]
|
|
|
|
# Create instance: axi_uart16550_0, and set properties
|
|
set axi_uart16550_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uart16550:2.0 axi_uart16550_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.UART_BOARD_INTERFACE {Custom} \
|
|
CONFIG.USE_BOARD_FLOW {true} \
|
|
] $axi_uart16550_0
|
|
|
|
|
|
# Create instance: IRQ_F2P, and set properties
|
|
set IRQ_F2P [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 IRQ_F2P ]
|
|
|
|
# Create instance: LEDS, and set properties
|
|
set LEDS [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 LEDS ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {7} \
|
|
CONFIG.DIN_WIDTH {16} \
|
|
] $LEDS
|
|
|
|
|
|
# Create instance: EMIO_O_0, and set properties
|
|
set EMIO_O_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 EMIO_O_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {15} \
|
|
CONFIG.DIN_WIDTH {64} \
|
|
] $EMIO_O_0
|
|
|
|
|
|
# Create instance: EMIO_O_1, and set properties
|
|
set EMIO_O_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 EMIO_O_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {47} \
|
|
CONFIG.DIN_TO {32} \
|
|
CONFIG.DIN_WIDTH {64} \
|
|
] $EMIO_O_1
|
|
|
|
|
|
# Create instance: EMIO_I, and set properties
|
|
set EMIO_I [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 EMIO_I ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {16} \
|
|
CONFIG.IN1_WIDTH {16} \
|
|
CONFIG.IN2_WIDTH {16} \
|
|
CONFIG.IN3_WIDTH {16} \
|
|
CONFIG.NUM_PORTS {4} \
|
|
] $EMIO_I
|
|
|
|
|
|
# Create instance: EMIO_I_0, and set properties
|
|
set EMIO_I_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 EMIO_I_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.IN0_WIDTH {8} \
|
|
CONFIG.IN1_WIDTH {5} \
|
|
CONFIG.IN2_WIDTH {3} \
|
|
CONFIG.NUM_PORTS {3} \
|
|
] $EMIO_I_0
|
|
|
|
|
|
# Create instance: xlconstant_0, and set properties
|
|
set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {3} \
|
|
] $xlconstant_0
|
|
|
|
|
|
# Create instance: EMIO_I_1, and set properties
|
|
set EMIO_I_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 EMIO_I_1 ]
|
|
set_property -dict [list \
|
|
CONFIG.CONST_VAL {0} \
|
|
CONFIG.CONST_WIDTH {16} \
|
|
] $EMIO_I_1
|
|
|
|
|
|
# Create instance: uart_mux_0, and set properties
|
|
set block_name uart_mux
|
|
set block_cell_name uart_mux_0
|
|
if { [catch {set uart_mux_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
} elseif { $uart_mux_0 eq "" } {
|
|
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
|
|
return 1
|
|
}
|
|
|
|
# Create instance: UART_MUX, and set properties
|
|
set UART_MUX [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 UART_MUX ]
|
|
set_property -dict [list \
|
|
CONFIG.DIN_FROM {10} \
|
|
CONFIG.DIN_TO {8} \
|
|
CONFIG.DIN_WIDTH {16} \
|
|
] $UART_MUX
|
|
|
|
|
|
# Create instance: xlconstant_1, and set properties
|
|
set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
|
|
|
|
# Create interface connections
|
|
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
|
|
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]
|
|
connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI]
|
|
connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins axi_uartlite_0/S_AXI]
|
|
connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] [get_bd_intf_pins axi_uart16550_0/S_AXI]
|
|
|
|
# Create port connections
|
|
connect_bd_net -net EMIO_O_1_Dout [get_bd_pins EMIO_O_1/Dout] [get_bd_pins EMIO_I/In2]
|
|
connect_bd_net -net In0_0_1 [get_bd_ports SWITCHES] [get_bd_pins EMIO_I_0/In0]
|
|
connect_bd_net -net In1_0_1 [get_bd_ports BTTNS] [get_bd_pins EMIO_I_0/In1]
|
|
connect_bd_net -net axi_uart16550_0_ip2intc_irpt [get_bd_pins axi_uart16550_0/ip2intc_irpt] [get_bd_pins IRQ_F2P/In1]
|
|
connect_bd_net -net axi_uart16550_0_sout [get_bd_pins axi_uart16550_0/sout] [get_bd_pins uart_mux_0/uart_2_tx]
|
|
connect_bd_net -net axi_uartlite_0_interrupt [get_bd_pins axi_uartlite_0/interrupt] [get_bd_pins IRQ_F2P/In0]
|
|
connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins uart_mux_0/uart_1_tx]
|
|
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins axi_uart16550_0/s_axi_aclk] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins uart_mux_0/sys_clk]
|
|
connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in]
|
|
connect_bd_net -net processing_system7_0_GPIO_O [get_bd_pins processing_system7_0/GPIO_O] [get_bd_pins EMIO_O_0/Din] [get_bd_pins EMIO_O_1/Din]
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connect_bd_net -net processing_system7_0_TTC0_WAVE0_OUT [get_bd_pins processing_system7_0/TTC0_WAVE0_OUT] [get_bd_ports TTC0_WAVEOUT]
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connect_bd_net -net processing_system7_0_UART0_TX [get_bd_pins processing_system7_0/UART0_TX] [get_bd_pins uart_mux_0/uart_0_tx]
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connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins axi_uart16550_0/s_axi_aresetn] [get_bd_pins ps7_0_axi_periph/M01_ARESETN]
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connect_bd_net -net rx_in_0_1 [get_bd_ports UART_rxd] [get_bd_pins uart_mux_0/rx_in]
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connect_bd_net -net uart_mux_0_tx_out [get_bd_pins uart_mux_0/tx_out] [get_bd_ports UART_txd]
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connect_bd_net -net uart_mux_0_uart_0_rx [get_bd_pins uart_mux_0/uart_0_rx] [get_bd_pins processing_system7_0/UART0_RX]
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connect_bd_net -net uart_mux_0_uart_1_rx [get_bd_pins uart_mux_0/uart_1_rx] [get_bd_pins axi_uartlite_0/rx]
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connect_bd_net -net uart_mux_0_uart_2_rx [get_bd_pins uart_mux_0/uart_2_rx] [get_bd_pins axi_uart16550_0/sin]
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connect_bd_net -net xlconcat_0_dout [get_bd_pins IRQ_F2P/dout] [get_bd_pins processing_system7_0/IRQ_F2P]
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connect_bd_net -net xlconcat_1_dout [get_bd_pins EMIO_I/dout] [get_bd_pins processing_system7_0/GPIO_I]
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connect_bd_net -net xlconcat_1_dout1 [get_bd_pins EMIO_I_0/dout] [get_bd_pins EMIO_I/In1]
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connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconstant_0/dout] [get_bd_pins EMIO_I_0/In2]
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connect_bd_net -net xlconstant_1_dout [get_bd_pins EMIO_I_1/dout] [get_bd_pins EMIO_I/In3]
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connect_bd_net -net xlconstant_1_dout1 [get_bd_pins xlconstant_1/dout] [get_bd_pins axi_uart16550_0/rin] [get_bd_pins axi_uart16550_0/dsrn] [get_bd_pins axi_uart16550_0/ctsn] [get_bd_pins axi_uart16550_0/dcdn]
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connect_bd_net -net xlslice_0_Dout [get_bd_pins LEDS/Dout] [get_bd_ports LEDS]
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connect_bd_net -net xlslice_0_Dout1 [get_bd_pins UART_MUX/Dout] [get_bd_pins uart_mux_0/sel]
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connect_bd_net -net xlslice_1_Dout [get_bd_pins EMIO_O_0/Dout] [get_bd_pins LEDS/Din] [get_bd_pins EMIO_I/In0] [get_bd_pins UART_MUX/Din]
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# Set DDR properties specified in the datasheet.
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set_property -dict [list \
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CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.410} \
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CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.411} \
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CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.341} \
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CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.358} \
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CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.025} \
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CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.028} \
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CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \
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CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.061} \
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] [get_bd_cells processing_system7_0]
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# Create address segments
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assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uart16550_0/S_AXI/Reg] -force
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assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] -force
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# Restore current instance
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current_bd_instance $oldCurInst
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validate_bd_design
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save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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