320 lines
12 KiB
Rust
320 lines
12 KiB
Rust
#![no_std]
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#![no_main]
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use core::{mem::MaybeUninit, panic::PanicInfo};
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use cortex_ar::asm::nop;
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use embassy_executor::Spawner;
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use embassy_time::{Duration, Ticker, WithTimeout};
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use embedded_hal::digital::StatefulOutputPin;
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use embedded_io::Write;
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use log::{error, info};
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use rand::{RngCore, SeedableRng};
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use zedboard::PS_CLOCK_FREQUENCY;
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use zynq7000_hal::{
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BootMode,
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clocks::Clocks,
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configure_level_shifter,
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eth::{AlignedBuffer, ClkConfigCollection, EthernetConfig, EthernetLowLevel},
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gic::{GicConfigurator, GicInterruptHelper, Interrupt},
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gpio::{GpioPins, Output, PinState},
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gtc::Gtc,
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uart::{ClkConfigRaw, Uart, UartConfig},
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};
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use zynq7000::{PsPeripherals, slcr::LevelShifterConfig};
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use zynq7000_rt::{self as _, mmu::section_attrs::SHAREABLE_DEVICE, mmu_l1_table_mut};
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const INIT_STRING: &str = "-- Zynq 7000 Zedboard Ethernet Example --\n\r";
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const MAC_ADDRESS: [u8; 6] = [0x01, 0x02, 0x03, 0x04, 0x05, 0x06];
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#[unsafe(link_section = ".uncached")]
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static RX_DESCRIPTORS: static_cell::ConstStaticCell<
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MaybeUninit<[zynq7000_hal::eth::rx_descr::Descriptor; 32]>,
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> = static_cell::ConstStaticCell::new(MaybeUninit::uninit());
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#[unsafe(link_section = ".uncached")]
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static TX_DESCRIPTORS: static_cell::ConstStaticCell<
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MaybeUninit<[zynq7000_hal::eth::tx_descr::Descriptor; 32]>,
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> = static_cell::ConstStaticCell::new(MaybeUninit::uninit());
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const NUM_RX_BUFS: usize = 32;
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const NUM_TX_BUFS: usize = 32;
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static ETH_RX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_RX_BUFS]> =
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static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_RX_BUFS]);
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static ETH_TX_BUFS: static_cell::ConstStaticCell<[AlignedBuffer; NUM_TX_BUFS]> =
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static_cell::ConstStaticCell::new([AlignedBuffer([0; zynq7000_hal::eth::MTU]); NUM_TX_BUFS]);
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/// See memory.x file. 1 MB starting at this address will be configured as uncached memory using the
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/// MMU.
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const UNCACHED_ADDR: u32 = 0x4000000;
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/// Entry point (not called like a normal main function)
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#[unsafe(no_mangle)]
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pub extern "C" fn boot_core(cpu_id: u32) -> ! {
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if cpu_id != 0 {
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panic!("unexpected CPU ID {}", cpu_id);
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}
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main();
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}
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#[embassy_executor::task]
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async fn embassy_net_task(
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mut runner: embassy_net::Runner<'static, zynq7000_hal::eth::embassy_net::Driver>,
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) -> ! {
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runner.run().await
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}
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#[embassy_executor::task]
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async fn led_task(mut mio_led: Output) -> ! {
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let mut ticker = Ticker::every(Duration::from_millis(200));
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loop {
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mio_led.toggle().unwrap();
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ticker.next().await; // Wait for the next cycle of the ticker
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}
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}
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#[embassy_executor::main]
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#[unsafe(export_name = "main")]
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async fn main(spawner: Spawner) -> ! {
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// Configure the uncached memory region using the MMU.
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mmu_l1_table_mut()
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.update(UNCACHED_ADDR, SHAREABLE_DEVICE)
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.expect("configuring uncached memory section failed");
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// Enable PS-PL level shifters.
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configure_level_shifter(LevelShifterConfig::EnableAll);
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let dp = PsPeripherals::take().unwrap();
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// Clock was already initialized by PS7 Init TCL script or FSBL, we just read it.
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let clocks = Clocks::new_from_regs(PS_CLOCK_FREQUENCY).unwrap();
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// Set up the global interrupt controller.
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let mut gic = GicConfigurator::new_with_init(dp.gicc, dp.gicd);
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gic.enable_all_interrupts();
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gic.set_all_spi_interrupt_targets_cpu0();
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gic.enable();
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unsafe {
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gic.enable_interrupts();
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}
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let mut gpio_pins = GpioPins::new(dp.gpio);
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// Set up global timer counter and embassy time driver.
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let gtc = Gtc::new(dp.gtc, clocks.arm_clocks());
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zynq7000_embassy::init(clocks.arm_clocks(), gtc);
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// Set up the UART, we are logging with it.
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let uart_clk_config = ClkConfigRaw::new_autocalc_with_error(clocks.io_clocks(), 115200)
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.unwrap()
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.0;
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let mut uart = Uart::new_with_mio(
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dp.uart_1,
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UartConfig::new_with_clk_config(uart_clk_config),
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(gpio_pins.mio.mio48, gpio_pins.mio.mio49),
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)
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.unwrap();
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uart.write_all(INIT_STRING.as_bytes()).unwrap();
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// Safety: We are not multi-threaded yet.
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unsafe {
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zynq7000_hal::log::uart_blocking::init_unsafe_single_core(
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uart,
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log::LevelFilter::Trace,
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false,
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)
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};
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let boot_mode = BootMode::new();
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info!("Boot mode: {:?}", boot_mode);
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let rx_bufs = ETH_RX_BUFS.take();
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let tx_bufs = ETH_TX_BUFS.take();
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let rx_descr = RX_DESCRIPTORS.take();
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let tx_descr = TX_DESCRIPTORS.take();
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rx_descr.write([const { zynq7000_hal::eth::rx_descr::Descriptor::new() }; 32]);
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tx_descr.write([const { zynq7000_hal::eth::tx_descr::Descriptor::new() }; 32]);
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let rx_descr_init = unsafe { rx_descr.assume_init_mut() };
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let tx_descr_init = unsafe { tx_descr.assume_init_mut() };
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// Unwraps okay, list length is not 0
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let mut rx_descr_ref =
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zynq7000_hal::eth::rx_descr::DescriptorList::new(rx_descr_init.as_mut_slice()).unwrap();
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// Create an unsafe copy for error handling.
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// let rx_descr_copy_for_error_handling = unsafe { rx_descr_ref.clone_unchecked() };
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let mut tx_descr_ref =
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zynq7000_hal::eth::tx_descr::DescriptorList::new(tx_descr_init.as_mut_slice());
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rx_descr_ref.init_with_aligned_bufs(rx_bufs.as_slice());
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tx_descr_ref.init_or_reset();
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// Unwrap okay, this is a valid peripheral.
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let eth_ll = EthernetLowLevel::new(dp.eth_0).unwrap();
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let (clk_collection, clk_errors) =
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ClkConfigCollection::calculate_for_rgmii_and_io_clock(clocks.io_clocks());
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info!(
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"Calculated RGMII clock configuration: {:?}, errors (missmatch from ideal rate in hertz): {:?}",
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clk_collection, clk_errors
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);
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// Unwrap okay, we use a standard clock config, and the clock config should never fail.
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let eth_cfg = EthernetConfig::new(
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clk_collection.cfg_100_mbps,
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zynq7000_hal::eth::calculate_mdc_clk_div(clocks.arm_clocks()).unwrap(),
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MAC_ADDRESS,
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);
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// Configures all the physical pins for ethernet operation and sets up the
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// ethernet peripheral.
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let mut eth = zynq7000_hal::eth::Ethernet::new_with_mio(
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eth_ll,
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eth_cfg,
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gpio_pins.mio.mio16,
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gpio_pins.mio.mio21,
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(
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gpio_pins.mio.mio17,
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gpio_pins.mio.mio18,
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gpio_pins.mio.mio19,
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gpio_pins.mio.mio20,
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),
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gpio_pins.mio.mio22,
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gpio_pins.mio.mio27,
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(
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gpio_pins.mio.mio23,
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gpio_pins.mio.mio24,
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gpio_pins.mio.mio25,
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gpio_pins.mio.mio26,
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),
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Some((gpio_pins.mio.mio52, gpio_pins.mio.mio53)),
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);
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eth.set_rx_buf_descriptor_base_address(rx_descr_ref.base_addr());
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eth.set_tx_buf_descriptor_base_address(tx_descr_ref.base_addr());
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let (mut phy, phy_rev) =
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zedboard::phy_marvell::Marvell88E1518Phy::new_autoprobe_addr(eth.mdio_mut()).unwrap();
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info!(
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"Detected Marvell 88E1518 PHY with revision number: {:?}",
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phy_rev
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);
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phy.reset();
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phy.restart_auto_negotiation();
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// TODO:
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// 1. PHY configuration.
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// 2. Interrupt handler for ethernet RX and TX. Need to pass the buffers and descriptors
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// to the interrupt handler.
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// 3. Create embassy-net driver and schedule it.
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//
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let bufs = zynq7000_hal::eth::embassy_net::DescriptorsAndBuffers::new(
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rx_descr_ref,
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rx_bufs,
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tx_descr_ref,
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tx_bufs,
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)
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.unwrap();
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let driver = zynq7000_hal::eth::embassy_net::Driver::new(ð, MAC_ADDRESS, bufs);
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let config = embassy_net::Config::dhcpv4(Default::default());
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static RESOURCES: static_cell::StaticCell<embassy_net::StackResources<3>> =
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static_cell::StaticCell::new();
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let mut rng = rand::rngs::SmallRng::seed_from_u64(1);
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let (stack, runner) = embassy_net::new(
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driver,
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config,
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RESOURCES.init(embassy_net::StackResources::new()),
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rng.next_u64(),
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);
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spawner.spawn(embassy_net_task(runner)).unwrap();
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let mut mio_led = Output::new_for_mio(gpio_pins.mio.mio7, PinState::Low);
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spawner.spawn(led_task(mio_led)).unwrap();
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let mut _emio_leds: [Output; 8] = [
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Output::new_for_emio(gpio_pins.emio.take(0).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(1).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(2).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(3).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(4).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(5).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(6).unwrap(), PinState::Low),
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Output::new_for_emio(gpio_pins.emio.take(7).unwrap(), PinState::Low),
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];
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loop {
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if !stack.is_link_up() {
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loop {
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let config_up_fut = stack.wait_config_up();
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let status = phy.read_copper_status();
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// TODO: How is this related to the ethernet stack link state? Should we only
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// update the link state to up once auto-negotiation is complete and the clock
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// was configured correctly?
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if status.auto_negotiation_complete() {
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let extended_status = phy.read_copper_specific_status_register_1();
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eth.configure_clock_and_speed_duplex(
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// If this has the reserved bits, what do we even do? For this example app,
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// I am going to assume this never happens..
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extended_status.speed().as_zynq7000_eth_speed().unwrap(),
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extended_status.duplex().as_zynq7000_eth_duplex(),
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&clk_collection,
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);
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eth.set_tx_rx_enable(true, true);
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}
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match config_up_fut.with_timeout(Duration::from_millis(100)).await {
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Ok(_) => break,
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Err(e) => todo!(),
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}
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}
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}
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let network_config = stack.config_v4();
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info!("Network configuration is up: DHCP config: {network_config:?}!",);
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//mio_led.toggle().unwrap();
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//ticker.next().await; // Wait for the next cycle of the ticker
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}
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _irq_handler() {
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let mut gic_helper = GicInterruptHelper::new();
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let irq_info = gic_helper.acknowledge_interrupt();
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match irq_info.interrupt() {
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Interrupt::Sgi(_) => (),
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Interrupt::Ppi(ppi_interrupt) => {
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if ppi_interrupt == zynq7000_hal::gic::PpiInterrupt::GlobalTimer {
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unsafe {
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zynq7000_embassy::on_interrupt();
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}
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}
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}
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Interrupt::Spi(spi_interrupt) => {
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if spi_interrupt == zynq7000_hal::gic::SpiInterrupt::Eth0 {
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let result = zynq7000_hal::eth::embassy_net::on_interrupt(
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zynq7000_hal::eth::EthernetId::Eth0,
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);
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// TODO: Send the result structure back to the main thread.
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}
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}
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Interrupt::Invalid(_) => (),
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Interrupt::Spurious => (),
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}
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gic_helper.end_of_interrupt(irq_info);
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _abort_handler() {
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loop {
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nop();
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}
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _undefined_handler() {
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loop {
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nop();
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}
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}
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#[unsafe(no_mangle)]
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pub extern "C" fn _prefetch_handler() {
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loop {
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nop();
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}
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}
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/// Panic handler
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#[panic_handler]
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fn panic(info: &PanicInfo) -> ! {
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error!("Panic: {info:?}");
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loop {}
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}
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