192 lines
8.5 KiB
Rust
192 lines
8.5 KiB
Rust
//! The overview of translation table memory attributes is described below.
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//!
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//!| | Memory Range | Definition in Translation Table |
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//!|-----------------------|-------------------------|-----------------------------------|
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//!| DDR | 0x00000000 - 0x3FFFFFFF | Normal write-back Cacheable |
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//!| PL | 0x40000000 - 0xBFFFFFFF | Strongly Ordered |
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//!| Reserved | 0xC0000000 - 0xDFFFFFFF | Unassigned |
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//!| Memory mapped devices | 0xE0000000 - 0xE02FFFFF | Device Memory |
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//!| Reserved | 0xE0300000 - 0xE0FFFFFF | Unassigned |
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//!| NAND, NOR | 0xE1000000 - 0xE3FFFFFF | Device memory |
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//!| SRAM | 0xE4000000 - 0xE5FFFFFF | Normal write-back Cacheable |
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//!| Reserved | 0xE6000000 - 0xF7FFFFFF | Unassigned |
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//!| AMBA APB Peripherals | 0xF8000000 - 0xF8FFFFFF | Device Memory |
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//!| Reserved | 0xF9000000 - 0xFBFFFFFF | Unassigned |
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//!| Linear QSPI - XIP | 0xFC000000 - 0xFDFFFFFF | Normal write-through cacheable |
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//!| Reserved | 0xFE000000 - 0xFFEFFFFF | Unassigned |
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//!| OCM | 0xFFF00000 - 0xFFFFFFFF | Normal inner write-back cacheable |
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//!
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//! For region 0x00000000 - 0x3FFFFFFF, a system where DDR is less than 1 GB,
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//! region after DDR and before PL is marked as undefined/reserved in translation
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//! table. In 0xF8000000 - 0xF8FFFFFF, 0xF8000C00 - 0xF8000FFF, 0xF8010000 -
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//! 0xF88FFFFF and 0xF8F03000 to 0xF8FFFFFF are reserved but due to granual size
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//! of 1 MB, it is not possible to define separate regions for them. For region
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//! 0xFFF00000 - 0xFFFFFFFF, 0xFFF00000 to 0xFFFB0000 is reserved but due to 1MB
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//! granual size, it is not possible to define separate region for it.
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pub const MAX_DDR_SIZE: usize = 0x4000_0000;
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pub const ONE_MB: usize = 0x10_0000;
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pub mod offsets {
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pub const OFFSET_DDR: usize = 0;
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pub const OFFSET_DDR_ALL_ACCESSIBLE: usize = 0x10_0000;
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pub const OFFSET_FPGA_SLAVE_0: usize = 0x4000_0000;
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pub const OFFSET_FPGA_SLAVE_1_START: usize = 0x8000_0000;
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pub const OFFSET_FPGA_SLAVE_1_END: usize = 0xC000_0000;
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pub const OFFSET_IO_PERIPHERALS_START: usize = 0xE000_0000;
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pub const OFFSET_IO_PERIPHERALS_END: usize = 0xE030_0000;
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pub const OFFSET_NAND_MEMORY: usize = 0xE100_0000;
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pub const OFFSET_NOR_MEMORY: usize = 0xE200_0000;
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pub const OFFSET_SRAM_MEMORY: usize = 0xE400_0000;
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pub const OFFSET_SMC_MEMORIES_END: usize = 0xE600_0000;
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/// 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
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/// 0xf8f03000 to 0xf8ffffff are reserved but due to granual size of
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/// 1MB, it is not possible to define separate regions for them.
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pub const OFFSET_AMBA_APB_START: usize = 0xF800_0000;
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pub const OFFSET_AMBA_APB_END: usize = 0xF900_0000;
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pub const OFFSET_QSPI_XIP_START: usize = 0xFC00_0000;
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pub const OFFSET_QSPI_XIP_END: usize = 0xFE00_0000;
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/// 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
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/// 1MB, it is not possible to define separate region for it
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pub const OFFSET_OCM_MAPPED_HIGH_START: usize = 0xFFF0_0000;
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pub const OFFSET_OCM_MAPPED_HIGH_END: u64 = 0x1_0000_0000;
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}
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pub mod segments {
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pub use super::offsets::*;
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use super::{MAX_DDR_SIZE, ONE_MB};
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/// First 1 MB of DDR has special treatment, access is dependant on SCU/OCM state.
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/// Refer to Zynq TRM UG585 p.106 for more details.
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pub const DDR_FULL_ACCESSIBLE: usize = (MAX_DDR_SIZE - ONE_MB) / ONE_MB;
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pub const FPGA_SLAVE: usize = (OFFSET_FPGA_SLAVE_1_START - OFFSET_FPGA_SLAVE_0) / ONE_MB;
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pub const UNASSIGNED_0: usize =
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(OFFSET_IO_PERIPHERALS_START - OFFSET_FPGA_SLAVE_1_END) / ONE_MB;
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pub const IO_PERIPHS: usize =
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(OFFSET_IO_PERIPHERALS_END - OFFSET_IO_PERIPHERALS_START) / ONE_MB;
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pub const UNASSIGNED_1: usize = (OFFSET_NAND_MEMORY - OFFSET_IO_PERIPHERALS_END) / ONE_MB;
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pub const NAND: usize = (OFFSET_NOR_MEMORY - OFFSET_NAND_MEMORY) / ONE_MB;
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pub const NOR: usize = (OFFSET_SRAM_MEMORY - OFFSET_NOR_MEMORY) / ONE_MB;
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pub const SRAM: usize = (OFFSET_SMC_MEMORIES_END - OFFSET_SRAM_MEMORY) / ONE_MB;
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pub const SEGMENTS_UNASSIGNED_2: usize =
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(OFFSET_AMBA_APB_START - OFFSET_SMC_MEMORIES_END) / ONE_MB;
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pub const AMBA_APB: usize = (OFFSET_AMBA_APB_END - OFFSET_AMBA_APB_START) / ONE_MB;
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pub const UNASSIGNED_3: usize = (OFFSET_QSPI_XIP_START - OFFSET_AMBA_APB_END) / ONE_MB;
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pub const QSPI_XIP: usize = (OFFSET_QSPI_XIP_END - OFFSET_QSPI_XIP_START) / ONE_MB;
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pub const UNASSIGNED_4: usize = (OFFSET_OCM_MAPPED_HIGH_START - OFFSET_QSPI_XIP_END) / ONE_MB;
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pub const OCM_MAPPED_HIGH: usize = ((OFFSET_OCM_MAPPED_HIGH_END
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- OFFSET_OCM_MAPPED_HIGH_START as u64)
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/ ONE_MB as u64) as usize;
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}
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pub mod section_attrs {
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use cortex_ar::mmu::{
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AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
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};
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pub const DDR: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: true,
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access: AccessPermissions::FullAccess,
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// Manager domain
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domain: 0b1111,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::CacheableMemory {
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inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
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outer: CacheableMemoryAttribute::WriteBackWriteAlloc,
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}
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.as_raw(),
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};
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pub const FPGA_SLAVES: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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domain: 0b0000,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::StronglyOrdered.as_raw(),
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};
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pub const SHAREABLE_DEVICE: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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domain: 0b0000,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::ShareableDevice.as_raw(),
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};
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pub const SRAM: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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domain: 0b0000,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::OuterAndInnerWriteBackNoWriteAlloc.as_raw(),
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};
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pub const QSPI_XIP: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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domain: 0b0000,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::OuterAndInnerWriteThroughNoWriteAlloc.as_raw(),
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};
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pub const OCM_MAPPED_HIGH: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::FullAccess,
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domain: 0b0000,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::CacheableMemory {
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inner: CacheableMemoryAttribute::WriteThroughNoWriteAlloc,
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outer: CacheableMemoryAttribute::NonCacheable,
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}
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.as_raw(),
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};
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pub const UNASSIGNED_RESERVED: SectionAttributes = SectionAttributes {
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non_global: false,
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p_bit: false,
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shareable: false,
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access: AccessPermissions::PermissionFault,
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domain: 0b0000,
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execute_never: false,
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memory_attrs: MemoryRegionAttributes::StronglyOrdered.as_raw(),
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};
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}
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pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;
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#[repr(C, align(16384))]
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#[cfg(feature = "rt")]
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pub struct L1Table(pub(crate) [u32; NUM_L1_PAGE_TABLE_ENTRIES]);
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/// Load the MMU translation table base address into the MMU.
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///
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/// # Safety
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///
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/// This function is unsafe because it directly writes to the MMU related registers. It has to be
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/// called once in the boot code before enabling the MMU, and it should be called while the MMU is
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/// disabled.
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#[unsafe(no_mangle)]
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#[cfg(feature = "rt")]
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unsafe extern "C" fn load_mmu_table() {
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let table_base = &crate::mmu_table::MMU_L1_PAGE_TABLE.0 as *const _ as u32;
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unsafe {
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core::arch::asm!(
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"orr {0}, {0}, #0x5B", // Outer-cacheable, WB
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"mcr p15, 0, {0}, c2, c0, 0", // Load table pointer
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inout(reg) table_base => _,
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options(nostack, preserves_flags)
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);
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}
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}
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