2022-01-30 17:16:17 +01:00
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#include "AxiPtmeConfig.h"
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#include "fsfw/serviceinterface/ServiceInterface.h"
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#include "fsfw_hal/linux/uio/UioMapper.h"
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AxiPtmeConfig::AxiPtmeConfig(object_id_t objectId, std::string axiUio, int mapNum)
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2022-10-27 14:02:34 +02:00
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: SystemObject(objectId), axiUio(std::move(axiUio)), mapNum(mapNum) {
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2022-01-30 17:16:17 +01:00
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mutex = MutexFactory::instance()->createMutex();
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if (mutex == nullptr) {
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sif::warning << "Failed to create mutex" << std::endl;
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}
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}
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AxiPtmeConfig::~AxiPtmeConfig() {}
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ReturnValue_t AxiPtmeConfig::initialize() {
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2022-08-24 17:27:47 +02:00
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ReturnValue_t result = returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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UioMapper uioMapper(axiUio, mapNum);
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result = uioMapper.getMappedAdress(&baseAddress, UioMapper::Permissions::READ_WRITE);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::writeCaduRateReg(uint8_t rateVal) {
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2022-08-24 17:27:47 +02:00
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ReturnValue_t result = returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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result = mutex->lockMutex(timeoutType, mutexTimeout);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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sif::warning << "AxiPtmeConfig::writeCaduRateReg: Failed to lock mutex" << std::endl;
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2022-08-24 17:27:47 +02:00
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return returnvalue::FAILED;
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2022-01-30 17:16:17 +01:00
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}
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*(baseAddress + CADU_BITRATE_REG) = static_cast<uint32_t>(rateVal);
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result = mutex->unlockMutex();
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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sif::warning << "AxiPtmeConfig::writeCaduRateReg: Failed to unlock mutex" << std::endl;
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2022-08-24 17:27:47 +02:00
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return returnvalue::FAILED;
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2022-01-30 17:16:17 +01:00
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::enableTxclockManipulator() {
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ReturnValue_t result = writeBit(COMMON_CONFIG_REG, true, BitPos::EN_TX_CLK_MANIPULATOR);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::disableTxclockManipulator() {
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ReturnValue_t result = writeBit(COMMON_CONFIG_REG, false, BitPos::EN_TX_CLK_MANIPULATOR);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::enableTxclockInversion() {
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ReturnValue_t result = writeBit(COMMON_CONFIG_REG, true, BitPos::INVERT_CLOCK);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::disableTxclockInversion() {
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ReturnValue_t result = writeBit(COMMON_CONFIG_REG, false, BitPos::INVERT_CLOCK);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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2023-03-17 14:51:00 +01:00
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ReturnValue_t AxiPtmeConfig::enableBatPriorityBit() {
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ReturnValue_t result = writeBit(COMMON_CONFIG_REG, true, BitPos::EN_BAT_PRIORITY);
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if (result != returnvalue::OK) {
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return result;
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}
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return returnvalue::OK;
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}
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ReturnValue_t AxiPtmeConfig::disableBatPriorityBit() {
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ReturnValue_t result = writeBit(COMMON_CONFIG_REG, false, BitPos::EN_BAT_PRIORITY);
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if (result != returnvalue::OK) {
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return result;
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}
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return returnvalue::OK;
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}
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2022-01-30 17:16:17 +01:00
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ReturnValue_t AxiPtmeConfig::writeReg(uint32_t regOffset, uint32_t writeVal) {
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ReturnValue_t result = returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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result = mutex->lockMutex(timeoutType, mutexTimeout);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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sif::warning << "AxiPtmeConfig::readReg: Failed to lock mutex" << std::endl;
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2022-08-24 17:27:47 +02:00
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return returnvalue::FAILED;
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2022-01-30 17:16:17 +01:00
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}
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*(baseAddress + regOffset / ADRESS_DIVIDER) = writeVal;
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result = mutex->unlockMutex();
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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sif::warning << "AxiPtmeConfig::readReg: Failed to unlock mutex" << std::endl;
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2022-08-24 17:27:47 +02:00
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return returnvalue::FAILED;
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2022-01-30 17:16:17 +01:00
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::readReg(uint32_t regOffset, uint32_t* readVal) {
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2022-08-24 17:27:47 +02:00
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ReturnValue_t result = returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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result = mutex->lockMutex(timeoutType, mutexTimeout);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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sif::warning << "AxiPtmeConfig::readReg: Failed to lock mutex" << std::endl;
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2022-08-24 17:27:47 +02:00
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return returnvalue::FAILED;
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2022-01-30 17:16:17 +01:00
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}
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*readVal = *(baseAddress + regOffset / ADRESS_DIVIDER);
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result = mutex->unlockMutex();
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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sif::warning << "AxiPtmeConfig::readReg: Failed to unlock mutex" << std::endl;
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2022-08-24 17:27:47 +02:00
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return returnvalue::FAILED;
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2022-01-30 17:16:17 +01:00
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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ReturnValue_t AxiPtmeConfig::writeBit(uint32_t regOffset, bool bitVal, BitPos bitPos) {
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uint32_t readVal = 0;
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ReturnValue_t result = readReg(regOffset, &readVal);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-01-31 08:09:58 +01:00
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uint32_t writeVal =
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(readVal & ~(1 << static_cast<uint32_t>(bitPos))) | bitVal << static_cast<uint32_t>(bitPos);
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2022-01-30 17:16:17 +01:00
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result = writeReg(regOffset, writeVal);
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2022-08-24 17:27:47 +02:00
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if (result != returnvalue::OK) {
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2022-01-30 17:16:17 +01:00
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return result;
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}
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2022-08-24 17:27:47 +02:00
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return returnvalue::OK;
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2022-01-30 17:16:17 +01:00
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}
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