eive-obsw/linux/ipcore/PtmeConfig.h

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#ifndef LINUX_OBC_PTMECONFIG_H_
#define LINUX_OBC_PTMECONFIG_H_
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#include <fsfw_hal/common/gpio/gpioDefinitions.h>
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#include "AxiPtmeConfig.h"
#include "fsfw/objectmanager/SystemObject.h"
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#include "fsfw/returnvalues/returnvalue.h"
#include "linux/ipcore/PtmeConfig.h"
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#include "returnvalues/classIds.h"
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/**
* @brief Class to configure donwlink specific parameters in the PTME IP core.
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*
* @author J. Meier
*/
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class PtmeConfig : public SystemObject {
public:
/**
* @brief Constructor
*
* ptmeAxiConfig Pointer to object providing access to PTME configuration registers.
*/
PtmeConfig(object_id_t opbjectId, AxiPtmeConfig* axiPtmeConfig);
virtual ~PtmeConfig();
virtual ReturnValue_t initialize() override;
/**
* @brief Changes the input frequency to the S-Band transceiver and thus the downlink rate
*
* @details This is the bitrate of the CADU clock and not the downlink which has twice the bitrate
* of the CADU clock due to the convolutional code added by the s-Band transceiver.
*/
ReturnValue_t setRate(uint32_t bitRate);
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uint32_t getRate();
/**
* @brief Will change the time the tx data signal is updated with respect to the tx clock
*
* @param invert True -> Data signal will be updated on the falling edge (not desired by the
* Syrlinks)
* False -> Data signal updated on rising edge (default configuration and desired
* by the syrlinks)
*
* @return REUTRN_OK if successful, otherwise error return value
*/
void invertTxClock(bool invert);
/**
* @brief Controls the tx clock manipulator of the PTME wrapper component
*
* @param enable Manipulator will be enabled (this is also the default configuration)
* @param disable Manipulator will be disabled
*
* @return REUTRN_OK if successful, otherwise error return value
*/
void configTxManipulator(bool enable);
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/**
* Enable the bat priority bit in the PTME wrapper component.
* Please note that a reset of the PTME is still required as specified in the documentation.
* This is done by a higher level component.
* @param enable
* @return
*/
void enableBatPriorityBit(bool enable);
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void setPollThreshold(AxiPtmeConfig::IdlePollThreshold pollThreshold);
private:
static const uint8_t INTERFACE_ID = CLASS_ID::RATE_SETTER;
//! [EXPORT] : [COMMENT] The commanded rate is not supported by the current FPGA design
static const ReturnValue_t RATE_NOT_SUPPORTED = MAKE_RETURN_CODE(0xA0);
//! [EXPORT] : [COMMENT] Bad bitrate has been commanded (e.g. 0)
static const ReturnValue_t BAD_BIT_RATE = MAKE_RETURN_CODE(0xA1);
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//! [EXPORT] : [COMMENT] Failed to invert clock and thus change the time the data is updated with
//! respect to the tx clock
static const ReturnValue_t CLK_INVERSION_FAILED = MAKE_RETURN_CODE(0xA2);
//! [EXPORT] : [COMMENT] Failed to change configuration bit of tx clock manipulator
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static const ReturnValue_t TX_MANIPULATOR_CONFIG_FAILED = MAKE_RETURN_CODE(0xA3);
// Bitrate register field is only 8 bit wide
static const uint32_t MAX_BITRATE = 0xFF;
// Bit clock frequency of PMTE IP core in Hz
static const uint32_t BIT_CLK_FREQ = 20000000;
AxiPtmeConfig* axiPtmeConfig = nullptr;
};
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#endif /* LINUX_OBC_PTMECONFIG_H_ */