introduced axi configuration interface for ptme ip core
All checks were successful
EIVE/eive-obsw/pipeline/head This commit looks good

This commit is contained in:
Jakob Meier 2022-01-25 18:55:52 +01:00
parent 38a1b496e7
commit 102385a707
11 changed files with 73 additions and 136 deletions

View File

@ -973,8 +973,7 @@ void ObjectFactory::createCcsdsComponents(LinuxLibgpioIF* gpioComIF) {
gpioComIF->addGpios(gpioCookiePdec);
new PdecHandler(objects::PDEC_HANDLER, objects::CCSDS_HANDLER, gpioComIF, gpioIds::PDEC_RESET,
std::string(q7s::UIO_PDEC_CONFIG_MEMORY), std::string(q7s::UIO_PDEC_RAM),
std::string(q7s::UIO_PDEC_REGISTERS));
q7s::UIO_PDEC_CONFIG_MEMORY, q7s::UIO_PDEC_RAM, q7s::UIO_PDEC_REGISTERS);
#if BOARD_TE0720 == 0
GpioCookie* gpioRS485Chip = new GpioCookie;

View File

@ -24,6 +24,7 @@ enum commonClassIds: uint8_t {
PLOC_MEMORY_DUMPER, //PLMEMDUMP
PDEC_HANDLER, //PDEC
CCSDS_HANDLER, //CCSDS
RATE_SETTER, //RS
ARCSEC_JSON_BASE, //JSONBASE
NVM_PARAM_BASE, //NVMB
COMMON_CLASS_ID_END // [EXPORT] : [END]

2
fsfw

@ -1 +1 @@
Subproject commit c1e0bcee6db652d6c474c87a4099e61ecf86b694
Subproject commit faf7da2743dcd30d83c3ab2f7b4d85277878e636

View File

@ -1,16 +1,14 @@
#include "PdecHandler.h"
#include <fcntl.h>
#include <sys/mman.h>
#include <cstring>
#include <sstream>
#include "OBSWConfig.h"
#include "PdecHandler.h"
#include "fsfw/ipc/QueueFactory.h"
#include "fsfw/objectmanager/ObjectManager.h"
#include "fsfw/serviceinterface/ServiceInterface.h"
#include "fsfw/tmtcservices/TmTcMessage.h"
#include "fsfw_hal/linux/uio/UioMapper.h"
PdecHandler::PdecHandler(object_id_t objectId, object_id_t tcDestinationId,
LinuxLibgpioIF* gpioComIF, gpioId_t pdecReset, std::string uioConfigMemory,
@ -44,17 +42,18 @@ ReturnValue_t PdecHandler::initialize() {
ReturnValue_t result = RETURN_OK;
result = getRegisterAddress();
UioMapper regMapper(uioRegisters);
result = regMapper.getMappedAdress(&registerBaseAddress, UioMapper::Permissions::READ_WRITE);
if (result != RETURN_OK) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
result = getConfigMemoryBaseAddress();
UioMapper configMemMapper(uioConfigMemory);
result = configMemMapper.getMappedAdress(&memoryBaseAddress, UioMapper::Permissions::READ_WRITE);
if (result != RETURN_OK) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
result = getRamBaseAddress();
UioMapper ramMapper(uioRamMemory);
result = ramMapper.getMappedAdress(&ramBaseAddress, UioMapper::Permissions::READ_WRITE);
if (result != RETURN_OK) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
@ -76,55 +75,6 @@ ReturnValue_t PdecHandler::initialize() {
MessageQueueId_t PdecHandler::getCommandQueue() const { return commandQueue->getId(); }
ReturnValue_t PdecHandler::getRegisterAddress() {
int fd = open(uioRegisters.c_str(), O_RDWR);
if (fd < 1) {
sif::warning << "PdecHandler::getRegisterAddress: Invalid UIO device file" << std::endl;
return RETURN_FAILED;
}
registerBaseAddress = static_cast<uint32_t*>(
mmap(NULL, REGISTER_MAP_SIZE, PROT_WRITE | PROT_READ, MAP_SHARED, fd, 0));
if (registerBaseAddress == MAP_FAILED) {
sif::error << "PdecHandler::getRegisterAddress: Failed to map uio address" << std::endl;
return RETURN_FAILED;
}
return RETURN_OK;
}
ReturnValue_t PdecHandler::getConfigMemoryBaseAddress() {
int fd = open(uioConfigMemory.c_str(), O_RDWR);
if (fd < 1) {
sif::warning << "PdecHandler::getConfigMemoryBaseAddress: Invalid UIO device file" << std::endl;
return RETURN_FAILED;
}
memoryBaseAddress = static_cast<uint32_t*>(
mmap(NULL, CONFIG_MEMORY_MAP_SIZE, PROT_WRITE | PROT_READ, MAP_SHARED, fd, 0));
if (memoryBaseAddress == MAP_FAILED) {
sif::error << "PdecHandler::getConfigMemoryBaseAddress: Failed to map uio address" << std::endl;
return RETURN_FAILED;
}
return RETURN_OK;
}
ReturnValue_t PdecHandler::getRamBaseAddress() {
int fd = open(uioRamMemory.c_str(), O_RDWR);
ramBaseAddress =
static_cast<uint32_t*>(mmap(NULL, RAM_MAP_SIZE, PROT_WRITE | PROT_READ, MAP_SHARED, fd, 0));
if (ramBaseAddress == MAP_FAILED) {
sif::error << "PdecHandler::getRamBaseAddress: Failed to map RAM base address" << std::endl;
return RETURN_FAILED;
}
return RETURN_OK;
}
void PdecHandler::writePdecConfig() {
PdecConfig pdecConfig;

View File

@ -231,25 +231,6 @@ class PdecHandler : public SystemObject,
*/
void readCommandQueue(void);
/**
* @brief Opens UIO device assigned to AXI to AHB converter giving access to the PDEC
* registers. The register base address will be mapped into the virtual address space.
*/
ReturnValue_t getRegisterAddress();
/**
* @brief Opens UIO device assigned to the base address of the PDEC memory space and maps the
* physical address into the virtual address space.
*/
ReturnValue_t getConfigMemoryBaseAddress();
/**
* @brief Opens UIO device assigned to the RAM section of the PDEC IP core memory map.
*
* @details A received TC segment will be written to this memory area.
*/
ReturnValue_t getRamBaseAddress();
/**
* @brief This functions writes the configuration parameters to the configuration
* section of the PDEC.

View File

@ -8,34 +8,20 @@ PtmeRateSetter::PtmeRateSetter(object_id_t objectId, PtmeAxiConfig* ptmeAxiConfi
PtmeRateSetter::~PtmeRateSetter() {}
ReturnValue_t PtmeRateSetter::initialize() {
if (ptmeAxiConfig == nullptr) {
sif::warning << "PtmeRateSetter::initialize: Invalid PtmeAxiConfig object" << std::endl;
return HasReturnvaluesIF::RETURN_FAILED;
}
return HasReturnvaluesIF::RETURN_OK;
if (ptmeAxiConfig == nullptr) {
sif::warning << "PtmeRateSetter::initialize: Invalid PtmeAxiConfig object" << std::endl;
return HasReturnvaluesIF::RETURN_FAILED;
}
return HasReturnvaluesIF::RETURN_OK;
}
ReturnValue_t PtmeRateSetter::setRate(BitRates rate) {
uint8_t rateVal = 0;
switch (rate) {
case RATE_2000KBPS:
rateVal = static_cast<uint8_t>(PtmeConfig::BIT_CLK_FREQ / 2000000 - 1);
break;
case RATE_1000KBPS:
rateVal = static_cast<uint8_t>(PtmeConfig::BIT_CLK_FREQ / 1000000 - 1);
break;
case RATE_500KBPS:
rateVal = static_cast<uint8_t>(PtmeConfig::BIT_CLK_FREQ / 500000 - 1);
break;
case RATE_200KBPS:
rateVal = static_cast<uint8_t>(PtmeConfig::BIT_CLK_FREQ / 200000 - 1);
break;
case RATE_100KBPS:
rateVal = static_cast<uint8_t>(PtmeConfig::BIT_CLK_FREQ / 100000 - 1);
break;
default:
sif::debug << "PtmeRateSetter::setRate: Unknown bit rate" << std::endl;
return HasReturnvaluesIF::RETURN_FAILED;
ReturnValue_t PtmeRateSetter::setRate(uint32_t bitRate) {
if (bitRate == 0) {
return BAD_BIT_RATE;
}
return ptmeAxiConfig->writeCaduRateReg(rateVal);
uint32_t rateVal = PtmeConfig::BIT_CLK_FREQ / bitRate - 1;
if (rateVal > 0xFF) {
return RATE_NOT_SUPPORTED;
}
return ptmeAxiConfig->writeCaduRateReg(static_cast<uint8_t>(rateVal));
}

View File

@ -16,23 +16,33 @@
*
* @author J. Meier
*/
class PtmeRateSetter: public TxRateSetterIF, public SystemObject {
public:
/**
* @brief Constructor
*
* objectId Object id of system object
* ptmeAxiConfig Pointer to object providing access to PTME configuration registers.
*/
PtmeRateSetter(object_id_t objectId, PtmeAxiConfig* ptmeAxiConfig);
virtual ~PtmeRateSetter();
class PtmeRateSetter : public TxRateSetterIF, public SystemObject, public HasReturnvaluesIF {
public:
/**
* @brief Constructor
*
* objectId Object id of system object
* ptmeAxiConfig Pointer to object providing access to PTME configuration registers.
*/
PtmeRateSetter(object_id_t objectId, PtmeAxiConfig* ptmeAxiConfig);
virtual ~PtmeRateSetter();
virtual ReturnValue_t initialize() override;
virtual ReturnValue_t setRate(BitRates rate);
virtual ReturnValue_t initialize() override;
virtual ReturnValue_t setRate(uint32_t bitRate);
private:
private:
PtmeAxiConfig* ptmeAxiConfig = nullptr;
static const uint8_t INTERFACE_ID = CLASS_ID::RATE_SETTER;
//! [EXPORT] : [COMMENT] The commanded rate is not supported by the current FPGA design
static const ReturnValue_t RATE_NOT_SUPPORTED = MAKE_RETURN_CODE(0xA0);
//! [EXPORT] : [COMMENT] Bad bitrate has been commanded (e.g. 0)
static const ReturnValue_t BAD_BIT_RATE = MAKE_RETURN_CODE(0xA1);
// Bitrate register field is only 8 bit wide
static const uint32_t MAX_BITRATE = 0xFF;
PtmeAxiConfig* ptmeAxiConfig = nullptr;
};
#endif /* LINUX_OBC_PTMERATESETTER_H_ */

View File

@ -3,15 +3,6 @@
#include "fsfw/returnvalues/HasReturnvaluesIF.h"
enum BitRates : uint32_t {
RATE_2000KBPS,
RATE_1000KBPS,
RATE_500KBPS,
RATE_400KBPS,
RATE_200KBPS,
RATE_100KBPS
};
/**
* @brief Abstract class for objects implementing the functionality to switch the
* downlink bit rate.
@ -23,7 +14,7 @@ class TxRateSetterIF {
TxRateSetterIF(){};
virtual ~TxRateSetterIF(){};
virtual ReturnValue_t setRate(BitRates bitRate) = 0;
virtual ReturnValue_t setRate(uint32_t bitRate) = 0;
};
#endif /* LINUX_OBC_TXRATESETTERIF_H_ */

View File

@ -5,6 +5,7 @@
#include "fsfw/events/EventManagerIF.h"
#include "fsfw/ipc/QueueFactory.h"
#include "fsfw/objectmanager/ObjectManager.h"
#include "fsfw/serialize/SerializeAdapter.h"
#include "fsfw/serviceinterface/ServiceInterface.h"
#include "fsfw/serviceinterface/serviceInterfaceDefintions.h"
@ -189,14 +190,21 @@ MessageQueueId_t CCSDSHandler::getRequestQueue() {
ReturnValue_t CCSDSHandler::executeAction(ActionId_t actionId, MessageQueueId_t commandedBy,
const uint8_t* data, size_t size) {
ReturnValue_t result = RETURN_OK;
switch (actionId) {
case SET_LOW_RATE: {
txRateSetterIF->setRate(BitRates::RATE_100KBPS);
return EXECUTION_FINISHED;
result = txRateSetterIF->setRate(RATE_100KBPS);
break;
}
case SET_HIGH_RATE: {
txRateSetterIF->setRate(BitRates::RATE_500KBPS);
return EXECUTION_FINISHED;
result = txRateSetterIF->setRate(RATE_500KBPS);
break;
}
case ARBITRARY_RATE: {
uint32_t bitrate = 0;
SerializeAdapter::deSerialize(&bitrate, &data, &size, SerializeIF::Endianness::BIG);
result = txRateSetterIF->setRate(bitrate);
break;
}
case EN_TRANSMITTER: {
enableTransmit();
@ -209,6 +217,10 @@ ReturnValue_t CCSDSHandler::executeAction(ActionId_t actionId, MessageQueueId_t
default:
return COMMAND_NOT_IMPLEMENTED;
}
if (result != RETURN_OK) {
return result;
}
return EXECUTION_FINISHED;
}
void CCSDSHandler::checkEvents() {

View File

@ -88,6 +88,13 @@ class CCSDSHandler : public SystemObject,
static const ActionId_t SET_HIGH_RATE = 1;
static const ActionId_t EN_TRANSMITTER = 2;
static const ActionId_t DIS_TRANSMITTER = 3;
static const ActionId_t ARBITRARY_RATE = 4;
// Syrlinks supports two bitrates (200 kbps and 1000 kbps)
// Due to convolutional code added by the syrlinks the input frequency must be half the
// target frequency
static const uint32_t RATE_100KBPS = 100000;
static const uint32_t RATE_500KBPS = 500000;
//! [EXPORT] : [COMMENT] Received action message with unknown action id
static const ReturnValue_t COMMAND_NOT_IMPLEMENTED = MAKE_RETURN_CODE(0xA0);

2
tmtc

@ -1 +1 @@
Subproject commit 580ac8b2d7e73aa860f3de55066187d7684d2d64
Subproject commit 598635ee4fb1eb246980564ae9f3a0feb1f4da30