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Merge pull request 'Change PDEC addresses' (#813) from pdec-changed-addrs into main
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Reviewed-on: #813
Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de>
This commit is contained in:
Robin Müller 2023-10-30 15:54:37 +01:00
commit 43af25891c
9 changed files with 56 additions and 29 deletions
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6
CHANGELOG.md
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@ -16,6 +16,12 @@ will consitute of a breaking change warranting a new major release:
# [unreleased]
## Changed
- Changed PDEC addresses depending on which firmware version is used. It is suspected that
the previous addresses were invalid and not properly covered by the Linux memory protection.
The OBSW will use the old addresses for older FW versions.
# [v7.2.0] 2023-10-27
- `eive-tmtc` v5.10.1

3
bsp_q7s/boardconfig/busConf.h
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@ -18,7 +18,8 @@ static constexpr char I2C_Q7_EIVE[] = "/dev/i2c_q7";
static constexpr char UART_GNSS_DEV[] = "/dev/gps0";
static constexpr char UART_PLOC_MPSOC_DEV[] = "/dev/ul_plmpsoc";
static constexpr char UART_PLOC_SUPERVSIOR_DEV[] = "/dev/ploc_supv";
static constexpr char UART_PLOC_SUPERVISOR_DEV_FALLBACK[] = "/dev/ttyUL4";
static constexpr char UART_PLOC_SUPERVISOR_DEV[] = "/dev/ploc_supv";
static constexpr char UART_SYRLINKS_DEV[] = "/dev/ul_syrlinks";
static constexpr char UART_STAR_TRACKER_DEV[] = "/dev/ul_str";
static constexpr char UART_SCEX_DEV[] = "/dev/scex";

4
bsp_q7s/em/emObjectFactory.cpp
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@ -163,8 +163,8 @@ void ObjectFactory::produce(void* args) {
#if OBSW_ADD_CCSDS_IP_CORES == 1
CcsdsIpCoreHandler* ipCoreHandler = nullptr;
CcsdsComponentArgs ccsdsArgs(*gpioComIF, *ipcStore, *tmStore, stores, *pusFunnel, *cfdpFunnel,
&ipCoreHandler);
createCcsdsIpComponentsAddTmRouting(ccsdsArgs);
&ipCoreHandler, 0, 0);
createCcsdsIpComponentsWrapper(ccsdsArgs);
#endif /* OBSW_ADD_CCSDS_IP_CORES == 1 */
/* Test Task */

4
bsp_q7s/fmObjectFactory.cpp
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@ -115,8 +115,8 @@ void ObjectFactory::produce(void* args) {
#if OBSW_ADD_CCSDS_IP_CORES == 1
CcsdsIpCoreHandler* ipCoreHandler = nullptr;
CcsdsComponentArgs ccsdsArgs(*gpioComIF, *ipcStore, *tmStore, stores, *pusFunnel, *cfdpFunnel,
&ipCoreHandler);
createCcsdsIpComponentsAddTmRouting(ccsdsArgs);
&ipCoreHandler, 0, 0);
createCcsdsIpComponentsWrapper(ccsdsArgs);
#endif /* OBSW_ADD_CCSDS_IP_CORES == 1 */
#if OBSW_ADD_SCEX_DEVICE == 1

16
bsp_q7s/objectFactory.cpp
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@ -642,8 +642,12 @@ void ObjectFactory::createPayloadComponents(LinuxLibgpioIF* gpioComIF, PowerSwit
auto supvGpioCookie = new GpioCookie;
supvGpioCookie->addGpio(gpioIds::ENABLE_SUPV_UART, gpioConfigSupv);
gpioComIF->addGpios(supvGpioCookie);
const char* plocSupvDev = q7s::UART_PLOC_SUPERVISOR_DEV;
if(not std::filesystem::exists(plocSupvDev)) {
plocSupvDev = q7s::UART_PLOC_SUPERVISOR_DEV_FALLBACK;
}
auto supervisorCookie = new SerialCookie(objects::PLOC_SUPERVISOR_HANDLER,
q7s::UART_PLOC_SUPERVSIOR_DEV, serial::PLOC_SUPV_BAUD,
plocSupvDev, serial::PLOC_SUPV_BAUD,
supv::MAX_PACKET_SIZE * 20, UartModes::NON_CANONICAL);
supervisorCookie->setNoFixedSizeReply();
auto supvHelper = new PlocSupvUartManager(objects::PLOC_SUPERVISOR_HELPER);
@ -836,7 +840,7 @@ ReturnValue_t ObjectFactory::createCcsdsComponents(CcsdsComponentArgs& args) {
uioNames.registers = q7s::UIO_PDEC_REGISTERS;
uioNames.irq = q7s::UIO_PDEC_IRQ;
new PdecHandler(objects::PDEC_HANDLER, objects::CCSDS_HANDLER, &args.gpioComIF,
gpioIds::PDEC_RESET, uioNames);
gpioIds::PDEC_RESET, uioNames, args.pdecCfgMemBaseAddr, args.pdecRamBaseAddr);
GpioCookie* gpioRS485Chip = new GpioCookie;
gpio = new GpiodRegularByLineName(q7s::gpioNames::RS485_EN_TX_CLOCK, "RS485 Transceiver",
Direction::OUT, Levels::LOW);
@ -1062,7 +1066,13 @@ ReturnValue_t ObjectFactory::readFirmwareVersion() {
return returnvalue::OK;
}
ReturnValue_t ObjectFactory::createCcsdsIpComponentsAddTmRouting(CcsdsComponentArgs& ccsdsArgs) {
ReturnValue_t ObjectFactory::createCcsdsIpComponentsWrapper(CcsdsComponentArgs& ccsdsArgs) {
ccsdsArgs.pdecCfgMemBaseAddr = config::pdec::PDEC_CONFIG_BASE_ADDR;
ccsdsArgs.pdecRamBaseAddr = config::pdec::PDEC_RAM_ADDR;
if (core::FW_VERSION_MAJOR < 6) {
ccsdsArgs.pdecCfgMemBaseAddr = config::pdec::PDEC_CONFIG_BASE_ADDR_LEGACY;
ccsdsArgs.pdecRamBaseAddr = config::pdec::PDEC_RAM_ADDR_LEGACY;
}
ReturnValue_t result = createCcsdsComponents(ccsdsArgs);
#if OBSW_TM_TO_PTME == 1
if (ccsdsArgs.normalLiveTmDest != MessageQueueIF::NO_QUEUE) {

11
bsp_q7s/objectFactory.h
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@ -31,14 +31,17 @@ namespace ObjectFactory {
struct CcsdsComponentArgs {
CcsdsComponentArgs(LinuxLibgpioIF& gpioIF, StorageManagerIF& ipcStore, StorageManagerIF& tmStore,
PersistentTmStores& stores, PusTmFunnel& pusFunnel, CfdpTmFunnel& cfdpFunnel,
CcsdsIpCoreHandler** ipCoreHandler)
CcsdsIpCoreHandler** ipCoreHandler, uint32_t pdecCfgMemBaseAddr,
uint32_t pdecRamBaseAddr)
: gpioComIF(gpioIF),
ipcStore(ipcStore),
tmStore(tmStore),
stores(stores),
pusFunnel(pusFunnel),
cfdpFunnel(cfdpFunnel),
ipCoreHandler(ipCoreHandler) {}
ipCoreHandler(ipCoreHandler),
pdecCfgMemBaseAddr(pdecCfgMemBaseAddr),
pdecRamBaseAddr(pdecRamBaseAddr) {}
LinuxLibgpioIF& gpioComIF;
StorageManagerIF& ipcStore;
StorageManagerIF& tmStore;
@ -46,6 +49,8 @@ struct CcsdsComponentArgs {
PusTmFunnel& pusFunnel;
CfdpTmFunnel& cfdpFunnel;
CcsdsIpCoreHandler** ipCoreHandler;
uint32_t pdecCfgMemBaseAddr;
uint32_t pdecRamBaseAddr;
MessageQueueId_t normalLiveTmDest = MessageQueueIF::NO_QUEUE;
MessageQueueId_t cfdpLiveTmDest = MessageQueueIF::NO_QUEUE;
};
@ -75,7 +80,7 @@ void createSolarArrayDeploymentComponents(PowerSwitchIF& pwrSwitcher, GpioIF& gp
void createSyrlinksComponents(PowerSwitchIF* pwrSwitcher);
void createPayloadComponents(LinuxLibgpioIF* gpioComIF, PowerSwitchIF& pwrSwitcher);
void createReactionWheelComponents(LinuxLibgpioIF* gpioComIF, PowerSwitchIF* pwrSwitcher);
ReturnValue_t createCcsdsIpComponentsAddTmRouting(CcsdsComponentArgs& args);
ReturnValue_t createCcsdsIpComponentsWrapper(CcsdsComponentArgs& args);
ReturnValue_t createCcsdsComponents(CcsdsComponentArgs& args);
ReturnValue_t readFirmwareVersion();
void createMiscComponents();

12
common/config/eive/definitions.h
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@ -115,6 +115,18 @@ static constexpr float SCHED_BLOCK_10_PERIOD =
} // namespace spiSched
namespace pdec {
// Pre FW v6.0.0
static constexpr uint32_t PDEC_CONFIG_BASE_ADDR_LEGACY = 0x24000000;
static constexpr uint32_t PDEC_RAM_ADDR_LEGACY = 0x26000000;
// Post FW v6.0.0
static constexpr uint32_t PDEC_CONFIG_BASE_ADDR = 0x4000000;
static constexpr uint32_t PDEC_RAM_ADDR = 0x7000000;
} // namespace pdec
} // namespace config
#endif /* COMMON_CONFIG_DEFINITIONS_H_ */

16
linux/ipcore/PdecHandler.cpp
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@ -24,12 +24,15 @@ using namespace pdec;
uint32_t PdecHandler::CURRENT_FAR = 0;
PdecHandler::PdecHandler(object_id_t objectId, object_id_t tcDestinationId,
LinuxLibgpioIF* gpioComIF, gpioId_t pdecReset, UioNames names)
LinuxLibgpioIF* gpioComIF, gpioId_t pdecReset, UioNames names,
uint32_t cfgMemPhyAddr, uint32_t pdecRamPhyAddr)
: SystemObject(objectId),
tcDestinationId(tcDestinationId),
gpioComIF(gpioComIF),
pdecReset(pdecReset),
actionHelper(this, nullptr),
cfgMemBaseAddr(cfgMemPhyAddr),
pdecRamBaseAddr(pdecRamPhyAddr),
uioNames(names),
paramHelper(this) {
auto mqArgs = MqArgs(objectId, static_cast<void*>(this));
@ -67,7 +70,7 @@ ReturnValue_t PdecHandler::initialize() {
};
memoryBaseAddress = static_cast<uint32_t*>(
mmap(0, PDEC_CFG_MEM_SIZE, static_cast<int>(UioMapper::Permissions::READ_WRITE), MAP_SHARED,
fd, PDEC_CFG_MEM_PHY_ADDR));
fd, cfgMemBaseAddr));
if (memoryBaseAddress == nullptr) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
@ -75,7 +78,7 @@ ReturnValue_t PdecHandler::initialize() {
ramBaseAddress = static_cast<uint32_t*>(mmap(0, PDEC_RAM_SIZE,
static_cast<int>(UioMapper::Permissions::READ_WRITE),
MAP_SHARED, fd, PDEC_RAM_PHY_ADDR));
MAP_SHARED, fd, pdecRamBaseAddr));
if (ramBaseAddress == nullptr) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
@ -466,11 +469,6 @@ bool PdecHandler::newTcReceived() {
}
void PdecHandler::doPeriodicWork() {
// scuffed test code
// if(testCntr < 30) {
// triggerEvent(pdec::INVALID_TC_FRAME, FRAME_DIRTY_RETVAL);
// testCntr++;
// }
checkLocks();
}
@ -645,7 +643,7 @@ void PdecHandler::handleNewTc() {
}
ReturnValue_t PdecHandler::readTc(uint32_t& tcLength) {
uint32_t tcOffset = (*(registerBaseAddress + PDEC_BPTR_OFFSET) - PHYSICAL_RAM_BASE_ADDRESS) / 4;
uint32_t tcOffset = (*(registerBaseAddress + PDEC_BPTR_OFFSET) - pdecRamBaseAddr) / 4;
#if OBSW_DEBUG_PDEC_HANDLER == 1
sif::debug << "PdecHandler::readTc: TC offset: 0x" << std::hex << tcOffset << std::endl;

13
linux/ipcore/PdecHandler.h
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@ -52,9 +52,7 @@ class PdecHandler : public SystemObject,
public:
static constexpr dur_millis_t IRQ_TIMEOUT_MS = 500;
static constexpr uint32_t PDEC_CFG_MEM_SIZE = 0x1000;
static constexpr uint32_t PDEC_CFG_MEM_PHY_ADDR = 0x24000000;
static constexpr uint32_t PDEC_RAM_SIZE = 0x10000;
static constexpr uint32_t PDEC_RAM_PHY_ADDR = 0x26000000;
enum class Modes { POLLED, IRQ };
@ -68,7 +66,7 @@ class PdecHandler : public SystemObject,
* @param uioregsiters String of uio device file same mapped to the PDEC register space
*/
PdecHandler(object_id_t objectId, object_id_t tcDestinationId, LinuxLibgpioIF* gpioComIF,
gpioId_t pdecReset, UioNames names);
gpioId_t pdecReset, UioNames names, uint32_t cfgMemPhyAddr, uint32_t pdecRamPhyAddr);
virtual ~PdecHandler();
@ -103,12 +101,6 @@ class PdecHandler : public SystemObject,
static const size_t MAX_TC_SEGMENT_SIZE = 1017;
static const uint8_t MAP_ID_MASK = 0x3F;
#ifdef TE0720_1CFA
static const uint32_t PHYSICAL_RAM_BASE_ADDRESS = 0x32000000;
#else
static const uint32_t PHYSICAL_RAM_BASE_ADDRESS = 0x26000000;
#endif
// Expected value stored in FAR register after reset
static const uint32_t FAR_RESET = 0x7FE0;
@ -195,6 +187,9 @@ class PdecHandler : public SystemObject,
MessageQueueId_t commandedBy = MessageQueueIF::NO_QUEUE;
bool ptmeResetWithReinitializationPending = false;
uint32_t cfgMemBaseAddr;
uint32_t pdecRamBaseAddr;
UioNames uioNames;
ParameterHelper paramHelper;