Merge branch 'develop' into feature_allow_quicker_transition
All checks were successful
EIVE/eive-obsw/pipeline/pr-develop This commit looks good
All checks were successful
EIVE/eive-obsw/pipeline/pr-develop This commit looks good
This commit is contained in:
commit
8ff70462cb
@ -16,6 +16,10 @@ will consitute of a breaking change warranting a new major release:
|
||||
|
||||
# [unreleased]
|
||||
|
||||
## Changed
|
||||
|
||||
- Moved polling of all SPI parts to the same PST.
|
||||
|
||||
# [v1.33.0]
|
||||
|
||||
eive-tmtc: v2.16.2
|
||||
|
||||
@ -55,7 +55,7 @@ static constexpr uint32_t MAX_PUS_FUNNEL_QUEUE_DEPTH = 100;
|
||||
static constexpr uint32_t MAX_STORED_CMDS_UDP = 120;
|
||||
static constexpr uint32_t MAX_STORED_CMDS_TCP = 150;
|
||||
|
||||
namespace acs {
|
||||
namespace spiSched {
|
||||
|
||||
static constexpr uint32_t SCHED_BLOCK_1_SUS_READ_MS = 15;
|
||||
static constexpr uint32_t SCHED_BLOCK_2_SENSOR_READ_MS = 30;
|
||||
@ -65,6 +65,8 @@ static constexpr uint32_t SCHED_BLOCK_5_ACTUATOR_MS = 55;
|
||||
static constexpr uint32_t SCHED_BLOCK_6_IMTQ_BLOCK_2_MS = 95;
|
||||
static constexpr uint32_t SCHED_BLOCK_RTD = 150;
|
||||
static constexpr uint32_t SCHED_BLOCK_7_RW_READ_MS = 300;
|
||||
static constexpr uint32_t SCHED_BLOCK_8_PLPCDU_MS = 320;
|
||||
static constexpr uint32_t SCHED_BLOCK_9_RAD_SENS_MS = 340;
|
||||
|
||||
// 15 ms for FM
|
||||
static constexpr float SCHED_BLOCK_1_PERIOD = static_cast<float>(SCHED_BLOCK_1_SUS_READ_MS) / 400.0;
|
||||
@ -76,8 +78,10 @@ static constexpr float SCHED_BLOCK_4_PERIOD = static_cast<float>(SCHED_BLOCK_4_A
|
||||
static constexpr float SCHED_BLOCK_5_PERIOD = static_cast<float>(SCHED_BLOCK_5_ACTUATOR_MS) / 400.0;
|
||||
static constexpr float SCHED_BLOCK_6_PERIOD =
|
||||
static_cast<float>(SCHED_BLOCK_6_IMTQ_BLOCK_2_MS) / 400.0;
|
||||
static constexpr float SCHED_BLOCK_7_PERIOD = static_cast<float>(SCHED_BLOCK_7_RW_READ_MS) / 400.0;
|
||||
static constexpr float SCHED_BLOCK_RTD_PERIOD = static_cast<float>(SCHED_BLOCK_RTD) / 400.0;
|
||||
static constexpr float SCHED_BLOCK_7_PERIOD = static_cast<float>(SCHED_BLOCK_7_RW_READ_MS) / 400.0;
|
||||
static constexpr float SCHED_BLOCK_8_PERIOD = static_cast<float>(SCHED_BLOCK_8_PLPCDU_MS) / 400.0;
|
||||
static constexpr float SCHED_BLOCK_9_PERIOD = static_cast<float>(SCHED_BLOCK_9_RAD_SENS_MS) / 400.0;
|
||||
|
||||
} // namespace acs
|
||||
|
||||
|
||||
@ -30,22 +30,6 @@ ReturnValue_t pst::pstSpiAndSyrlinks(FixedTimeslotTaskIF *thisSequence) {
|
||||
#endif
|
||||
|
||||
static_cast<void>(length);
|
||||
#if OBSW_ADD_PL_PCDU == 1
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * 0, DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * 0, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * 0, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * 0, DeviceHandlerIF::GET_READ);
|
||||
#endif
|
||||
|
||||
#if OBSW_ADD_RAD_SENSORS == 1
|
||||
/* Radiation sensor */
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * 0, DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * 0.2, DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * 0.4, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * 0.6, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * 0.8, DeviceHandlerIF::GET_READ);
|
||||
#endif
|
||||
|
||||
return thisSequence->checkSequence();
|
||||
}
|
||||
@ -267,53 +251,53 @@ ReturnValue_t pst::pstTcsAndAcs(FixedTimeslotTaskIF *thisSequence, AcsPstCfg cfg
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
|
||||
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_0_N_LOC_XFYFZM_PT_XF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_1_N_LOC_XBYFZM_PT_XB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_2_N_LOC_XFYBZB_PT_YB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_3_N_LOC_XFYBZF_PT_YF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_6_R_LOC_XFYBZM_PT_XF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_7_R_LOC_XBYBZM_PT_XB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_8_R_LOC_XBYBZB_PT_YB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_9_R_LOC_XBYBZB_PT_YF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
|
||||
length * config::acs::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_1_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
}
|
||||
|
||||
if (cfg.scheduleStr) {
|
||||
@ -329,185 +313,201 @@ ReturnValue_t pst::pstTcsAndAcs(FixedTimeslotTaskIF *thisSequence, AcsPstCfg cfg
|
||||
if (cfg.scheduleAcsBoard) {
|
||||
if (enableAside) {
|
||||
// A side
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_0_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
|
||||
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::MGM_1_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
}
|
||||
if (enableBside) {
|
||||
// B side
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::MGM_2_LIS3_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
|
||||
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::MGM_3_RM3100_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
}
|
||||
if (enableAside) {
|
||||
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::GYRO_0_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_1_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
}
|
||||
if (enableBside) {
|
||||
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
length * config::spiSched::SCHED_BLOCK_2_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::GYRO_2_ADIS_HANDLER,
|
||||
length * config::acs::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
length * config::spiSched::SCHED_BLOCK_3_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::acs::SCHED_BLOCK_2_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_2_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::GYRO_3_L3G_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
}
|
||||
}
|
||||
|
||||
if (cfg.scheduleImtq) {
|
||||
// This is the MTM measurement cycle
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_1_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
||||
imtq::ComStep::DHB_OP);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_1_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
||||
imtq::ComStep::START_MEASURE_SEND);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_1_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_1_PERIOD,
|
||||
imtq::ComStep::START_MEASURE_GET);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
imtq::ComStep::READ_MEASURE_SEND);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_3_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_3_PERIOD,
|
||||
imtq::ComStep::READ_MEASURE_GET);
|
||||
}
|
||||
|
||||
thisSequence->addSlot(objects::ACS_CONTROLLER, length * config::acs::SCHED_BLOCK_4_PERIOD, 0);
|
||||
thisSequence->addSlot(objects::ACS_CONTROLLER, length * config::spiSched::SCHED_BLOCK_4_PERIOD, 0);
|
||||
|
||||
if (cfg.scheduleImtq) {
|
||||
// This is the torquing cycle.
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
imtq::ComStep::START_ACTUATE_SEND);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
imtq::ComStep::START_ACTUATE_GET);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_6_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_6_PERIOD,
|
||||
imtq::ComStep::READ_ACTUATE_SEND);
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::acs::SCHED_BLOCK_6_PERIOD,
|
||||
thisSequence->addSlot(objects::IMTQ_HANDLER, length * config::spiSched::SCHED_BLOCK_6_PERIOD,
|
||||
imtq::ComStep::READ_ACTUATE_GET);
|
||||
}
|
||||
|
||||
if (cfg.scheduleRws) {
|
||||
// this is the torquing cycle
|
||||
thisSequence->addSlot(objects::RW1, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::RW2, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::RW3, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::RW4, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::PERFORM_OPERATION);
|
||||
|
||||
thisSequence->addSlot(objects::RW1, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::RW2, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::RW3, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::RW4, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::SEND_WRITE);
|
||||
|
||||
thisSequence->addSlot(objects::RW1, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::RW2, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::RW3, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::RW4, length * config::acs::SCHED_BLOCK_5_PERIOD,
|
||||
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_5_PERIOD,
|
||||
DeviceHandlerIF::GET_WRITE);
|
||||
|
||||
thisSequence->addSlot(objects::RW1, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::RW2, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::RW3, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::RW4, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::SEND_READ);
|
||||
|
||||
thisSequence->addSlot(objects::RW1, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW1, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::RW2, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW2, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::RW3, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW3, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
thisSequence->addSlot(objects::RW4, length * config::acs::SCHED_BLOCK_7_PERIOD,
|
||||
thisSequence->addSlot(objects::RW4, length * config::spiSched::SCHED_BLOCK_7_PERIOD,
|
||||
DeviceHandlerIF::GET_READ);
|
||||
}
|
||||
|
||||
thisSequence->addSlot(objects::SPI_RTD_COM_IF, length * config::acs::SCHED_BLOCK_RTD_PERIOD, 0);
|
||||
thisSequence->addSlot(objects::SPI_RTD_COM_IF, length * config::spiSched::SCHED_BLOCK_RTD_PERIOD, 0);
|
||||
|
||||
#if OBSW_ADD_PL_PCDU == 1
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD, DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD, DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::PLPCDU_HANDLER, length * config::spiSched::SCHED_BLOCK_8_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
#endif
|
||||
|
||||
#if OBSW_ADD_RAD_SENSORS == 1
|
||||
/* Radiation sensor */
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD, DeviceHandlerIF::PERFORM_OPERATION);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD, DeviceHandlerIF::SEND_WRITE);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD, DeviceHandlerIF::GET_WRITE);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD, DeviceHandlerIF::SEND_READ);
|
||||
thisSequence->addSlot(objects::RAD_SENSOR, length * config::spiSched::SCHED_BLOCK_9_PERIOD, DeviceHandlerIF::GET_READ);
|
||||
#endif
|
||||
return returnvalue::OK;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user