Compare commits

...

8 Commits

Author SHA1 Message Date
78a7b29f8b Merge pull request 'prep v6.6.0' (#795) from prep_v6.6.0 into main
All checks were successful
EIVE/eive-obsw/pipeline/head This commit looks good
Reviewed-on: #795
2023-09-19 11:09:38 +02:00
d4a87ee789 prep v6.6.0
Some checks are pending
EIVE/eive-obsw/pipeline/head Build started...
EIVE/eive-obsw/pipeline/pr-main This commit looks good
2023-09-18 16:32:22 +02:00
34a82b6e6c Merge pull request 'PDEC DTB update' (#794) from pdec-dtb-update into main
All checks were successful
EIVE/eive-obsw/pipeline/head This commit looks good
Reviewed-on: #794
Reviewed-by: Marius Eggert <eggertm@irs.uni-stuttgart.de>
2023-09-18 16:24:57 +02:00
ca4e90ad97 important fix
All checks were successful
EIVE/eive-obsw/pipeline/pr-main This commit looks good
2023-09-13 18:13:16 +02:00
695f5fa5bc changelog
All checks were successful
EIVE/eive-obsw/pipeline/pr-main This commit looks good
2023-09-12 13:31:03 +02:00
a697368297 remove diagnostic printouts
All checks were successful
EIVE/eive-obsw/pipeline/head This commit looks good
EIVE/eive-obsw/pipeline/pr-main This commit looks good
2023-09-12 13:18:49 +02:00
d0effc50b1 Merge remote-tracking branch 'origin/main' into pdec-dtb-update 2023-09-12 13:18:33 +02:00
cdf63f0d42 PDEC DTB update
All checks were successful
EIVE/eive-obsw/pipeline/head This commit looks good
2023-09-12 12:54:24 +02:00
4 changed files with 33 additions and 13 deletions

View File

@ -16,6 +16,15 @@ will consitute of a breaking change warranting a new major release:
# [unreleased]
# [v6.6.0] 2023-09-18
## Changed
- Changed the memory initialized for the PDEC Config Memory and the PDEC RAM by using `mmap`
directly and ignoring UIO. This makes the OBSW compatible to a device tree update, where those
memory segments are marked reserved and are thus not properly accessible through the UIO API
anymore. This change should be downwards compatible to older device trees.
# [v6.5.1] 2023-09-12
- Bumped `eive-tmtc` to v5.5.0.

View File

@ -10,8 +10,8 @@
cmake_minimum_required(VERSION 3.13)
set(OBSW_VERSION_MAJOR 6)
set(OBSW_VERSION_MINOR 5)
set(OBSW_VERSION_REVISION 1)
set(OBSW_VERSION_MINOR 6)
set(OBSW_VERSION_REVISION 0)
# set(CMAKE_VERBOSE TRUE)

View File

@ -53,23 +53,30 @@ ReturnValue_t PdecHandler::initialize() {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
ReturnValue_t result = returnvalue::OK;
UioMapper regMapper(uioNames.registers);
result = regMapper.getMappedAdress(&registerBaseAddress, UioMapper::Permissions::READ_WRITE);
ReturnValue_t result =
regMapper.getMappedAdress(&registerBaseAddress, UioMapper::Permissions::READ_WRITE);
if (result != returnvalue::OK) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}
UioMapper configMemMapper(uioNames.configMemory);
result = configMemMapper.getMappedAdress(&memoryBaseAddress, UioMapper::Permissions::READ_WRITE);
if (result != returnvalue::OK) {
int fd = 0;
if ((fd = open("/dev/mem", O_RDWR | O_SYNC)) == -1) {
sif::error << "PdecHandler::initialize: Opening /dev/mem failed" << std::endl;
return ObjectManagerIF::CHILD_INIT_FAILED;
};
memoryBaseAddress = static_cast<uint32_t*>(
mmap(0, PDEC_CFG_MEM_SIZE, static_cast<int>(UioMapper::Permissions::READ_WRITE), MAP_SHARED,
fd, PDEC_CFG_MEM_PHY_ADDR));
if (memoryBaseAddress == nullptr) {
return ObjectManagerIF::CHILD_INIT_FAILED;
} else {
pdecConfig.setMemoryBaseAddress(memoryBaseAddress);
}
UioMapper ramMapper(uioNames.ramMemory);
result = ramMapper.getMappedAdress(&ramBaseAddress, UioMapper::Permissions::READ_WRITE);
if (result != returnvalue::OK) {
pdecConfig.setMemoryBaseAddress(memoryBaseAddress);
ramBaseAddress = static_cast<uint32_t*>(mmap(0, PDEC_RAM_SIZE,
static_cast<int>(UioMapper::Permissions::READ_WRITE),
MAP_SHARED, fd, PDEC_RAM_PHY_ADDR));
if (ramBaseAddress == nullptr) {
return ObjectManagerIF::CHILD_INIT_FAILED;
}

View File

@ -51,6 +51,10 @@ class PdecHandler : public SystemObject,
public ReceivesParameterMessagesIF {
public:
static constexpr dur_millis_t IRQ_TIMEOUT_MS = 500;
static constexpr uint32_t PDEC_CFG_MEM_SIZE = 0x1000;
static constexpr uint32_t PDEC_CFG_MEM_PHY_ADDR = 0x24000000;
static constexpr uint32_t PDEC_RAM_SIZE = 0x10000;
static constexpr uint32_t PDEC_RAM_PHY_ADDR = 0x26000000;
enum class Modes { POLLED, IRQ };