always add PLOC code
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Higher ACS Modes STR Only
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Update Internal Resistance
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PLOC SUPV debug mode
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Swap RTD9 and RTD11 chip selects
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Change PDEC addresses
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PL PCDU JSON update
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State of Charge FDIR improvements
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Added CFDP fault handler events
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more testing
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Reduce SUS FDIR Events
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MPSoC robustness tweaks and debug mode
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Small bugfix for Power CTRL set handling
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CFDP Source Handler Testing
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