2021-06-03 21:42:52 +02:00
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#ifndef FSFW_HAL_STM32H7_SPI_MSPINIT_H_
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#define FSFW_HAL_STM32H7_SPI_MSPINIT_H_
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2021-06-10 19:09:33 +02:00
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#include "spiDefinitions.h"
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#include "../dma.h"
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2021-06-10 21:31:21 +02:00
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2021-06-10 19:09:33 +02:00
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#include "stm32h7xx_hal_spi.h"
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#include <cstdint>
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2021-06-03 21:42:52 +02:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2021-06-10 21:31:21 +02:00
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/**
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* @brief This file provides MSP implementation for DMA, IRQ and Polling mode for the
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* SPI peripheral. This configuration is required for the SPI communication to work.
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*/
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2021-06-05 13:29:43 +02:00
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namespace spi {
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2021-06-03 21:42:52 +02:00
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2021-06-10 19:09:33 +02:00
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struct MspCfgBase {
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virtual ~MspCfgBase() = default;
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void (* cleanUpMacroWrapper) (void) = nullptr;
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void (* setupMacroWrapper) (void) = nullptr;
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GPIO_TypeDef* sckPort = nullptr;
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uint32_t sckPin = 0;
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uint8_t sckAlternateFunction = 0;
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GPIO_TypeDef* mosiPort = nullptr;
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uint32_t mosiPin = 0;
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uint8_t mosiAlternateFunction = 0;
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GPIO_TypeDef* misoPort = nullptr;
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uint32_t misoPin = 0;
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uint8_t misoAlternateFunction = 0;
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};
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struct MspPollingConfigStruct: public MspCfgBase {};
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/* A valid instance of this struct must be passed to the MSP initialization function as a void*
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argument */
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struct MspIrqConfigStruct: public MspPollingConfigStruct {
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SpiBus spiBus = SpiBus::SPI_1;
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user_handler_t spiIrqHandler = nullptr;
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user_args_t spiUserArgs = nullptr;
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IRQn_Type spiIrqNumber = SPI1_IRQn;
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// Priorities for NVIC
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// Pre-Empt priority ranging from 0 to 15. If FreeRTOS calls are used, only 5-15 are allowed
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IrqPriorities preEmptPriority = IrqPriorities::LOWEST;
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IrqPriorities subpriority = IrqPriorities::LOWEST;
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};
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/* A valid instance of this struct must be passed to the MSP initialization function as a void*
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argument */
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struct MspDmaConfigStruct: public MspIrqConfigStruct {
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void (* dmaClkEnableWrapper) (void) = nullptr;
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dma::DMAIndexes txDmaIndex;
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dma::DMAIndexes rxDmaIndex;
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dma::DMAStreams txDmaStream;
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dma::DMAStreams rxDmaStream;
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IRQn_Type txDmaIrqNumber = DMA1_Stream0_IRQn;
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IRQn_Type rxDmaIrqNumber = DMA1_Stream1_IRQn;
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// Priorities for NVIC
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IrqPriorities txPreEmptPriority = IrqPriorities::LOWEST;
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IrqPriorities rxPreEmptPriority = IrqPriorities::LOWEST;
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IrqPriorities txSubpriority = IrqPriorities::LOWEST;
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IrqPriorities rxSubpriority = IrqPriorities::LOWEST;
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};
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using msp_func_t = void (*) (SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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void getMspInitFunction(msp_func_t* init_func, MspCfgBase **args);
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void getMspDeinitFunction(msp_func_t* deinit_func, MspCfgBase **args);
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void halMspInitDma(SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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void halMspDeinitDma(SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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void halMspInitInterrupt(SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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void halMspDeinitInterrupt(SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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void halMspInitPolling(SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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void halMspDeinitPolling(SPI_HandleTypeDef* hspi, MspCfgBase* cfg);
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2021-06-05 13:29:43 +02:00
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2021-06-10 19:09:33 +02:00
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/**
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* Assign MSP init functions. Important for SPI configuration
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* @param init_func
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* @param init_args
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* @param deinit_func
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* @param deinit_args
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*/
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void setSpiDmaMspFunctions(MspDmaConfigStruct* cfg,
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msp_func_t initFunc = &spi::halMspInitDma,
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msp_func_t deinitFunc= &spi::halMspDeinitDma
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);
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void setSpiIrqMspFunctions(MspIrqConfigStruct* cfg,
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msp_func_t initFunc = &spi::halMspInitInterrupt,
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msp_func_t deinitFunc= &spi::halMspDeinitInterrupt
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);
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void setSpiPollingMspFunctions(MspPollingConfigStruct* cfg,
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msp_func_t initFunc = &spi::halMspInitPolling,
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msp_func_t deinitFunc= &spi::halMspDeinitPolling
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);
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2021-06-05 13:29:43 +02:00
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2021-06-10 19:09:33 +02:00
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void mspErrorHandler(const char* const function, const char *const message);
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2021-06-05 13:29:43 +02:00
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}
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2021-06-03 21:49:16 +02:00
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2021-06-04 15:50:02 +02:00
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2021-06-03 21:42:52 +02:00
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#ifdef __cplusplus
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}
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#endif
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#endif /* FSFW_HAL_STM32H7_SPI_MSPINIT_H_ */
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