forked from ROMEO/obsw
slip working with int driven rx
This commit is contained in:
@ -9,8 +9,13 @@
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#include <netif/slipif.h>
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#include <sys/socket.h>
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#include <xscugic.h>
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#include <xuartps.h>
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#undef XUARTPS_IXR_RXOVR
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#define XUARTPS_IXR_RXOVR 0x00000020U /**< Rx Overrun error interrupt */
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#define XUARTPS_IXR_RTRIG 0x00000001U /**< RX FIFO trigger interrupt. */
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extern "C" {
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void slipif_rxbyte_input(struct netif *netif, u8_t c);
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@ -18,22 +23,41 @@ void myInitDone(void *arg) { puts("init done"); }
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struct netif netif;
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void pollUart(void *) {
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extern XScuGic xInterruptController; /* Interrupt controller instance */
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/** this is based on XUartPs_InterruptHandler() in xuartps_intr.c*/
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void handleUARTInt(void *) {
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XUartPs_SendByte(STDOUT_BASEADDRESS, 'I');
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u32 IsrStatus;
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/*
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* Read the interrupt ID register to determine which
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* interrupt is active
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*/
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IsrStatus = XUartPs_ReadReg(STDIN_BASEADDRESS, XUARTPS_IMR_OFFSET);
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IsrStatus &= XUartPs_ReadReg(STDIN_BASEADDRESS, XUARTPS_ISR_OFFSET);
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// Onlx RX intterupts are enabled
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// We do not care which interrupt actually triggered, just get all bytes
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// available into the stack
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u32 RecievedByte;
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while (XUartPs_IsReceiveData(STDIN_BASEADDRESS)) {
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RecievedByte = XUartPs_ReadReg(STDIN_BASEADDRESS, XUARTPS_FIFO_OFFSET);
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slipif_received_byte(&netif, (u8)RecievedByte);
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}
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/* Clear the interrupt status. */
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XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_ISR_OFFSET, IsrStatus);
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}
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void forwardPackets(void *) {
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while (1) {
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if (XUartPs_IsReceiveData(STDIN_BASEADDRESS)) {
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u32 RecievedByte;
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/* Wait until there is data */
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while (XUartPs_IsReceiveData(STDIN_BASEADDRESS)) {
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RecievedByte = XUartPs_ReadReg(STDIN_BASEADDRESS, XUARTPS_FIFO_OFFSET);
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slipif_rxbyte_input(&netif, (u8)RecievedByte);
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}
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}
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vTaskDelay(pdMS_TO_TICKS(5));
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slipif_process_rxqueue(&netif);
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vTaskDelay(pdMS_TO_TICKS(10));
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}
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}
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}
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uint32_t sio_data;
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@ -41,6 +65,8 @@ sio_fd_t sio_open(u8_t devnum) { return &sio_data; }
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void sio_send(u8_t c, sio_fd_t fd) { XUartPs_SendByte(STDOUT_BASEADDRESS, c); }
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} // extern "C"
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void testIp() {
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tcpip_init(myInitDone, nullptr);
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@ -59,14 +85,38 @@ void testIp() {
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vTaskDelay(pdMS_TO_TICKS(2000));
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xTaskCreate(
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pollUart, /* The function that implements the task. */
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"uart", /* The text name assigned to the task - for debug only as it is not used by the
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kernel. */
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2048, /* The size of the stack to allocate to the task. */
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nullptr, /* The parameter passed to the task - not used in this simple case. */
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1, /* The priority assigned to the task. */
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nullptr);
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/* Install the UART Interrupt handler. */
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BaseType_t xStatus =
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XScuGic_Connect(&xInterruptController, XPAR_XUARTPS_1_INTR,
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(Xil_ExceptionHandler)handleUARTInt, nullptr);
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configASSERT(xStatus == XST_SUCCESS);
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(void)xStatus; /* Remove compiler warning if configASSERT() is not defined. */
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// Set trigger level to 62 of 64 bytes, giving interrupt some time to react
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XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_RXWM_OFFSET, 62);
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// Setting the rx timeout to n*4 -1 bits
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XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_RXTOUT_OFFSET, 50);
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// enable UART Interrupts
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u32 mask = XUARTPS_IXR_RTRIG | XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXFULL | XUARTPS_IXR_TOUT;
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/* Write the mask to the IER Register */
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XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_IER_OFFSET, mask);
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/* Write the inverse of the Mask to the IDR register */
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XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_IDR_OFFSET, (~mask));
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/* Enable the interrupt for the UART1 in the interrupt controller. */
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XScuGic_Enable(&xInterruptController, XPAR_XUARTPS_1_INTR);
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// Start task to forwad packets from ISR to IP Task
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xTaskCreate(forwardPackets, /* The function that implements the task. */
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"slip forward", /* The text name assigned to the task - for debug
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only as it is not used by the kernel. */
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1024, /* The size of the stack to allocate to the task. */
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nullptr, /* The parameter passed to the task - not used in this
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simple case. */
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4, /* The priority assigned to the task. */
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nullptr);
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puts("socket");
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