forked from ROMEO/obsw
cleanup
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44ffb09ee9
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8fa5cddc23
@ -54,7 +54,6 @@ void uart0_handle_interrupt(void *) {
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}
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void uart1_handle_interrupt(void *) {
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outbyte('R');
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u32 IsrStatus;
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/*
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@ -73,8 +72,6 @@ void uart1_handle_interrupt(void *) {
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while (XUartPs_IsReceiveData(XPS_UART1_BASEADDR)) {
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RecievedByte = XUartPs_ReadReg(XPS_UART1_BASEADDR, XUARTPS_FIFO_OFFSET);
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outbyte(RecievedByte);
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outbyte(XUartPs_ReadReg(XPS_UART1_BASEADDR, XUARTPS_ISR_OFFSET));
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xQueueSendToBackFromISR(uart1_receive_queue, &RecievedByte,
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&xHigherPriorityTaskWoken);
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}
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@ -83,8 +80,6 @@ void uart1_handle_interrupt(void *) {
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/* Clear the interrupt status. */
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XUartPs_WriteReg(XPS_UART1_BASEADDR, XUARTPS_ISR_OFFSET, IsrStatus);
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outbyte('X');
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outbyte('\n');
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/* directly yield if sending to the queue woke something in ourselves */
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portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
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}
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@ -498,8 +498,6 @@ void setup_rx_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *rxring)
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void emacps_recv_handler(void *arg)
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{
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outbyte('D');
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struct pbuf *p;
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XEmacPs_Bd *rxbdset, *curbdptr;
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struct xemac_s *xemac;
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@ -587,7 +585,6 @@ void emacps_recv_handler(void *arg)
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sys_sem_signal(&xemac->sem_rx_data_available);
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xInsideISR--;
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#endif
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outbyte('M');
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return;
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}
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@ -65,9 +65,9 @@ int main(void) {
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// printf("Booting Software\n");
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testEth();
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// testEth();
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//mission();
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mission();
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}
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static void prvSetupHardware(void) {
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@ -22,7 +22,7 @@ int _write(int fd, const char *ptr, int len) {
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return -1; // TODO error
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}
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// we only support a single debug UART, so
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// stdout and stderr are the same and go to the xiling stdout UART
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// stdout and stderr are the same and go to the xilinx stdout UART
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// We output directely to avoid loops and allow debugging (not via a write)
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if (fd < 3) {
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int todo;
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@ -94,7 +94,7 @@ void udp_echo_thread(void *_) {
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uint16_t port = ntohs(peer_addr.sin_port);
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switch (port) {
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case 8100:
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xil_printf("udp rec 8100 len: %i\n", ret);
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// xil_printf("udp rec 8100 len: %i\n", ret);
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write(uart0_fd, rec_buffer, ret);
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break;
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case 8101:
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@ -119,7 +119,7 @@ void udp_echo_thread(void *_) {
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sizeof(peer_addr));
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} else if (readable == uart0_receive_queue) {
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ret = read(uart0_fd, rec_buffer, sizeof(rec_buffer));
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xil_printf("uart got %i\n", ret);
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// xil_printf("uart got %i\n", ret);
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// Do not send empty packets
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if (ret <= 0) {
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@ -14,13 +14,25 @@ void rust_main();
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void test_hardware() {
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int fd0 = hw_device_open("uart0", 5);
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write(fd0, "uart0\n", 6);
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write(fd0, "UART0\n", 6);
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int fd1 = hw_device_open("uart1", 5);
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write(fd1, "uart1\n", 6);
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vTaskDelay(1 / portTICK_PERIOD_MS);
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uint8_t buffer[255];
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// for (int i = 0; i< sizeof(buffer); i++) {
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// buffer[i] = i;
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// }
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// write(fd0, buffer, sizeof(buffer));
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vTaskDelay(10 / portTICK_PERIOD_MS);
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write(1, "got:\n", 5);
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uint8_t buffer[100];
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int read_bytes = read(fd0, buffer, sizeof(buffer));
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write(1, buffer, read_bytes);
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read_bytes = read(fd1, buffer, sizeof(buffer));
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