25 Commits

Author SHA1 Message Date
d3af5e1519 additional adjustment to xil_eth 2024-10-17 14:00:32 +02:00
6ff33beecc adjusting xil eth to work for us 2024-10-14 14:15:07 +02:00
fd2c5a544f xilinx eth lwip version xilinx_v2024.1 2024-10-14 14:06:49 +02:00
65299e46c4 documentation 2024-10-14 13:36:46 +02:00
dd9c39af30 further cleanup 2024-10-10 16:04:18 +02:00
791428e6c0 making the linker happy 2024-10-07 16:55:20 +02:00
944e45cad2 refactoring, added second binary for sim interface, added second lwip implementation for sim interface 2024-09-30 17:38:37 +02:00
8fa5cddc23 cleanup 2024-09-09 17:37:41 +02:00
5ad8853fef uart1 IO 2024-08-29 14:48:16 +02:00
8e7424bb2f io interface; relying on patched lwip 2024-08-26 23:03:38 +02:00
ee06c79bf4 xilinx eth in own folder. found another bug/challenge with dma 2024-08-26 12:03:31 +02:00
8497fe754c cleanup 2024-08-23 12:06:35 +02:00
ae47ca8291 found it. DMA can obviously not handle fragmented pbufs to receive packets. -> debug cleanup needed 2024-08-22 18:14:51 +02:00
497e380860 RX working, still a bit messy 2024-08-20 22:38:02 +02:00
6c556b8fbf better, not done 2024-08-20 15:13:03 +02:00
2d8d8aeb0a working on RX, broke FreeRTOS 2024-08-20 11:26:27 +02:00
910553df45 added xilinx lwip drivers, outgoing is working incoming TODO 2024-08-19 16:52:10 +02:00
701d3dca7f lwip without any alloc and sending and receiving UDP via slip 2023-11-03 17:08:59 +01:00
450eeede33 lwip is back (using printf with malloc, but apart from that static) 2023-11-03 11:58:56 +01:00
1eb406074c thread safety in newlib, newer lwip, optimized ISR for UART, some more stuff 2023-10-06 17:29:07 +02:00
8bca815cd2 slip working with int driven rx 2023-09-28 18:03:02 +02:00
5c75cfa63a lwip both directions working 2023-09-26 12:46:24 +02:00
3697705319 removed features from ip stack that crash ip stack 2023-09-25 14:27:23 +02:00
69e14e14cf ip over slip outgoing works 2023-09-22 16:38:05 +02:00
2b6a8a501b WIP 2023-09-21 18:02:13 +02:00