rust/va108xx-rs
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This commit is contained in:
Robin Müller 2024-09-19 16:39:03 +02:00
parent 8434ec872d
commit c34fbb01f5
Signed by: muellerr
GPG Key ID: A649FB78196E3849
1 changed files with 6 additions and 6 deletions
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12
va108xx-hal/src/spi.rs
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@ -267,13 +267,13 @@ pub trait TransferConfigProvider {
#[derive(Copy, Clone, Debug)]
pub struct TransferConfigWithHwcs<HwCs> {
pub hw_cs: Option<HwCs>,
pub cfg: CommonTransferConfig,
pub cfg: TransferConfig,
}
/// Type erased variant of the transfer configuration. This is required to avoid generics in
/// the SPI constructor.
#[derive(Copy, Clone, Debug)]
pub struct CommonTransferConfig {
pub struct TransferConfig {
pub clk_cfg: Option<SpiClkConfig>,
pub mode: Option<Mode>,
pub sod: bool,
@ -293,7 +293,7 @@ impl TransferConfigWithHwcs<NoneT> {
) -> Self {
TransferConfigWithHwcs {
hw_cs: None,
cfg: CommonTransferConfig {
cfg: TransferConfig {
clk_cfg,
mode,
sod,
@ -314,7 +314,7 @@ impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
) -> Self {
TransferConfigWithHwcs {
hw_cs,
cfg: CommonTransferConfig {
cfg: TransferConfig {
clk_cfg,
mode,
sod,
@ -324,7 +324,7 @@ impl<HwCs: HwCsProvider> TransferConfigWithHwcs<HwCs> {
}
}
pub fn downgrade(self) -> CommonTransferConfig {
pub fn downgrade(self) -> TransferConfig {
self.cfg
}
}
@ -591,7 +591,7 @@ where
spi: SpiI,
pins: (Sck, Miso, Mosi),
spi_cfg: SpiConfig,
transfer_cfg: Option<&CommonTransferConfig>,
transfer_cfg: Option<&TransferConfig>,
) -> Self {
enable_peripheral_clock(syscfg, SpiI::PERIPH_SEL);
let SpiConfig {