fix simple example

Merge pull request 'prepare va108xx-embassy and vorago-reb1 release' (#80 ) from prepare-embassy-bsp-release into main
Reviewed-on: #80
2025-10-27 22:18:57 +01:00 · 2025-09-03 11:33:56 +02:00 · 2025-09-03 11:30:18 +02:00 · 2025-09-03 11:24:17 +02:00 · 2025-09-03 11:22:35 +02:00 · 2025-09-03 10:01:26 +02:00
175 changed files with 861 additions and 2763 deletions
--- a/.cargo/config.toml.template
+++ b/.cargo/config.toml.template
--- a/Embed.toml.template
+++ b/Embed.toml.template
--- a/README.md
+++ b/README.md
@@ -34,12 +34,15 @@ It also contains the following helper crates:
  [`RTIC`](https://rtic.rs/2/book/en/) and [`embassy`](https://github.com/embassy-rs/embassy)
  native Rust RTOSes.

+The majority of the HAL implementation and the Embassy-rs support are contained in the external
+[`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) crate.
+
 ## Using the `.cargo/config.toml` file

 Use the following command to have a starting `config.toml` file

 ```sh
-cp .cargo/def-config.toml .cargo/config.toml
+cp .cargo/config.toml.template .cargo/config.toml
 ```

 You then can adapt the `config.toml` to your needs. For example, you can configure runners
@@ -55,10 +58,27 @@ cp -rT vscode .vscode

 You can then adapt the files in `.vscode` to your needs.

+## Building projects
+
+Building an application requires the `thumbv6m-none-eabi` cross-compiler toolchain.
+If you have not installed it yet, you can do so with
+
+```sh
+rustup target add thumbv6m-none-eabi
+```
+
+After that, you can use `cargo build` to build the development version of the crate.
+For example, you can use
+
+```sh
+cargo build --example blinky
+```
+
+to build a simple blinky app.
+
 ## Flashing, running and debugging the software

-You can use CLI or VS Code for flashing, running and debugging. In any case, take
-care of installing the pre-requisites first.
+You can use CLI or VS Code for flashing, running and debugging.

 ### Using CLI with probe-rs

--- a/board-tests/Cargo.toml
+++ b/board-tests/Cargo.toml
@@ -4,16 +4,15 @@ version = "0.1.0"
 edition = "2021"

 [dependencies]
-cortex-m = { version = "0.7.6", features = ["critical-section-single-core"] }
+cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
-panic-halt = "1"
-rtt-target = "0.6"
-panic-rtt-target = "0.2"
+defmt = "1"
+defmt-rtt = "1"
+panic-probe = { version = "1", features = ["print-defmt"] }
 embedded-hal = "1"
-embedded-hal-nb = "1"
-embedded-io = "0.6"

 [dependencies.va108xx-hal]
-version = "0.11"
+version = "0.12"
 features = ["rt"]
+path = "../va108xx-hal"

--- a/board-tests/src/main.rs
+++ b/board-tests/src/main.rs
@@ -7,18 +7,21 @@

 use cortex_m_rt::entry;
 use embedded_hal::delay::DelayNs;
-use panic_rtt_target as _;
-use rtt_target::{rprintln, rtt_init_print};
+// Logging provider
+use defmt_rtt as _;
+// Panic provider
+use panic_probe as _;
 use va108xx_hal::{
-    gpio::{PinState, PinsA, PinsB},
-    pac::{self, interrupt},
+    gpio::{regs::Gpio, Input, Output, PinState, Pull},
+    pac,
+    pins::{PinsA, PinsB, Port},
    prelude::*,
    time::Hertz,
-    timer::{default_ms_irq_handler, set_up_ms_tick, CountdownTimer, InterruptConfig},
+    timer::CountdownTimer,
 };

 #[allow(dead_code)]
-#[derive(Debug)]
+#[derive(Debug, defmt::Format)]
 enum TestCase {
    // Tie PORTA[0] to PORTA[1] for these tests!
    TestBasic,
@@ -32,18 +35,18 @@ enum TestCase {
    Pulse,
    // Tie PA0, PA1 and PA3 to an oscilloscope
    DelayGpio,
+    // PA0 can be checked with an oscillsope to verify timing correctness.
    DelayMs,
 }

 #[entry]
 fn main() -> ! {
-    rtt_init_print!();
-    rprintln!("-- VA108xx Test Application --");
-    let mut dp = pac::Peripherals::take().unwrap();
+    defmt::println!("-- VA108xx Test Application --");
+    let dp = pac::Peripherals::take().unwrap();
    let cp = cortex_m::Peripherals::take().unwrap();
-    let pinsa = PinsA::new(&mut dp.sysconfig, dp.porta);
-    let pinsb = PinsB::new(&mut dp.sysconfig, dp.portb);
-    let mut led1 = pinsa.pa10.into_readable_push_pull_output();
+    let pinsa = PinsA::new(dp.porta);
+    let pinsb = PinsB::new(dp.portb);
+    let mut led1 = Output::new(pinsa.pa10, PinState::Low);
    let test_case = TestCase::DelayMs;

    match test_case {
@@ -51,20 +54,20 @@ fn main() -> ! {
        | TestCase::TestPulldown
        | TestCase::TestPullup
        | TestCase::TestMask => {
-            rprintln!(
+            defmt::info!(
                "Test case {:?}. Make sure to tie PORTA[0] to PORTA[1]",
                test_case
            );
        }
        _ => {
-            rprintln!("Test case {:?}", test_case);
+            defmt::info!("Test case {:?}", test_case);
        }
    }
    match test_case {
        TestCase::TestBasic => {
            // Tie PORTA[0] to PORTA[1] for these tests!
-            let mut out = pinsa.pa0.into_readable_push_pull_output();
-            let input = pinsa.pa1.into_floating_input();
+            let mut out = Output::new(pinsa.pa0, PinState::Low);
+            let input = Input::new_floating(pinsa.pa1);
            out.set_high();
            assert!(input.is_high());
            out.set_low();
@@ -72,73 +75,74 @@ fn main() -> ! {
        }
        TestCase::TestPullup => {
            // Tie PORTA[0] to PORTA[1] for these tests!
-            let input = pinsa.pa1.into_pull_up_input();
+            let input = Input::new_with_pull(pinsa.pa1, Pull::Up);
            assert!(input.is_high());
-            let mut out = pinsa.pa0.into_readable_push_pull_output();
+            let mut out = Output::new(pinsa.pa0, PinState::Low);
            out.set_low();
            assert!(input.is_low());
            out.set_high();
            assert!(input.is_high());
-            out.into_floating_input();
-            assert!(input.is_high());
        }
        TestCase::TestPulldown => {
            // Tie PORTA[0] to PORTA[1] for these tests!
-            let input = pinsa.pa1.into_pull_down_input();
+            let input = Input::new_with_pull(pinsa.pa1, Pull::Down);
            assert!(input.is_low());
-            let mut out = pinsa.pa0.into_push_pull_output();
+            let mut out = Output::new(pinsa.pa0, PinState::Low);
            out.set_low();
            assert!(input.is_low());
            out.set_high();
            assert!(input.is_high());
-            out.into_floating_input();
-            assert!(input.is_low());
        }
        TestCase::TestMask => {
            // Tie PORTA[0] to PORTA[1] for these tests!
-            let mut input = pinsa.pa1.into_pull_down_input();
+            // Need to test this low-level..
+            /*
+            let mut input = Input::new_with_pull(pinsa.pa1, Pull::Down);
            input.clear_datamask();
            assert!(!input.datamask());
            let mut out = pinsa.pa0.into_push_pull_output();
            out.clear_datamask();
            assert!(input.is_low_masked().is_err());
            assert!(out.set_high_masked().is_err());
+            */
        }
        TestCase::PortB => {
            // Tie PORTB[22] to PORTB[23] for these tests!
-            let mut out = pinsb.pb22.into_readable_push_pull_output();
-            let input = pinsb.pb23.into_floating_input();
+            let mut out = Output::new(pinsb.pb22, PinState::Low);
+            let input = Input::new_floating(pinsb.pb23);
            out.set_high();
            assert!(input.is_high());
            out.set_low();
            assert!(input.is_low());
        }
        TestCase::Perid => {
-            assert_eq!(PinsA::get_perid(), 0x004007e1);
-            assert_eq!(PinsB::get_perid(), 0x004007e1);
+            let mmio_porta = Gpio::new_mmio(Port::A);
+            assert_eq!(mmio_porta.read_perid(), 0x004007e1);
+            let mmio_porta = Gpio::new_mmio(Port::B);
+            assert_eq!(mmio_porta.read_perid(), 0x004007e1);
        }
        TestCase::Pulse => {
-            let mut output_pulsed = pinsa.pa0.into_push_pull_output();
+            let mut output_pulsed = Output::new(pinsa.pa0, PinState::Low);
            output_pulsed.configure_pulse_mode(true, PinState::Low);
-            rprintln!("Pulsing high 10 times..");
+            defmt::info!("Pulsing high 10 times..");
            output_pulsed.set_low();
            for _ in 0..10 {
                output_pulsed.set_high();
                cortex_m::asm::delay(25_000_000);
            }
            output_pulsed.configure_pulse_mode(true, PinState::High);
-            rprintln!("Pulsing low 10 times..");
+            defmt::info!("Pulsing low 10 times..");
            for _ in 0..10 {
                output_pulsed.set_low();
                cortex_m::asm::delay(25_000_000);
            }
        }
        TestCase::DelayGpio => {
-            let mut out_0 = pinsa.pa0.into_readable_push_pull_output();
+            let mut out_0 = Output::new(pinsa.pa0, PinState::Low);
            out_0.configure_delay(true, false);
-            let mut out_1 = pinsa.pa1.into_readable_push_pull_output();
+            let mut out_1 = Output::new(pinsa.pa1, PinState::Low);
            out_1.configure_delay(false, true);
-            let mut out_2 = pinsa.pa3.into_readable_push_pull_output();
+            let mut out_2 = Output::new(pinsa.pa3, PinState::Low);
            out_2.configure_delay(true, true);
            for _ in 0..20 {
                out_0.toggle();
@@ -148,22 +152,8 @@ fn main() -> ! {
            }
        }
        TestCase::DelayMs => {
-            let mut ms_timer = set_up_ms_tick(
-                InterruptConfig::new(pac::Interrupt::OC0, true, true),
-                &mut dp.sysconfig,
-                Some(&mut dp.irqsel),
-                50.MHz(),
-                dp.tim0,
-            );
-            for _ in 0..5 {
-                led1.toggle();
-                ms_timer.delay_ms(500);
-                led1.toggle();
-                ms_timer.delay_ms(500);
-            }
-
-            let mut delay_timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim1);
-            let mut pa0 = pinsa.pa0.into_readable_push_pull_output();
+            let mut delay_timer = CountdownTimer::new(dp.tim1, 50.MHz());
+            let mut pa0 = Output::new(pinsa.pa0, PinState::Low);
            for _ in 0..5 {
                led1.toggle();
                delay_timer.delay_ms(500);
@@ -172,30 +162,23 @@ fn main() -> ! {
            }
            let ahb_freq: Hertz = 50.MHz();
            let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.raw());
-            // Test usecond delay using both TIM peripheral and SYST. Use the release image if you
-            // want to verify the timings!
-            loop {
-                pa0.toggle();
-                delay_timer.delay_us(50);
-                pa0.toggle();
-                delay_timer.delay_us(50);
+            // Release image should be used to verify timings for pin PA0
+            for _ in 0..5 {
                pa0.toggle();
                syst_delay.delay_us(50);
                pa0.toggle();
                syst_delay.delay_us(50);
+                pa0.toggle();
+                delay_timer.delay_us(50);
+                pa0.toggle();
+                delay_timer.delay_us(50);
            }
        }
    }

-    rprintln!("Test success");
+    defmt::info!("Test success");
    loop {
        led1.toggle();
        cortex_m::asm::delay(25_000_000);
    }
 }
-
-#[interrupt]
-#[allow(non_snake_case)]
-fn OC0() {
-    default_ms_irq_handler()
-}
--- a/bootloader/Cargo.toml
+++ b/bootloader/Cargo.toml
@@ -7,7 +7,7 @@ edition = "2021"
 cortex-m = "0.7"
 cortex-m-rt = "0.7"
 embedded-hal = "1"
-defmt-rtt = "0.4"
+defmt-rtt = "1"
 defmt = "1"
 panic-probe = { version = "1", features = ["defmt"] }
 crc = "3"
@@ -15,12 +15,12 @@ num_enum = { version = "0.7", default-features = false }
 static_assertions = "1"

 [dependencies.va108xx-hal]
-version = "0.11"
+version = "0.12"
 path = "../va108xx-hal"
 features = ["defmt"]

 [dependencies.vorago-reb1]
-version = "0.8"
+version = "0.9"
 path = "../vorago-reb1"

 [features]
--- a/bootloader/README.md
+++ b/bootloader/README.md
@@ -12,8 +12,8 @@ The bootloader uses the following memory map:
 | 0x0 | Bootloader start | code up to 0x2FFE bytes |
 | 0x2FFE | Bootloader CRC | half-word |
 | 0x3000 | App image A start | code up to 0xE7F4 (~59K) bytes |
-| 0x117F8 | App image A CRC check length | word |
-| 0x117FC | App image A CRC check value | word |
+| 0x117F4 | App image A CRC check length | word |
+| 0x117F8 | App image A CRC check value | word |
 | 0x117FC | App image B start | code up to 0xE7F4 (~59K) bytes |
 | 0x1FFF0 | App image B CRC check length | word |
 | 0x1FFF4 | App image B CRC check value | word |
--- a/bootloader/src/main.rs
+++ b/bootloader/src/main.rs
@@ -10,7 +10,7 @@ use num_enum::TryFromPrimitive;
 use panic_probe as _;
 // Import logger.
 use defmt_rtt as _;
-use va108xx_hal::{pac, spi::SpiClkConfig, time::Hertz, timer::CountdownTimer};
+use va108xx_hal::{pac, spi::SpiClockConfig, time::Hertz, timer::CountdownTimer};
 use vorago_reb1::m95m01::M95M01;

 // Useful for debugging and see what the bootloader is doing. Enabled currently, because
@@ -106,7 +106,7 @@ fn main() -> ! {
    let cp = cortex_m::Peripherals::take().unwrap();
    let mut timer = CountdownTimer::new(dp.tim0, CLOCK_FREQ);

-    let clk_config = SpiClkConfig::new(2, 4);
+    let clk_config = SpiClockConfig::new(2, 4);
    let mut nvm = M95M01::new(dp.spic, clk_config);

    if FLASH_SELF {
--- a/examples/embassy/Cargo.toml
+++ b/examples/embassy/Cargo.toml
@@ -5,35 +5,35 @@ edition = "2021"

 [dependencies]
 cfg-if = "1"
-cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 cortex-m-rt = "0.7"
-embedded-hal = "1"
 embedded-hal-async = "1"
 embedded-io = "0.6"
 embedded-io-async = "0.6"
-heapless = "0.8"
+heapless = "0.9"
 static_cell = "2"

 defmt = "1"
-defmt-rtt = "0.4"
-panic-probe = { version = "0.3", features = ["print-defmt"] }
+defmt-rtt = "1"
+panic-probe = { version = "1", features = ["print-defmt"] }

 critical-section = "1"
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}

-embassy-sync = "0.6"
-embassy-time = "0.4"
-embassy-executor = { version = "0.7", features = [
+embassy-sync = "0.7"
+embassy-time = "0.5"
+embassy-executor = { version = "0.9", features = [
  "arch-cortex-m",
  "executor-thread",
  "executor-interrupt"
 ]}

-va108xx-hal = { version = "0.11", path = "../../va108xx-hal", features = ["defmt"] }
-va108xx-embassy = { version = "0.2" }
+va108xx-hal = { version = "0.12", path = "../../va108xx-hal", features = ["defmt"] }
+va108xx-embassy = { version = "0.3", path = "../../va108xx-embassy" }

 [features]
 default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]
 custom-irqs = []
 ticks-hz-1_000 = ["embassy-time/tick-hz-1_000"]
 ticks-hz-32_768 = ["embassy-time/tick-hz-32_768"]
+
+[package.metadata.cargo-machete]
+ignored = ["cortex-m-rt"]
--- a/examples/embassy/src/bin/async-gpio.rs
+++ b/examples/embassy/src/bin/async-gpio.rs
@@ -59,16 +59,10 @@ static CHANNEL_PB22_TO_PB23: Channel<ThreadModeRawMutex, GpioCmd, 3> = Channel::
 async fn main(spawner: Spawner) {
    defmt::println!("-- VA108xx Async GPIO Demo --");

-    let mut dp = pac::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();

    // Safety: Only called once here.
-    va108xx_embassy::init(
-        &mut dp.sysconfig,
-        &dp.irqsel,
-        SYSCLK_FREQ,
-        dp.tim23,
-        dp.tim22,
-    );
+    va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ);

    let porta = PinsA::new(dp.porta);
    let portb = PinsB::new(dp.portb);
--- a/examples/embassy/src/bin/async-uart-rx.rs
+++ b/examples/embassy/src/bin/async-uart-rx.rs
@@ -40,28 +40,22 @@ const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);

 static QUEUE_UART_A: static_cell::ConstStaticCell<Queue<u8, 256>> =
    static_cell::ConstStaticCell::new(Queue::new());
-static PRODUCER_UART_A: Mutex<RefCell<Option<Producer<u8, 256>>>> = Mutex::new(RefCell::new(None));
+static PRODUCER_UART_A: Mutex<RefCell<Option<Producer<u8>>>> = Mutex::new(RefCell::new(None));

 static QUEUE_UART_B: static_cell::ConstStaticCell<Queue<u8, 256>> =
    static_cell::ConstStaticCell::new(Queue::new());
-static PRODUCER_UART_B: Mutex<RefCell<Option<Producer<u8, 256>>>> = Mutex::new(RefCell::new(None));
-static CONSUMER_UART_B: Mutex<RefCell<Option<Consumer<u8, 256>>>> = Mutex::new(RefCell::new(None));
+static PRODUCER_UART_B: Mutex<RefCell<Option<Producer<u8>>>> = Mutex::new(RefCell::new(None));
+static CONSUMER_UART_B: Mutex<RefCell<Option<Consumer<u8>>>> = Mutex::new(RefCell::new(None));

 // main is itself an async function.
 #[embassy_executor::main]
 async fn main(spawner: Spawner) {
    defmt::println!("-- VA108xx Async UART RX Demo --");

-    let mut dp = pac::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();

    // Safety: Only called once here.
-    va108xx_embassy::init(
-        &mut dp.sysconfig,
-        &dp.irqsel,
-        SYSCLK_FREQ,
-        dp.tim23,
-        dp.tim22,
-    );
+    va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ);

    let porta = PinsA::new(dp.porta);
    let mut led0 = Output::new(porta.pa10, PinState::Low);
@@ -126,7 +120,7 @@ async fn main(spawner: Spawner) {
 }

 #[embassy_executor::task]
-async fn uart_b_task(mut async_rx: RxAsyncOverwriting<256>, mut tx: Tx) {
+async fn uart_b_task(mut async_rx: RxAsyncOverwriting, mut tx: Tx) {
    let mut buf = [0u8; 256];
    loop {
        defmt::info!("Current time UART B: {}", Instant::now().as_secs());
--- a/examples/embassy/src/bin/async-uart-tx.rs
+++ b/examples/embassy/src/bin/async-uart-tx.rs
@@ -39,16 +39,10 @@ const STR_LIST: &[&str] = &[
 async fn main(_spawner: Spawner) {
    defmt::println!("-- VA108xx Async UART TX Demo --");

-    let mut dp = pac::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();

    // Safety: Only called once here.
-    va108xx_embassy::init(
-        &mut dp.sysconfig,
-        &dp.irqsel,
-        SYSCLK_FREQ,
-        dp.tim23,
-        dp.tim22,
-    );
+    va108xx_embassy::init(dp.tim23, dp.tim22, SYSCLK_FREQ);

    let porta = PinsA::new(dp.porta);

--- a/examples/embassy/src/main.rs
+++ b/examples/embassy/src/main.rs
@@ -26,23 +26,21 @@ const SYSCLK_FREQ: Hertz = Hertz::from_raw(50_000_000);
 async fn main(_spawner: Spawner) {
    defmt::println!("-- VA108xx Embassy Demo --");

-    let mut dp = pac::Peripherals::take().unwrap();
+    let dp = pac::Peripherals::take().unwrap();

    // Safety: Only called once here.
    cfg_if::cfg_if! {
        if #[cfg(not(feature = "custom-irqs"))] {
            va108xx_embassy::init(
-                &mut dp.sysconfig,
-                &dp.irqsel,
-                SYSCLK_FREQ,
                dp.tim23,
                dp.tim22,
+                SYSCLK_FREQ,
            );
        } else {
            va108xx_embassy::init_with_custom_irqs(
-                SYSCLK_FREQ,
                dp.tim23,
                dp.tim22,
+                SYSCLK_FREQ,
                pac::Interrupt::OC23,
                pac::Interrupt::OC24,
            );
--- a/examples/rtic/Cargo.toml
+++ b/examples/rtic/Cargo.toml
@@ -5,23 +5,13 @@ edition = "2021"

 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
-cortex-m-rt = "0.7"
-embedded-hal = "1"
 embedded-io = "0.6"
-defmt-rtt = "0.4"
+defmt-rtt = "1"
 defmt = "1"
 panic-probe = { version = "1", features = ["defmt"] }
-
-# Even though we do not use this directly, we need to activate this feature explicitely
-# so that RTIC compiles because thumv6 does not have CAS operations natively.
-portable-atomic = { version = "1", features = ["unsafe-assume-single-core"]}
-
 rtic = { version = "2", features = ["thumbv6-backend"] }
 rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
-rtic-sync = { version = "1.3", features = ["defmt-03"] }
-
-once_cell = {version = "1", default-features = false, features = ["critical-section"]}
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }

-va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
-vorago-reb1 = { version = "0.8", path = "../../vorago-reb1" }
+va108xx-hal = { version = "0.12", path = "../../va108xx-hal" }
+vorago-reb1 = { version = "0.9", path = "../../vorago-reb1" }
--- a/examples/rtic/src/bin/blinky-button-rtic.rs
+++ b/examples/rtic/src/bin/blinky-button-rtic.rs
@@ -10,7 +10,7 @@ mod app {
    // Import global logger.
    use defmt_rtt as _;
    use va108xx_hal::{
-        clock::{set_clk_div_register, FilterClkSel},
+        clock::{set_clk_div_register, FilterClockSelect},
        gpio::{FilterType, InterruptEdge},
        pac,
        pins::PinsA,
@@ -60,8 +60,8 @@ mod app {

        if mode == PressMode::Toggle {
            // This filter debounces the switch for edge based interrupts
-            button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
-            set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
+            button.configure_filter_type(FilterType::FilterFourCycles, FilterClockSelect::Clk1);
+            set_clk_div_register(&mut dp.sysconfig, FilterClockSelect::Clk1, 50_000);
        }
        button.configure_and_enable_edge_interrupt(
            edge_irq,
--- a/examples/simple/Cargo.toml
+++ b/examples/simple/Cargo.toml
@@ -7,21 +7,15 @@ edition = "2021"
 cortex-m = {version = "0.7", features = ["critical-section-single-core"]}
 cortex-m-rt = "0.7"
 panic-halt = "1"
-critical-section = "1"
-defmt-rtt = "0.4"
+defmt-rtt = "1"
 defmt = "1"
 panic-probe = { version = "1", features = ["defmt"] }
 embedded-hal = "1"
 embedded-hal-nb = "1"
 embedded-io = "0.6"
-cortex-m-semihosting = "0.5.0"
 portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }

 [dependencies.va108xx-hal]
-version = "0.11"
+version = "0.12"
 path = "../../va108xx-hal"
 features = ["defmt"]
-
-[dependencies.vorago-reb1]
-path = "../../vorago-reb1"
-version = "0.8"
--- a/examples/simple/examples/spi.rs
+++ b/examples/simple/examples/spi.rs
@@ -14,7 +14,7 @@ use va108xx_hal::{
    pac,
    pins::{PinsA, PinsB},
    prelude::*,
-    spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClkConfig, TransferConfig},
+    spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClockConfig, TransferConfig},
    timer::CountdownTimer,
 };

@@ -45,7 +45,7 @@ fn main() -> ! {
    let dp = pac::Peripherals::take().unwrap();
    let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());

-    let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
+    let spi_clk_cfg = SpiClockConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
        .expect("creating SPI clock config failed");
    let pinsa = PinsA::new(dp.porta);
    let pinsb = PinsB::new(dp.portb);
--- a/examples/simple/examples/timer-ticks.rs
+++ b/examples/simple/examples/timer-ticks.rs
@@ -10,7 +10,6 @@ use panic_probe as _;
 use defmt_rtt as _;
 use portable_atomic::AtomicU32;
 use va108xx_hal::{
-    clock::{get_sys_clock, set_sys_clock},
    pac::{self, interrupt},
    prelude::*,
    time::Hertz,
@@ -32,7 +31,6 @@ fn main() -> ! {
    let mut delay = CountdownTimer::new(dp.tim2, 50.MHz());
    let mut last_ms = 0;
    defmt::info!("-- Vorago system ticks using timers --");
-    set_sys_clock(50.MHz());
    let lib_type = LibType::Hal;
    match lib_type {
        LibType::Pac => {
@@ -43,8 +41,8 @@ fn main() -> ! {
                dp.sysconfig
                    .tim_clk_enable()
                    .modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1)));
-                dp.irqsel.tim0(0).write(|w| w.bits(0x00));
-                dp.irqsel.tim0(1).write(|w| w.bits(0x01));
+                dp.irqsel.tim(0).write(|w| w.bits(0x00));
+                dp.irqsel.tim(1).write(|w| w.bits(0x01));
            }

            let sys_clk: Hertz = 50.MHz();
@@ -67,10 +65,10 @@ fn main() -> ! {
            }
        }
        LibType::Hal => {
-            let mut ms_timer = CountdownTimer::new(dp.tim0, get_sys_clock().unwrap());
+            let mut ms_timer = CountdownTimer::new(dp.tim0, 50.MHz());
            ms_timer.enable_interrupt(InterruptConfig::new(interrupt::OC0, true, true));
            ms_timer.start(1.kHz());
-            let mut second_timer = CountdownTimer::new(dp.tim1, get_sys_clock().unwrap());
+            let mut second_timer = CountdownTimer::new(dp.tim1, 50.MHz());
            second_timer.enable_interrupt(InterruptConfig::new(interrupt::OC1, true, true));
            second_timer.start(1.Hz());
        }
--- a/examples/simple/src/main.rs
+++ b/examples/simple/src/main.rs
@@ -3,7 +3,6 @@
 #![no_std]

 use cortex_m_rt::entry;
-use panic_probe as _;
 use va108xx_hal as _;

 #[entry]
@@ -12,3 +11,10 @@ fn main() -> ! {
        cortex_m::asm::nop();
    }
 }
+
+#[panic_handler]
+fn panic(_info: &core::panic::PanicInfo) -> ! {
+    loop {
+        cortex_m::asm::nop();
+    }
+}
--- a/flashloader/Cargo.toml
+++ b/flashloader/Cargo.toml
@@ -4,33 +4,32 @@ version = "0.1.0"
 edition = "2021"

 [dependencies]
-cortex-m = "0.7"
+cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
 cortex-m-rt = "0.7"
-embedded-hal = "1"
-embedded-hal-nb = "1"
 embedded-io = "0.6"
 defmt = "1"
-defmt-rtt = { version = "0.4" }
-panic-probe = { version = "0.3", features = ["print-defmt"] }
+defmt-rtt = { version = "1" }
+panic-probe = { version = "1", features = ["print-defmt"] }
 num_enum = { version = "0.7", default-features = false }
-crc = "3"
-cobs = { version = "0.3", default-features = false }
-satrs = { version = "0.2", default-features = false }
+cobs = { version = "0.4", default-features = false }
+satrs = { version = "0.3.0-alpha.1", default-features = false }
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
-once_cell = { version = "1", default-features = false, features = ["critical-section"] }
-spacepackets = { version = "0.11", default-features = false, features = ["defmt"] }
+spacepackets = { version = "0.15", default-features = false, features = ["defmt"] }
 # Even though we do not use this directly, we need to activate this feature explicitely
 # so that RTIC compiles because thumv6 does not have CAS operations natively.
 portable-atomic = {version = "1", features = ["unsafe-assume-single-core"]}

 rtic = { version = "2", features = ["thumbv6-backend"] }
 rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
-rtic-sync = {version = "1", features = ["defmt-03"]}

 [dependencies.va108xx-hal]
-version = "0.11"
+version = "0.12"
 path = "../va108xx-hal"
 features = ["defmt"]

 [dependencies.vorago-reb1]
-version = "0.8"
+version = "0.9"
+path = "../vorago-reb1"
+
+[package.metadata.cargo-machete]
+ignored = ["portable-atomic", "cortex-m-rt"]
--- a/flashloader/slot-a-blinky/Cargo.toml
+++ b/flashloader/slot-a-blinky/Cargo.toml
@@ -9,9 +9,8 @@ edition = "2021"
 cortex-m-rt = "0.7"
 panic-rtt-target = { version = "0.1.3" }
 rtt-target = { version = "0.5" }
-cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 embedded-hal = "1"
-va108xx-hal = { version = "0.10.0" }
+va108xx-hal = { version = "0.11" }

 [profile.dev]
 codegen-units = 1
--- a/flashloader/slot-a-blinky/src/main.rs
+++ b/flashloader/slot-a-blinky/src/main.rs
@@ -3,7 +3,7 @@
 #![no_std]

 use cortex_m_rt::entry;
-use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
+use embedded_hal::delay::DelayNs;
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer};
@@ -15,11 +15,11 @@ fn main() -> ! {

    let mut dp = pac::Peripherals::take().unwrap();
    let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0);
-    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
    let mut led1 = porta.pa10.into_readable_push_pull_output();

    loop {
-        led1.toggle().ok();
+        led1.toggle();
        timer.delay_ms(500);
    }
 }
--- a/flashloader/slot-b-blinky/Cargo.toml
+++ b/flashloader/slot-b-blinky/Cargo.toml
@@ -9,9 +9,8 @@ edition = "2021"
 cortex-m-rt = "0.7"
 panic-rtt-target = { version = "0.1.3" }
 rtt-target = { version = "0.5" }
-cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
 embedded-hal = "1"
-va108xx-hal = { version = "0.10.0" }
+va108xx-hal = { version = "0.11" }

 [profile.dev]
 codegen-units = 1
--- a/flashloader/slot-b-blinky/src/main.rs
+++ b/flashloader/slot-b-blinky/src/main.rs
@@ -3,7 +3,7 @@
 #![no_std]

 use cortex_m_rt::entry;
-use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
+use embedded_hal::delay::DelayNs;
 use panic_rtt_target as _;
 use rtt_target::{rprintln, rtt_init_print};
 use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountdownTimer};
@@ -15,11 +15,11 @@ fn main() -> ! {

    let mut dp = pac::Peripherals::take().unwrap();
    let mut timer = CountdownTimer::new(&mut dp.sysconfig, 50.MHz(), dp.tim0);
-    let porta = PinsA::new(&mut dp.sysconfig, Some(dp.ioconfig), dp.porta);
+    let porta = PinsA::new(&mut dp.sysconfig, dp.porta);
    let mut led2 = porta.pa7.into_readable_push_pull_output();

    loop {
-        led2.toggle().ok();
+        led2.toggle();
        timer.delay_ms(1000);
    }
 }
--- a/flashloader/src/main.rs
+++ b/flashloader/src/main.rs
@@ -69,7 +69,8 @@ mod app {
        tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
    };
    use va108xx_hal::pins::PinsA;
-    use va108xx_hal::uart::IrqContextTimeoutOrMaxSize;
+    use va108xx_hal::spi::SpiClockConfig;
+    use va108xx_hal::uart::InterruptContextTimeoutOrMaxSize;
    use va108xx_hal::{pac, uart, InterruptConfig};
    use vorago_reb1::m95m01::M95M01;

@@ -85,7 +86,7 @@ mod app {
    struct Local {
        uart_rx: uart::RxWithInterrupt,
        uart_tx: uart::Tx,
-        rx_context: IrqContextTimeoutOrMaxSize,
+        rx_context: InterruptContextTimeoutOrMaxSize,
        verif_reporter: VerificationReportCreator,
        nvm: M95M01,
    }
@@ -105,8 +106,9 @@ mod app {

        Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());

-        let mut dp = cx.device;
-        let nvm = M95M01::new(&mut dp.sysconfig, SYSCLK_FREQ, dp.spic);
+        let dp = cx.device;
+        let spi_clock_config = SpiClockConfig::new(2, 4);
+        let nvm = M95M01::new(dp.spic, spi_clock_config);

        let gpioa = PinsA::new(dp.porta);
        let tx = gpioa.pa9;
@@ -127,7 +129,7 @@ mod app {

        let verif_reporter = VerificationReportCreator::new(0).unwrap();

-        let mut rx_context = IrqContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
+        let mut rx_context = InterruptContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
        rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context)
            .expect("initiating UART RX failed");
        pus_tc_handler::spawn().unwrap();
@@ -270,7 +272,7 @@ mod app {
            defmt::warn!("PUS TC error: {}", pus_tc.unwrap_err());
            return;
        }
-        let (pus_tc, _) = pus_tc.unwrap();
+        let pus_tc = pus_tc.unwrap();
        let mut write_and_send = |tm: &PusTmCreator| {
            let written_size = tm.write_to_bytes(cx.local.verif_buf).unwrap();
            cx.shared.tm_rb.lock(|prod| {
@@ -278,18 +280,18 @@ mod app {
                prod.buf.push_slice(&cx.local.verif_buf[0..written_size]);
            });
        };
-        let token = cx.local.verif_reporter.add_tc(&pus_tc);
-        let (tm, accepted_token) = cx
+        let request_id = VerificationReportCreator::read_request_id_from_tc(&pus_tc);
+        let tm = cx
            .local
            .verif_reporter
-            .acceptance_success(cx.local.src_data_buf, token, 0, 0, &[])
+            .acceptance_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
            .expect("acceptance success failed");
        write_and_send(&tm);

-        let (tm, started_token) = cx
+        let tm = cx
            .local
            .verif_reporter
-            .start_success(cx.local.src_data_buf, accepted_token, 0, 0, &[])
+            .start_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
            .expect("acceptance success failed");
        write_and_send(&tm);

@@ -308,7 +310,7 @@ mod app {
                let tm = cx
                    .local
                    .verif_reporter
-                    .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
+                    .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
                    .expect("completion success failed");
                write_and_send(&tm);
            };
@@ -339,7 +341,7 @@ mod app {
                let tm = cx
                    .local
                    .verif_reporter
-                    .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
+                    .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
                    .expect("completion success failed");
                write_and_send(&tm);
            }
@@ -349,7 +351,7 @@ mod app {
            let tm = cx
                .local
                .verif_reporter
-                .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
+                .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
                .expect("completion success failed");
            write_and_send(&tm);
        } else if pus_tc.service() == PusServiceId::MemoryManagement as u8 {
@@ -358,7 +360,7 @@ mod app {
                .verif_reporter
                .step_success(
                    cx.local.src_data_buf,
-                    &started_token,
+                    &request_id,
                    0,
                    0,
                    &[],
@@ -408,7 +410,7 @@ mod app {
                        .verif_reporter
                        .completion_failure(
                            cx.local.src_data_buf,
-                            started_token,
+                            &request_id,
                            0,
                            0,
                            FailParams::new(&[], &EcssEnumU8::new(0), &[]),
@@ -417,7 +419,7 @@ mod app {
                } else {
                    cx.local
                        .verif_reporter
-                        .completion_success(cx.local.src_data_buf, started_token, 0, 0, &[])
+                        .completion_success(cx.local.src_data_buf, &request_id, 0, 0, &[])
                        .expect("completion success failed")
                };
                write_and_send(&tm);
--- a/va108xx-embassy/CHANGELOG.md
+++ b/va108xx-embassy/CHANGELOG.md
@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ## [unreleased]

+## [v0.3.0] 2025-09-03
+
+Bumped allowed va108xx-hal to v0.12
+
 ## [v0.2.1] 2025-03-07

 - Bumped allowed va108xx-hal to v0.11
@@ -26,6 +30,7 @@ Docs patch

 Initial release

-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.1...HEAD
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.3.0...HEAD
+[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.1...va10xx-embassy-v0.3.0
 [v0.2.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.2.0...va10xx-embassy-v0.2.1
 [v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-embassy-v0.1.2...va10xx-embassy-v0.2.0
--- a/va108xx-embassy/Cargo.toml
+++ b/va108xx-embassy/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-embassy"
-version = "0.2.1"
+version = "0.3.0"
 edition = "2021"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers"
@@ -11,8 +11,8 @@ keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
 categories = ["aerospace", "embedded", "no-std", "hardware-support"]

 [dependencies]
-vorago-shared-periphs = { version = "0.1", path = "../../vorago-shared-periphs" }
-va108xx-hal = { path = "../va108xx-hal" }
+vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
+va108xx-hal = { version = "0.12" }

 [features]
 default = ["irq-oc30-oc31"]
--- a/va108xx-embassy/src/lib.rs
+++ b/va108xx-embassy/src/lib.rs
@@ -36,8 +36,8 @@
 #[cfg(feature = "irqs-in-lib")]
 use va108xx_hal::pac::{self, interrupt};
 use va108xx_hal::time::Hertz;
-use va108xx_hal::timer::TimMarker;
-use vorago_shared_periphs::embassy::time_driver;
+use va108xx_hal::timer::TimInstance;
+use vorago_shared_hal::embassy::time_driver;

 /// Macro to define the IRQ handlers for the time driver.
 ///
@@ -87,10 +87,10 @@ embassy_time_driver_irqs!(timekeeper_irq = OC29, alarm_irq = OC28);
 /// This should be used if the interrupt handler is provided by the library, which is the
 /// default case.
 #[cfg(feature = "irqs-in-lib")]
-pub fn init<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
-    sysclk: Hertz,
+pub fn init<TimekeeperTim: TimInstance, AlarmTim: TimInstance>(
    timekeeper_tim: TimekeeperTim,
    alarm_tim: AlarmTim,
+    sysclk: Hertz,
 ) {
    time_driver().__init(sysclk, timekeeper_tim, alarm_tim, TIMEKEEPER_IRQ, ALARM_IRQ)
 }
@@ -98,10 +98,10 @@ pub fn init<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
 /// Initialization method for embassy when using custom IRQ handlers.
 ///
 /// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs.
-pub fn init_with_custom_irqs<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
-    sysclk: Hertz,
+pub fn init_with_custom_irqs<TimekeeperTim: TimInstance, AlarmTim: TimInstance>(
    timekeeper_tim: TimekeeperTim,
    alarm_tim: AlarmTim,
+    sysclk: Hertz,
    timekeeper_irq: pac::Interrupt,
    alarm_irq: pac::Interrupt,
 ) {
--- a/va108xx-hal/CHANGELOG.md
+++ b/va108xx-hal/CHANGELOG.md
@@ -8,9 +8,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ## [unreleased]

+## [v0.12.0] 2025-09-03
+
 ## Changed

- Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs)
+- Move most library components to new [`vorago-shared-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal)
  which is mostly re-exported in this crate.
 - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router
  peripheral instance generally does not need to be passed to HAL API anymore.
@@ -274,7 +276,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Added basic test binary in form of an example
 - README with basic instructions how to set up own binary crate

-[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.12.0...HEAD
+[v0.12.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.1...va108xx-hal-v0.12.0
 [v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
 [v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
 [v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
--- a/va108xx-hal/Cargo.toml
+++ b/va108xx-hal/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.11.1"
+version = "0.12.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -12,29 +12,11 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]

 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
-cortex-m-rt = "0.7"
-nb = "1"
-paste = "1"
-#vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
-vorago-shared-periphs = { path = "../../vorago-shared-periphs", features = ["vor1x"] }
-embedded-hal = "1"
-embedded-hal-async = "1"
-embedded-hal-nb = "1"
-embedded-io = "0.6"
-embedded-io-async = "0.6"
+vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
 fugit = "0.3"
-typenum = "1"
-critical-section = "1"
-delegate = ">=0.12, <=0.13"
-heapless = "0.8"
-static_cell = "2"
 thiserror = { version = "2", default-features = false }
-void = { version = "1", default-features = false }
-once_cell = { version = "1", default-features = false }
-va108xx = { version = "0.5", default-features = false, features = ["critical-section", "defmt"] }
-embassy-sync = "0.6"
-
-defmt = { version = "0.3", optional = true }
+va108xx = { version = "0.6", default-features = false, features = ["critical-section", "defmt"] }
+defmt = { version = "1", optional = true }

 [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
 portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
@@ -44,8 +26,11 @@ portable-atomic = "1"
 [features]
 default = ["rt"]
 rt = ["va108xx/rt"]
-defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03", "vorago-shared-periphs/defmt"]
+defmt = ["dep:defmt", "vorago-shared-hal/defmt"]

 [package.metadata.docs.rs]
 all-features = true
 rustdoc-args = ["--generate-link-to-definition"]
+
+[package.metadata.cargo-machete]
+ignored = ["cortex-m"]
--- a/va108xx-hal/src/clock.rs
+++ b/va108xx-hal/src/clock.rs
@@ -1,51 +1,31 @@
 //! # API for clock related functionality
 //!
 //! This also includes functionality to enable the peripheral clocks
-use crate::time::Hertz;
-use cortex_m::interrupt::{self, Mutex};
-use once_cell::unsync::OnceCell;
+pub use vorago_shared_hal::gpio::FilterClockSelect;
+pub use vorago_shared_hal::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};

-pub use vorago_shared_periphs::gpio::FilterClkSel;
-pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
-
-static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
-
-/// The Vorago in powered by an external clock which might have different frequencies.
-/// The clock can be set here so it can be used by other software components as well.
-/// The clock can be set exactly once
-pub fn set_sys_clock(freq: impl Into<Hertz>) {
-    interrupt::free(|cs| {
-        SYS_CLOCK.borrow(cs).set(freq.into()).ok();
-    })
-}
-
-/// Returns the configured system clock
-pub fn get_sys_clock() -> Option<Hertz> {
-    interrupt::free(|cs| SYS_CLOCK.borrow(cs).get().copied())
-}
-
-pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
+pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClockSelect, div: u32) {
    match clk_sel {
-        FilterClkSel::SysClk => (),
-        FilterClkSel::Clk1 => {
+        FilterClockSelect::SysClk => (),
+        FilterClockSelect::Clk1 => {
            syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
        }
-        FilterClkSel::Clk2 => {
+        FilterClockSelect::Clk2 => {
            syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
        }
-        FilterClkSel::Clk3 => {
+        FilterClockSelect::Clk3 => {
            syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
        }
-        FilterClkSel::Clk4 => {
+        FilterClockSelect::Clk4 => {
            syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
        }
-        FilterClkSel::Clk5 => {
+        FilterClockSelect::Clk5 => {
            syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
        }
-        FilterClkSel::Clk6 => {
+        FilterClockSelect::Clk6 => {
            syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
        }
-        FilterClkSel::Clk7 => {
+        FilterClockSelect::Clk7 => {
            syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
        }
    }
--- a/va108xx-hal/src/gpio/mod.rs
+++ b/va108xx-hal/src/gpio/mod.rs
@@ -17,4 +17,4 @@
 //!
 //! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
 //! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
-pub use vorago_shared_periphs::gpio::*;
+pub use vorago_shared_hal::gpio::*;
--- a/va108xx-hal/src/i2c.rs
+++ b/va108xx-hal/src/i2c.rs
@@ -3,4 +3,4 @@
 //! ## Examples
 //!
 //! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
-pub use vorago_shared_periphs::i2c::*;
+pub use vorago_shared_hal::i2c::*;
--- a/va108xx-hal/src/lib.rs
+++ b/va108xx-hal/src/lib.rs
@@ -17,8 +17,9 @@ pub mod time;
 pub mod timer;
 pub mod uart;

-pub use vorago_shared_periphs::{
-    disable_nvic_interrupt, enable_nvic_interrupt, FunSel, InterruptConfig, PeripheralSelect,
+pub use vorago_shared_hal::{
+    disable_nvic_interrupt, enable_nvic_interrupt, FunctionSelect, InterruptConfig,
+    PeripheralSelect,
 };

 /// This is the NONE destination reigster value for the IRQSEL peripheral.
@@ -38,7 +39,7 @@ pub fn port_function_select(
    ioconfig: &mut pac::Ioconfig,
    port: Port,
    pin: u8,
-    funsel: FunSel,
+    funsel: FunctionSelect,
 ) -> Result<(), InvalidPinError> {
    if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) {
        return Err(InvalidPinError(pin));
@@ -46,7 +47,7 @@ pub fn port_function_select(

    let reg_block = match port {
        Port::A => ioconfig.porta(pin as usize),
-        Port::B => ioconfig.portb0(pin as usize),
+        Port::B => ioconfig.portb(pin as usize),
    };

    reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
--- a/va108xx-hal/src/pins.rs
+++ b/va108xx-hal/src/pins.rs
@@ -3,4 +3,4 @@
 //! This module contains the pin singletons. It allows creating those singletons
 //! to access the [Pin] structures of individual ports in a safe way with checked ownership
 //! rules.
-pub use vorago_shared_periphs::pins::*;
+pub use vorago_shared_hal::pins::*;
--- a/va108xx-hal/src/pwm.rs
+++ b/va108xx-hal/src/pwm.rs
@@ -5,4 +5,4 @@
 //! ## Examples
 //!
 //! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
-pub use vorago_shared_periphs::pwm::*;
+pub use vorago_shared_hal::pwm::*;
--- a/va108xx-hal/src/spi/mod.rs
+++ b/va108xx-hal/src/spi/mod.rs
@@ -1,12 +1,12 @@
 //! API for the SPI peripheral.
 //!
 //! The main abstraction provided by this module is the [Spi] an structure.
-//! It provides the [embedded_hal::spi] traits, but also offer a low level interface
-//! via the [SpiLowLevel] trait.
+//! It provides the [SpiBus trait](https://docs.rs/embedded-hal/latest/embedded_hal/spi/trait.SpiBus.html),
+//! but also offer a low level interface via the [SpiLowLevel] trait.
 //!
 //! ## Examples
 //!
 //! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
 //! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
 //! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
-pub use vorago_shared_periphs::spi::*;
+pub use vorago_shared_hal::spi::*;
--- a/va108xx-hal/src/sysconfig.rs
+++ b/va108xx-hal/src/sysconfig.rs
@@ -38,6 +38,6 @@ pub fn disable_ram_scrubbing() {
    syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
 }

-pub use vorago_shared_periphs::sysconfig::{
+pub use vorago_shared_hal::sysconfig::{
    assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock,
 };
--- a/va108xx-hal/src/time.rs
+++ b/va108xx-hal/src/time.rs
@@ -1,2 +1,2 @@
 //! Time units
-pub use vorago_shared_periphs::time::*;
+pub use vorago_shared_hal::time::*;
--- a/va108xx-hal/src/timer.rs
+++ b/va108xx-hal/src/timer.rs
@@ -4,4 +4,4 @@
 //!
 //! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
 //! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
-pub use vorago_shared_periphs::timer::*;
+pub use vorago_shared_hal::timer::*;
--- a/va108xx-hal/src/uart/mod.rs
+++ b/va108xx-hal/src/uart/mod.rs
@@ -14,4 +14,4 @@
 //! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
 //! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
 //! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
-pub use vorago_shared_periphs::uart::*;
+pub use vorago_shared_hal::uart::*;
--- a/va108xx/CHANGELOG.md
+++ b/va108xx/CHANGELOG.md
@@ -8,6 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ## [unreleased]

+## [v0.6.0] 2025-09-03
+
+- Re-generated PAC with `svd2rust` v0.37.0
+
+## [v0.5.1] 2025-07-22
+
+defmt version v1
+
 ## [v0.5.0] 2025-02-17

 - Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations
@@ -55,7 +63,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ### Fixed

- Generated with patched version of `svd2rust`: See 
+- Generated with patched version of `svd2rust`: See
  https://github.com/rust-embedded/svd2rust/pull/549 for more details.
  Some bitmasks were missing from register reader definitions.

@@ -79,3 +87,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 - First version of the PAC which builds. Uses a patched version
  of `svd2rust`: https://github.com/rust-embedded/svd2rust
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.6.0...HEAD
+[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.1...va108xx-v0.6.0
+[v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.5.0...va108xx-v0.5.1
+[v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-v0.4.0...va108xx-v0.5.0
--- a/va108xx/Cargo.toml
+++ b/va108xx/Cargo.toml
@@ -1,6 +1,6 @@
 [package]
 name = "va108xx"
-version = "0.5.0"
+version = "0.6.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"
--- a/va108xx/src/generic.rs
+++ b/va108xx/src/generic.rs
@@ -1,8 +1,46 @@
 use core::marker;
+#[doc = " Generic peripheral accessor"]
+pub struct Periph<RB, const A: usize> {
+    _marker: marker::PhantomData<RB>,
+}
+unsafe impl<RB, const A: usize> Send for Periph<RB, A> {}
+impl<RB, const A: usize> Periph<RB, A> {
+    #[doc = "Pointer to the register block"]
+    pub const PTR: *const RB = A as *const _;
+    #[doc = "Return the pointer to the register block"]
+    #[inline(always)]
+    pub const fn ptr() -> *const RB {
+        Self::PTR
+    }
+    #[doc = " Steal an instance of this peripheral"]
+    #[doc = ""]
+    #[doc = " # Safety"]
+    #[doc = ""]
+    #[doc = " Ensure that the new instance of the peripheral cannot be used in a way"]
+    #[doc = " that may race with any existing instances, for example by only"]
+    #[doc = " accessing read-only or write-only registers, or by consuming the"]
+    #[doc = " original peripheral and using critical sections to coordinate"]
+    #[doc = " access between multiple new instances."]
+    #[doc = ""]
+    #[doc = " Additionally, other software such as HALs may rely on only one"]
+    #[doc = " peripheral instance existing to ensure memory safety; ensure"]
+    #[doc = " no stolen instances are passed to such software."]
+    pub unsafe fn steal() -> Self {
+        Self {
+            _marker: marker::PhantomData,
+        }
+    }
+}
+impl<RB, const A: usize> core::ops::Deref for Periph<RB, A> {
+    type Target = RB;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        unsafe { &*Self::PTR }
+    }
+}
 #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
 pub trait RawReg:
    Copy
-    + Default
    + From<bool>
    + core::ops::BitOr<Output = Self>
    + core::ops::BitAnd<Output = Self>
@@ -13,8 +51,10 @@ pub trait RawReg:
 {
    #[doc = " Mask for bits of width `WI`"]
    fn mask<const WI: u8>() -> Self;
-    #[doc = " Mask for bits of width 1"]
-    fn one() -> Self;
+    #[doc = " `0`"]
+    const ZERO: Self;
+    #[doc = " `1`"]
+    const ONE: Self;
 }
 macro_rules! raw_reg {
    ($ U : ty , $ size : literal , $ mask : ident) => {
@@ -23,10 +63,8 @@ macro_rules! raw_reg {
            fn mask<const WI: u8>() -> Self {
                $mask::<WI>()
            }
-            #[inline(always)]
-            fn one() -> Self {
-                1
-            }
+            const ZERO: Self = 0;
+            const ONE: Self = 1;
        }
        const fn $mask<const WI: u8>() -> $U {
            <$U>::MAX >> ($size - WI)
@@ -65,9 +103,9 @@ pub trait Writable: RegisterSpec {
    #[doc = " Is it safe to write any bits to register"]
    type Safety;
    #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
    #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
-    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = Self::Ux::ZERO;
 }
 #[doc = " Reset value of the register."]
 #[doc = ""]
@@ -75,7 +113,7 @@ pub trait Writable: RegisterSpec {
 #[doc = " register by using the `reset` method."]
 pub trait Resettable: RegisterSpec {
    #[doc = " Reset value of the register."]
-    const RESET_VALUE: Self::Ux;
+    const RESET_VALUE: Self::Ux = Self::Ux::ZERO;
    #[doc = " Reset value of the register."]
    #[inline(always)]
    fn reset_value() -> Self::Ux {
@@ -344,8 +382,8 @@ macro_rules! bit_proxy {
            #[doc = " Writes bit to the field"]
            #[inline(always)]
            pub fn bit(self, value: bool) -> &'a mut W<REG> {
-                self.w.bits &= !(REG::Ux::one() << self.o);
-                self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
+                self.w.bits &= !(REG::Ux::ONE << self.o);
+                self.w.bits |= (REG::Ux::from(value) & REG::Ux::ONE) << self.o;
                self.w
            }
            #[doc = " Writes `variant` to the field"]
@@ -371,13 +409,13 @@ where
    #[doc = " Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
        self.w
    }
    #[doc = " Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
        self.w
    }
 }
@@ -389,7 +427,7 @@ where
    #[doc = " Sets the field bit"]
    #[inline(always)]
    pub fn set_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
        self.w
    }
 }
@@ -401,7 +439,7 @@ where
    #[doc = " Clears the field bit"]
    #[inline(always)]
    pub fn clear_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
        self.w
    }
 }
@@ -413,7 +451,7 @@ where
    #[doc = "Clears the field bit by passing one"]
    #[inline(always)]
    pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
        self.w
    }
 }
@@ -425,7 +463,7 @@ where
    #[doc = "Sets the field bit by passing zero"]
    #[inline(always)]
    pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
        self.w
    }
 }
@@ -437,7 +475,7 @@ where
    #[doc = "Toggle the field bit by passing one"]
    #[inline(always)]
    pub fn toggle_bit(self) -> &'a mut W<REG> {
-        self.w.bits |= REG::Ux::one() << self.o;
+        self.w.bits |= REG::Ux::ONE << self.o;
        self.w
    }
 }
@@ -449,7 +487,7 @@ where
    #[doc = "Toggle the field bit by passing zero"]
    #[inline(always)]
    pub fn toggle_bit(self) -> &'a mut W<REG> {
-        self.w.bits &= !(REG::Ux::one() << self.o);
+        self.w.bits &= !(REG::Ux::ONE << self.o);
        self.w
    }
 }
@@ -594,7 +632,7 @@ impl<REG: Writable> Reg<REG> {
        F: FnOnce(&mut W<REG>) -> &mut W<REG>,
    {
        let value = f(&mut W {
-            bits: REG::Ux::default(),
+            bits: REG::Ux::ZERO,
            _reg: marker::PhantomData,
        })
        .bits;
@@ -614,7 +652,7 @@ impl<REG: Writable> Reg<REG> {
        F: FnOnce(&mut W<REG>) -> T,
    {
        let mut writer = W {
-            bits: REG::Ux::default(),
+            bits: REG::Ux::ZERO,
            _reg: marker::PhantomData,
        };
        let result = f(&mut writer);
--- a/va108xx/src/i2ca.rs
+++ b/va108xx/src/i2ca.rs
@@ -240,68 +240,57 @@ impl RegisterBlock {
        &self.perid
    }
 }
-#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
-module"]
+#[doc = "CTRL (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`] module"]
 #[doc(alias = "CTRL")]
 pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
 #[doc = "Control Register"]
 pub mod ctrl;
-#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`]
-module"]
+#[doc = "CLKSCALE (rw) register accessor: Clock Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkscale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkscale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkscale`] module"]
 #[doc(alias = "CLKSCALE")]
 pub type Clkscale = crate::Reg<clkscale::ClkscaleSpec>;
 #[doc = "Clock Scale divide value"]
 pub mod clkscale;
-#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`]
-module"]
+#[doc = "WORDS (rw) register accessor: Word Count value\n\nYou can [`read`](crate::Reg::read) this register and get [`words::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`words::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@words`] module"]
 #[doc(alias = "WORDS")]
 pub type Words = crate::Reg<words::WordsSpec>;
 #[doc = "Word Count value"]
 pub mod words;
-#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`]
-module"]
+#[doc = "ADDRESS (rw) register accessor: I2C Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@address`] module"]
 #[doc(alias = "ADDRESS")]
 pub type Address = crate::Reg<address::AddressSpec>;
 #[doc = "I2C Address value"]
 pub mod address;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
-module"]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`]
-module"]
+#[doc = "CMD (rw) register accessor: Command Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cmd::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmd::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmd`] module"]
 #[doc(alias = "CMD")]
 pub type Cmd = crate::Reg<cmd::CmdSpec>;
 #[doc = "Command Register"]
 pub mod cmd;
-#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
-module"]
+#[doc = "STATUS (r) register accessor: I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "I2C Controller Status Register"]
 pub mod status;
-#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
-module"]
+#[doc = "STATE (r) register accessor: Internal STATE of I2C Master Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of I2C Master Controller"]
 pub mod state;
-#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`]
-module"]
+#[doc = "TXCOUNT (r) register accessor: TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txcount`] module"]
 #[doc(alias = "TXCOUNT")]
 pub type Txcount = crate::Reg<txcount::TxcountSpec>;
 #[doc = "TX Count Register"]
 pub mod txcount;
-#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`]
-module"]
+#[doc = "RXCOUNT (r) register accessor: RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxcount`] module"]
 #[doc(alias = "RXCOUNT")]
 pub type Rxcount = crate::Reg<rxcount::RxcountSpec>;
 #[doc = "RX Count Register"]
 pub mod rxcount;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
-module"]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
@@ -312,98 +301,82 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
-module"]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
-module"]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
-module"]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`]
-module"]
+#[doc = "TMCONFIG (rw) register accessor: Timing Config Register\n\nYou can [`read`](crate::Reg::read) this register and get [`tmconfig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tmconfig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tmconfig`] module"]
 #[doc(alias = "TMCONFIG")]
 pub type Tmconfig = crate::Reg<tmconfig::TmconfigSpec>;
 #[doc = "Timing Config Register"]
 pub mod tmconfig;
-#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`]
-module"]
+#[doc = "CLKTOLIMIT (rw) register accessor: Clock Low Timeout Limit Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clktolimit::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clktolimit::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clktolimit`] module"]
 #[doc(alias = "CLKTOLIMIT")]
 pub type Clktolimit = crate::Reg<clktolimit::ClktolimitSpec>;
 #[doc = "Clock Low Timeout Limit Register"]
 pub mod clktolimit;
-#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`]
-module"]
+#[doc = "S0_CTRL (rw) register accessor: Slave Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_ctrl`] module"]
 #[doc(alias = "S0_CTRL")]
 pub type S0Ctrl = crate::Reg<s0_ctrl::S0CtrlSpec>;
 #[doc = "Slave Control Register"]
 pub mod s0_ctrl;
-#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`]
-module"]
+#[doc = "S0_MAXWORDS (rw) register accessor: Slave MaxWords Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_maxwords::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_maxwords::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_maxwords`] module"]
 #[doc(alias = "S0_MAXWORDS")]
 pub type S0Maxwords = crate::Reg<s0_maxwords::S0MaxwordsSpec>;
 #[doc = "Slave MaxWords Register"]
 pub mod s0_maxwords;
-#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`]
-module"]
+#[doc = "S0_ADDRESS (rw) register accessor: Slave I2C Address Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_address::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_address::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_address`] module"]
 #[doc(alias = "S0_ADDRESS")]
 pub type S0Address = crate::Reg<s0_address::S0AddressSpec>;
 #[doc = "Slave I2C Address Value"]
 pub mod s0_address;
-#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`]
-module"]
+#[doc = "S0_ADDRESSMASK (rw) register accessor: Slave I2C Address Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmask`] module"]
 #[doc(alias = "S0_ADDRESSMASK")]
 pub type S0Addressmask = crate::Reg<s0_addressmask::S0AddressmaskSpec>;
 #[doc = "Slave I2C Address Mask value"]
 pub mod s0_addressmask;
-#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`]
-module"]
+#[doc = "S0_DATA (rw) register accessor: Slave Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_data`] module"]
 #[doc(alias = "S0_DATA")]
 pub type S0Data = crate::Reg<s0_data::S0DataSpec>;
 #[doc = "Slave Data Input/Output"]
 pub mod s0_data;
-#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`]
-module"]
+#[doc = "S0_LASTADDRESS (r) register accessor: Slave I2C Last Address value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_lastaddress::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_lastaddress`] module"]
 #[doc(alias = "S0_LASTADDRESS")]
 pub type S0Lastaddress = crate::Reg<s0_lastaddress::S0LastaddressSpec>;
 #[doc = "Slave I2C Last Address value"]
 pub mod s0_lastaddress;
-#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`]
-module"]
+#[doc = "S0_STATUS (r) register accessor: Slave I2C Controller Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_status`] module"]
 #[doc(alias = "S0_STATUS")]
 pub type S0Status = crate::Reg<s0_status::S0StatusSpec>;
 #[doc = "Slave I2C Controller Status Register"]
 pub mod s0_status;
-#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`]
-module"]
+#[doc = "S0_STATE (r) register accessor: Internal STATE of I2C Slave Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_state`] module"]
 #[doc(alias = "S0_STATE")]
 pub type S0State = crate::Reg<s0_state::S0StateSpec>;
 #[doc = "Internal STATE of I2C Slave Controller"]
 pub mod s0_state;
-#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`]
-module"]
+#[doc = "S0_TXCOUNT (r) register accessor: Slave TX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txcount`] module"]
 #[doc(alias = "S0_TXCOUNT")]
 pub type S0Txcount = crate::Reg<s0_txcount::S0TxcountSpec>;
 #[doc = "Slave TX Count Register"]
 pub mod s0_txcount;
-#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`]
-module"]
+#[doc = "S0_RXCOUNT (r) register accessor: Slave RX Count Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxcount::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxcount`] module"]
 #[doc(alias = "S0_RXCOUNT")]
 pub type S0Rxcount = crate::Reg<s0_rxcount::S0RxcountSpec>;
 #[doc = "Slave RX Count Register"]
 pub mod s0_rxcount;
-#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`]
-module"]
+#[doc = "S0_IRQ_ENB (rw) register accessor: Slave Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_irq_enb`] module"]
 #[doc(alias = "S0_IRQ_ENB")]
 pub type S0IrqEnb = crate::Reg<s0_irq_enb::S0IrqEnbSpec>;
 #[doc = "Slave Interrupt Enable Register"]
@@ -414,38 +387,32 @@ pub use s0_irq_enb as s0_irq_clr;
 pub use S0IrqEnb as S0IrqRaw;
 pub use S0IrqEnb as S0IrqEnd;
 pub use S0IrqEnb as S0IrqClr;
-#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`]
-module"]
+#[doc = "S0_RXFIFOIRQTRG (rw) register accessor: Slave Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_rxfifoirqtrg`] module"]
 #[doc(alias = "S0_RXFIFOIRQTRG")]
 pub type S0Rxfifoirqtrg = crate::Reg<s0_rxfifoirqtrg::S0RxfifoirqtrgSpec>;
 #[doc = "Slave Rx FIFO IRQ Trigger Level"]
 pub mod s0_rxfifoirqtrg;
-#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`]
-module"]
+#[doc = "S0_TXFIFOIRQTRG (rw) register accessor: Slave Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_txfifoirqtrg`] module"]
 #[doc(alias = "S0_TXFIFOIRQTRG")]
 pub type S0Txfifoirqtrg = crate::Reg<s0_txfifoirqtrg::S0TxfifoirqtrgSpec>;
 #[doc = "Slave Tx FIFO IRQ Trigger Level"]
 pub mod s0_txfifoirqtrg;
-#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`]
-module"]
+#[doc = "S0_FIFO_CLR (w) register accessor: Slave Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_fifo_clr`] module"]
 #[doc(alias = "S0_FIFO_CLR")]
 pub type S0FifoClr = crate::Reg<s0_fifo_clr::S0FifoClrSpec>;
 #[doc = "Slave Clear FIFO Register"]
 pub mod s0_fifo_clr;
-#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`]
-module"]
+#[doc = "S0_ADDRESSB (rw) register accessor: Slave I2C Address B Value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressb`] module"]
 #[doc(alias = "S0_ADDRESSB")]
 pub type S0Addressb = crate::Reg<s0_addressb::S0AddressbSpec>;
 #[doc = "Slave I2C Address B Value"]
 pub mod s0_addressb;
-#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`]
-module"]
+#[doc = "S0_ADDRESSMASKB (rw) register accessor: Slave I2C Address B Mask value\n\nYou can [`read`](crate::Reg::read) this register and get [`s0_addressmaskb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`s0_addressmaskb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@s0_addressmaskb`] module"]
 #[doc(alias = "S0_ADDRESSMASKB")]
 pub type S0Addressmaskb = crate::Reg<s0_addressmaskb::S0AddressmaskbSpec>;
 #[doc = "Slave I2C Address B Mask value"]
 pub mod s0_addressmaskb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
-module"]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]
--- a/va108xx/src/i2ca/address.rs
+++ b/va108xx/src/i2ca/address.rs
@@ -19,10 +19,6 @@ impl crate::Readable for AddressSpec {}
 #[doc = "`write(|w| ..)` method takes [`address::W`](W) writer structure"]
 impl crate::Writable for AddressSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets ADDRESS to value 0"]
-impl crate::Resettable for AddressSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for AddressSpec {}
--- a/va108xx/src/i2ca/clkscale.rs
+++ b/va108xx/src/i2ca/clkscale.rs
@@ -25,12 +25,12 @@ impl R {
 impl W {
    #[doc = "Bits 0:30 - Enable FastMode"]
    #[inline(always)]
-    pub fn value(&mut self) -> ValueW<ClkscaleSpec> {
+    pub fn value(&mut self) -> ValueW<'_, ClkscaleSpec> {
        ValueW::new(self, 0)
    }
    #[doc = "Bit 31 - Enable FastMode"]
    #[inline(always)]
-    pub fn fastmode(&mut self) -> FastmodeW<ClkscaleSpec> {
+    pub fn fastmode(&mut self) -> FastmodeW<'_, ClkscaleSpec> {
        FastmodeW::new(self, 31)
    }
 }
@@ -44,10 +44,6 @@ impl crate::Readable for ClkscaleSpec {}
 #[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
 impl crate::Writable for ClkscaleSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKSCALE to value 0"]
-impl crate::Resettable for ClkscaleSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for ClkscaleSpec {}
--- a/va108xx/src/i2ca/clktolimit.rs
+++ b/va108xx/src/i2ca/clktolimit.rs
@@ -19,10 +19,6 @@ impl crate::Readable for ClktolimitSpec {}
 #[doc = "`write(|w| ..)` method takes [`clktolimit::W`](W) writer structure"]
 impl crate::Writable for ClktolimitSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
-impl crate::Resettable for ClktolimitSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for ClktolimitSpec {}
--- a/va108xx/src/i2ca/cmd.rs
+++ b/va108xx/src/i2ca/cmd.rs
@@ -19,10 +19,6 @@ impl crate::Readable for CmdSpec {}
 #[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
 impl crate::Writable for CmdSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CMD to value 0"]
-impl crate::Resettable for CmdSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for CmdSpec {}
--- a/va108xx/src/i2ca/ctrl.rs
+++ b/va108xx/src/i2ca/ctrl.rs
@@ -88,47 +88,47 @@ impl R {
 impl W {
    #[doc = "Bit 0 - I2C CLK Enabled"]
    #[inline(always)]
-    pub fn clkenabled(&mut self) -> ClkenabledW<CtrlSpec> {
+    pub fn clkenabled(&mut self) -> ClkenabledW<'_, CtrlSpec> {
        ClkenabledW::new(self, 0)
    }
    #[doc = "Bit 1 - I2C Activated"]
    #[inline(always)]
-    pub fn enabled(&mut self) -> EnabledW<CtrlSpec> {
+    pub fn enabled(&mut self) -> EnabledW<'_, CtrlSpec> {
        EnabledW::new(self, 1)
    }
    #[doc = "Bit 2 - I2C Active"]
    #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<CtrlSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, CtrlSpec> {
        EnableW::new(self, 2)
    }
    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
    #[inline(always)]
-    pub fn txfemd(&mut self) -> TxfemdW<CtrlSpec> {
+    pub fn txfemd(&mut self) -> TxfemdW<'_, CtrlSpec> {
        TxfemdW::new(self, 3)
    }
    #[doc = "Bit 4 - RX FIFO Full Mode"]
    #[inline(always)]
-    pub fn rxffmd(&mut self) -> RxffmdW<CtrlSpec> {
+    pub fn rxffmd(&mut self) -> RxffmdW<'_, CtrlSpec> {
        RxffmdW::new(self, 4)
    }
    #[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
    #[inline(always)]
-    pub fn algfilter(&mut self) -> AlgfilterW<CtrlSpec> {
+    pub fn algfilter(&mut self) -> AlgfilterW<'_, CtrlSpec> {
        AlgfilterW::new(self, 5)
    }
    #[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
    #[inline(always)]
-    pub fn dlgfilter(&mut self) -> DlgfilterW<CtrlSpec> {
+    pub fn dlgfilter(&mut self) -> DlgfilterW<'_, CtrlSpec> {
        DlgfilterW::new(self, 6)
    }
    #[doc = "Bit 8 - Enable LoopBack Mode"]
    #[inline(always)]
-    pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
+    pub fn loopback(&mut self) -> LoopbackW<'_, CtrlSpec> {
        LoopbackW::new(self, 8)
    }
    #[doc = "Bit 9 - Enable Timing Config Register"]
    #[inline(always)]
-    pub fn tmconfigenb(&mut self) -> TmconfigenbW<CtrlSpec> {
+    pub fn tmconfigenb(&mut self) -> TmconfigenbW<'_, CtrlSpec> {
        TmconfigenbW::new(self, 9)
    }
 }
@@ -142,10 +142,6 @@ impl crate::Readable for CtrlSpec {}
 #[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
 impl crate::Writable for CtrlSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CTRL to value 0"]
-impl crate::Resettable for CtrlSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for CtrlSpec {}
--- a/va108xx/src/i2ca/data.rs
+++ b/va108xx/src/i2ca/data.rs
@@ -19,10 +19,6 @@ impl crate::Readable for DataSpec {}
 #[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
 impl crate::Writable for DataSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATA to value 0"]
-impl crate::Resettable for DataSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for DataSpec {}
--- a/va108xx/src/i2ca/fifo_clr.rs
+++ b/va108xx/src/i2ca/fifo_clr.rs
@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
    #[doc = "Bit 0 - Clear Rx FIFO"]
    #[inline(always)]
-    pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
+    pub fn rxfifo(&mut self) -> RxfifoW<'_, FifoClrSpec> {
        RxfifoW::new(self, 0)
    }
    #[doc = "Bit 1 - Clear Tx FIFO"]
    #[inline(always)]
-    pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
+    pub fn txfifo(&mut self) -> TxfifoW<'_, FifoClrSpec> {
        TxfifoW::new(self, 1)
    }
 }
@@ -24,10 +24,6 @@ impl crate::RegisterSpec for FifoClrSpec {
 #[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
 impl crate::Writable for FifoClrSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets FIFO_CLR to value 0"]
-impl crate::Resettable for FifoClrSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for FifoClrSpec {}
--- a/va108xx/src/i2ca/irq_enb.rs
+++ b/va108xx/src/i2ca/irq_enb.rs
@@ -133,72 +133,72 @@ impl R {
 impl W {
    #[doc = "Bit 0 - I2C Bus is Idle"]
    #[inline(always)]
-    pub fn i2cidle(&mut self) -> I2cidleW<IrqEnbSpec> {
+    pub fn i2cidle(&mut self) -> I2cidleW<'_, IrqEnbSpec> {
        I2cidleW::new(self, 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
-    pub fn idle(&mut self) -> IdleW<IrqEnbSpec> {
+    pub fn idle(&mut self) -> IdleW<'_, IrqEnbSpec> {
        IdleW::new(self, 1)
    }
    #[doc = "Bit 2 - Controller is Waiting"]
    #[inline(always)]
-    pub fn waiting(&mut self) -> WaitingW<IrqEnbSpec> {
+    pub fn waiting(&mut self) -> WaitingW<'_, IrqEnbSpec> {
        WaitingW::new(self, 2)
    }
    #[doc = "Bit 3 - Controller is Stalled"]
    #[inline(always)]
-    pub fn stalled(&mut self) -> StalledW<IrqEnbSpec> {
+    pub fn stalled(&mut self) -> StalledW<'_, IrqEnbSpec> {
        StalledW::new(self, 3)
    }
    #[doc = "Bit 4 - I2C Arbitration was lost"]
    #[inline(always)]
-    pub fn arblost(&mut self) -> ArblostW<IrqEnbSpec> {
+    pub fn arblost(&mut self) -> ArblostW<'_, IrqEnbSpec> {
        ArblostW::new(self, 4)
    }
    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
    #[inline(always)]
-    pub fn nackaddr(&mut self) -> NackaddrW<IrqEnbSpec> {
+    pub fn nackaddr(&mut self) -> NackaddrW<'_, IrqEnbSpec> {
        NackaddrW::new(self, 5)
    }
    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
    #[inline(always)]
-    pub fn nackdata(&mut self) -> NackdataW<IrqEnbSpec> {
+    pub fn nackdata(&mut self) -> NackdataW<'_, IrqEnbSpec> {
        NackdataW::new(self, 6)
    }
    #[doc = "Bit 7 - I2C Clock Low Timeout"]
    #[inline(always)]
-    pub fn clkloto(&mut self) -> ClklotoW<IrqEnbSpec> {
+    pub fn clkloto(&mut self) -> ClklotoW<'_, IrqEnbSpec> {
        ClklotoW::new(self, 7)
    }
    #[doc = "Bit 10 - TX FIFO Overflowed"]
    #[inline(always)]
-    pub fn txoverflow(&mut self) -> TxoverflowW<IrqEnbSpec> {
+    pub fn txoverflow(&mut self) -> TxoverflowW<'_, IrqEnbSpec> {
        TxoverflowW::new(self, 10)
    }
    #[doc = "Bit 11 - TX FIFO Overflowed"]
    #[inline(always)]
-    pub fn rxoverflow(&mut self) -> RxoverflowW<IrqEnbSpec> {
+    pub fn rxoverflow(&mut self) -> RxoverflowW<'_, IrqEnbSpec> {
        RxoverflowW::new(self, 11)
    }
    #[doc = "Bit 12 - TX FIFO Ready"]
    #[inline(always)]
-    pub fn txready(&mut self) -> TxreadyW<IrqEnbSpec> {
+    pub fn txready(&mut self) -> TxreadyW<'_, IrqEnbSpec> {
        TxreadyW::new(self, 12)
    }
    #[doc = "Bit 13 - RX FIFO Ready"]
    #[inline(always)]
-    pub fn rxready(&mut self) -> RxreadyW<IrqEnbSpec> {
+    pub fn rxready(&mut self) -> RxreadyW<'_, IrqEnbSpec> {
        RxreadyW::new(self, 13)
    }
    #[doc = "Bit 14 - TX FIFO Empty"]
    #[inline(always)]
-    pub fn txempty(&mut self) -> TxemptyW<IrqEnbSpec> {
+    pub fn txempty(&mut self) -> TxemptyW<'_, IrqEnbSpec> {
        TxemptyW::new(self, 14)
    }
    #[doc = "Bit 15 - RX FIFO Full"]
    #[inline(always)]
-    pub fn rxfull(&mut self) -> RxfullW<IrqEnbSpec> {
+    pub fn rxfull(&mut self) -> RxfullW<'_, IrqEnbSpec> {
        RxfullW::new(self, 15)
    }
 }
@@ -212,10 +212,6 @@ impl crate::Readable for IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
 impl crate::Writable for IrqEnbSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_ENB to value 0"]
-impl crate::Resettable for IrqEnbSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqEnbSpec {}
--- a/va108xx/src/i2ca/rxcount.rs
+++ b/va108xx/src/i2ca/rxcount.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for RxcountSpec {
 #[doc = "`read()` method returns [`rxcount::R`](R) reader structure"]
 impl crate::Readable for RxcountSpec {}
 #[doc = "`reset()` method sets RXCOUNT to value 0"]
-impl crate::Resettable for RxcountSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for RxcountSpec {}
--- a/va108xx/src/i2ca/rxfifoirqtrg.rs
+++ b/va108xx/src/i2ca/rxfifoirqtrg.rs
@@ -19,10 +19,6 @@ impl crate::Readable for RxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for RxfifoirqtrgSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
-impl crate::Resettable for RxfifoirqtrgSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for RxfifoirqtrgSpec {}
--- a/va108xx/src/i2ca/s0_address.rs
+++ b/va108xx/src/i2ca/s0_address.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_address::W`](W) writer structure"]
 impl crate::Writable for S0AddressSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESS to value 0"]
-impl crate::Resettable for S0AddressSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0AddressSpec {}
--- a/va108xx/src/i2ca/s0_addressb.rs
+++ b/va108xx/src/i2ca/s0_addressb.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressbSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_addressb::W`](W) writer structure"]
 impl crate::Writable for S0AddressbSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESSB to value 0"]
-impl crate::Resettable for S0AddressbSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0AddressbSpec {}
--- a/va108xx/src/i2ca/s0_addressmask.rs
+++ b/va108xx/src/i2ca/s0_addressmask.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressmaskSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_addressmask::W`](W) writer structure"]
 impl crate::Writable for S0AddressmaskSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESSMASK to value 0"]
-impl crate::Resettable for S0AddressmaskSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0AddressmaskSpec {}
--- a/va108xx/src/i2ca/s0_addressmaskb.rs
+++ b/va108xx/src/i2ca/s0_addressmaskb.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0AddressmaskbSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_addressmaskb::W`](W) writer structure"]
 impl crate::Writable for S0AddressmaskbSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_ADDRESSMASKB to value 0"]
-impl crate::Resettable for S0AddressmaskbSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0AddressmaskbSpec {}
--- a/va108xx/src/i2ca/s0_ctrl.rs
+++ b/va108xx/src/i2ca/s0_ctrl.rs
@@ -52,27 +52,27 @@ impl R {
 impl W {
    #[doc = "Bit 0 - I2C Enabled"]
    #[inline(always)]
-    pub fn clkenabled(&mut self) -> ClkenabledW<S0CtrlSpec> {
+    pub fn clkenabled(&mut self) -> ClkenabledW<'_, S0CtrlSpec> {
        ClkenabledW::new(self, 0)
    }
    #[doc = "Bit 1 - I2C Activated"]
    #[inline(always)]
-    pub fn enabled(&mut self) -> EnabledW<S0CtrlSpec> {
+    pub fn enabled(&mut self) -> EnabledW<'_, S0CtrlSpec> {
        EnabledW::new(self, 1)
    }
    #[doc = "Bit 2 - I2C Active"]
    #[inline(always)]
-    pub fn enable(&mut self) -> EnableW<S0CtrlSpec> {
+    pub fn enable(&mut self) -> EnableW<'_, S0CtrlSpec> {
        EnableW::new(self, 2)
    }
    #[doc = "Bit 3 - TX FIFIO Empty Mode"]
    #[inline(always)]
-    pub fn txfemd(&mut self) -> TxfemdW<S0CtrlSpec> {
+    pub fn txfemd(&mut self) -> TxfemdW<'_, S0CtrlSpec> {
        TxfemdW::new(self, 3)
    }
    #[doc = "Bit 4 - RX FIFO Full Mode"]
    #[inline(always)]
-    pub fn rxffmd(&mut self) -> RxffmdW<S0CtrlSpec> {
+    pub fn rxffmd(&mut self) -> RxffmdW<'_, S0CtrlSpec> {
        RxffmdW::new(self, 4)
    }
 }
@@ -86,10 +86,6 @@ impl crate::Readable for S0CtrlSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_ctrl::W`](W) writer structure"]
 impl crate::Writable for S0CtrlSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_CTRL to value 0"]
-impl crate::Resettable for S0CtrlSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0CtrlSpec {}
--- a/va108xx/src/i2ca/s0_data.rs
+++ b/va108xx/src/i2ca/s0_data.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0DataSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_data::W`](W) writer structure"]
 impl crate::Writable for S0DataSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_DATA to value 0"]
-impl crate::Resettable for S0DataSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0DataSpec {}
--- a/va108xx/src/i2ca/s0_fifo_clr.rs
+++ b/va108xx/src/i2ca/s0_fifo_clr.rs
@@ -7,12 +7,12 @@ pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
 impl W {
    #[doc = "Bit 0 - Clear Rx FIFO"]
    #[inline(always)]
-    pub fn rxfifo(&mut self) -> RxfifoW<S0FifoClrSpec> {
+    pub fn rxfifo(&mut self) -> RxfifoW<'_, S0FifoClrSpec> {
        RxfifoW::new(self, 0)
    }
    #[doc = "Bit 1 - Clear Tx FIFO"]
    #[inline(always)]
-    pub fn txfifo(&mut self) -> TxfifoW<S0FifoClrSpec> {
+    pub fn txfifo(&mut self) -> TxfifoW<'_, S0FifoClrSpec> {
        TxfifoW::new(self, 1)
    }
 }
@@ -24,10 +24,6 @@ impl crate::RegisterSpec for S0FifoClrSpec {
 #[doc = "`write(|w| ..)` method takes [`s0_fifo_clr::W`](W) writer structure"]
 impl crate::Writable for S0FifoClrSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_FIFO_CLR to value 0"]
-impl crate::Resettable for S0FifoClrSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0FifoClrSpec {}
--- a/va108xx/src/i2ca/s0_irq_enb.rs
+++ b/va108xx/src/i2ca/s0_irq_enb.rs
@@ -151,82 +151,82 @@ impl R {
 impl W {
    #[doc = "Bit 0 - Controller Complted a Transaction"]
    #[inline(always)]
-    pub fn completed(&mut self) -> CompletedW<S0IrqEnbSpec> {
+    pub fn completed(&mut self) -> CompletedW<'_, S0IrqEnbSpec> {
        CompletedW::new(self, 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
-    pub fn idle(&mut self) -> IdleW<S0IrqEnbSpec> {
+    pub fn idle(&mut self) -> IdleW<'_, S0IrqEnbSpec> {
        IdleW::new(self, 1)
    }
    #[doc = "Bit 2 - Controller is Waiting"]
    #[inline(always)]
-    pub fn waiting(&mut self) -> WaitingW<S0IrqEnbSpec> {
+    pub fn waiting(&mut self) -> WaitingW<'_, S0IrqEnbSpec> {
        WaitingW::new(self, 2)
    }
    #[doc = "Bit 3 - Controller is Tx Stalled"]
    #[inline(always)]
-    pub fn txstalled(&mut self) -> TxstalledW<S0IrqEnbSpec> {
+    pub fn txstalled(&mut self) -> TxstalledW<'_, S0IrqEnbSpec> {
        TxstalledW::new(self, 3)
    }
    #[doc = "Bit 4 - Controller is Rx Stalled"]
    #[inline(always)]
-    pub fn rxstalled(&mut self) -> RxstalledW<S0IrqEnbSpec> {
+    pub fn rxstalled(&mut self) -> RxstalledW<'_, S0IrqEnbSpec> {
        RxstalledW::new(self, 4)
    }
    #[doc = "Bit 5 - I2C Address Match"]
    #[inline(always)]
-    pub fn addressmatch(&mut self) -> AddressmatchW<S0IrqEnbSpec> {
+    pub fn addressmatch(&mut self) -> AddressmatchW<'_, S0IrqEnbSpec> {
        AddressmatchW::new(self, 5)
    }
    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
    #[inline(always)]
-    pub fn nackdata(&mut self) -> NackdataW<S0IrqEnbSpec> {
+    pub fn nackdata(&mut self) -> NackdataW<'_, S0IrqEnbSpec> {
        NackdataW::new(self, 6)
    }
    #[doc = "Bit 7 - Pending Data is first Byte following Address"]
    #[inline(always)]
-    pub fn rxdatafirst(&mut self) -> RxdatafirstW<S0IrqEnbSpec> {
+    pub fn rxdatafirst(&mut self) -> RxdatafirstW<'_, S0IrqEnbSpec> {
        RxdatafirstW::new(self, 7)
    }
    #[doc = "Bit 8 - I2C Start Condition"]
    #[inline(always)]
-    pub fn i2c_start(&mut self) -> I2cStartW<S0IrqEnbSpec> {
+    pub fn i2c_start(&mut self) -> I2cStartW<'_, S0IrqEnbSpec> {
        I2cStartW::new(self, 8)
    }
    #[doc = "Bit 9 - I2C Stop Condition"]
    #[inline(always)]
-    pub fn i2c_stop(&mut self) -> I2cStopW<S0IrqEnbSpec> {
+    pub fn i2c_stop(&mut self) -> I2cStopW<'_, S0IrqEnbSpec> {
        I2cStopW::new(self, 9)
    }
    #[doc = "Bit 10 - TX FIFO Underflowed"]
    #[inline(always)]
-    pub fn txunderflow(&mut self) -> TxunderflowW<S0IrqEnbSpec> {
+    pub fn txunderflow(&mut self) -> TxunderflowW<'_, S0IrqEnbSpec> {
        TxunderflowW::new(self, 10)
    }
    #[doc = "Bit 11 - TX FIFO Overflowed"]
    #[inline(always)]
-    pub fn rxoverflow(&mut self) -> RxoverflowW<S0IrqEnbSpec> {
+    pub fn rxoverflow(&mut self) -> RxoverflowW<'_, S0IrqEnbSpec> {
        RxoverflowW::new(self, 11)
    }
    #[doc = "Bit 12 - TX FIFO Ready"]
    #[inline(always)]
-    pub fn txready(&mut self) -> TxreadyW<S0IrqEnbSpec> {
+    pub fn txready(&mut self) -> TxreadyW<'_, S0IrqEnbSpec> {
        TxreadyW::new(self, 12)
    }
    #[doc = "Bit 13 - RX FIFO Ready"]
    #[inline(always)]
-    pub fn rxready(&mut self) -> RxreadyW<S0IrqEnbSpec> {
+    pub fn rxready(&mut self) -> RxreadyW<'_, S0IrqEnbSpec> {
        RxreadyW::new(self, 13)
    }
    #[doc = "Bit 14 - TX FIFO Empty"]
    #[inline(always)]
-    pub fn txempty(&mut self) -> TxemptyW<S0IrqEnbSpec> {
+    pub fn txempty(&mut self) -> TxemptyW<'_, S0IrqEnbSpec> {
        TxemptyW::new(self, 14)
    }
    #[doc = "Bit 15 - RX FIFO Full"]
    #[inline(always)]
-    pub fn rxfull(&mut self) -> RxfullW<S0IrqEnbSpec> {
+    pub fn rxfull(&mut self) -> RxfullW<'_, S0IrqEnbSpec> {
        RxfullW::new(self, 15)
    }
 }
@@ -240,10 +240,6 @@ impl crate::Readable for S0IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_irq_enb::W`](W) writer structure"]
 impl crate::Writable for S0IrqEnbSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_IRQ_ENB to value 0"]
-impl crate::Resettable for S0IrqEnbSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0IrqEnbSpec {}
--- a/va108xx/src/i2ca/s0_lastaddress.rs
+++ b/va108xx/src/i2ca/s0_lastaddress.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0LastaddressSpec {
 #[doc = "`read()` method returns [`s0_lastaddress::R`](R) reader structure"]
 impl crate::Readable for S0LastaddressSpec {}
 #[doc = "`reset()` method sets S0_LASTADDRESS to value 0"]
-impl crate::Resettable for S0LastaddressSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0LastaddressSpec {}
--- a/va108xx/src/i2ca/s0_maxwords.rs
+++ b/va108xx/src/i2ca/s0_maxwords.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0MaxwordsSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_maxwords::W`](W) writer structure"]
 impl crate::Writable for S0MaxwordsSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_MAXWORDS to value 0"]
-impl crate::Resettable for S0MaxwordsSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0MaxwordsSpec {}
--- a/va108xx/src/i2ca/s0_rxcount.rs
+++ b/va108xx/src/i2ca/s0_rxcount.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0RxcountSpec {
 #[doc = "`read()` method returns [`s0_rxcount::R`](R) reader structure"]
 impl crate::Readable for S0RxcountSpec {}
 #[doc = "`reset()` method sets S0_RXCOUNT to value 0"]
-impl crate::Resettable for S0RxcountSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0RxcountSpec {}
--- a/va108xx/src/i2ca/s0_rxfifoirqtrg.rs
+++ b/va108xx/src/i2ca/s0_rxfifoirqtrg.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0RxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_rxfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for S0RxfifoirqtrgSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_RXFIFOIRQTRG to value 0"]
-impl crate::Resettable for S0RxfifoirqtrgSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0RxfifoirqtrgSpec {}
--- a/va108xx/src/i2ca/s0_state.rs
+++ b/va108xx/src/i2ca/s0_state.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0StateSpec {
 #[doc = "`read()` method returns [`s0_state::R`](R) reader structure"]
 impl crate::Readable for S0StateSpec {}
 #[doc = "`reset()` method sets S0_STATE to value 0"]
-impl crate::Resettable for S0StateSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0StateSpec {}
--- a/va108xx/src/i2ca/s0_status.rs
+++ b/va108xx/src/i2ca/s0_status.rs
@@ -129,6 +129,4 @@ impl crate::RegisterSpec for S0StatusSpec {
 #[doc = "`read()` method returns [`s0_status::R`](R) reader structure"]
 impl crate::Readable for S0StatusSpec {}
 #[doc = "`reset()` method sets S0_STATUS to value 0"]
-impl crate::Resettable for S0StatusSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0StatusSpec {}
--- a/va108xx/src/i2ca/s0_txcount.rs
+++ b/va108xx/src/i2ca/s0_txcount.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for S0TxcountSpec {
 #[doc = "`read()` method returns [`s0_txcount::R`](R) reader structure"]
 impl crate::Readable for S0TxcountSpec {}
 #[doc = "`reset()` method sets S0_TXCOUNT to value 0"]
-impl crate::Resettable for S0TxcountSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0TxcountSpec {}
--- a/va108xx/src/i2ca/s0_txfifoirqtrg.rs
+++ b/va108xx/src/i2ca/s0_txfifoirqtrg.rs
@@ -19,10 +19,6 @@ impl crate::Readable for S0TxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`s0_txfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for S0TxfifoirqtrgSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets S0_TXFIFOIRQTRG to value 0"]
-impl crate::Resettable for S0TxfifoirqtrgSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for S0TxfifoirqtrgSpec {}
--- a/va108xx/src/i2ca/state.rs
+++ b/va108xx/src/i2ca/state.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for StateSpec {
 #[doc = "`read()` method returns [`state::R`](R) reader structure"]
 impl crate::Readable for StateSpec {}
 #[doc = "`reset()` method sets STATE to value 0"]
-impl crate::Resettable for StateSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for StateSpec {}
--- a/va108xx/src/i2ca/status.rs
+++ b/va108xx/src/i2ca/status.rs
@@ -115,6 +115,4 @@ impl crate::RegisterSpec for StatusSpec {
 #[doc = "`read()` method returns [`status::R`](R) reader structure"]
 impl crate::Readable for StatusSpec {}
 #[doc = "`reset()` method sets STATUS to value 0"]
-impl crate::Resettable for StatusSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for StatusSpec {}
--- a/va108xx/src/i2ca/tmconfig.rs
+++ b/va108xx/src/i2ca/tmconfig.rs
@@ -19,10 +19,6 @@ impl crate::Readable for TmconfigSpec {}
 #[doc = "`write(|w| ..)` method takes [`tmconfig::W`](W) writer structure"]
 impl crate::Writable for TmconfigSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TMCONFIG to value 0"]
-impl crate::Resettable for TmconfigSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for TmconfigSpec {}
--- a/va108xx/src/i2ca/txcount.rs
+++ b/va108xx/src/i2ca/txcount.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for TxcountSpec {
 #[doc = "`read()` method returns [`txcount::R`](R) reader structure"]
 impl crate::Readable for TxcountSpec {}
 #[doc = "`reset()` method sets TXCOUNT to value 0"]
-impl crate::Resettable for TxcountSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for TxcountSpec {}
--- a/va108xx/src/i2ca/txfifoirqtrg.rs
+++ b/va108xx/src/i2ca/txfifoirqtrg.rs
@@ -19,10 +19,6 @@ impl crate::Readable for TxfifoirqtrgSpec {}
 #[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
 impl crate::Writable for TxfifoirqtrgSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
-impl crate::Resettable for TxfifoirqtrgSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for TxfifoirqtrgSpec {}
--- a/va108xx/src/i2ca/words.rs
+++ b/va108xx/src/i2ca/words.rs
@@ -19,10 +19,6 @@ impl crate::Readable for WordsSpec {}
 #[doc = "`write(|w| ..)` method takes [`words::W`](W) writer structure"]
 impl crate::Writable for WordsSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets WORDS to value 0"]
-impl crate::Resettable for WordsSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for WordsSpec {}
--- a/va108xx/src/ioconfig.rs
+++ b/va108xx/src/ioconfig.rs
@@ -2,7 +2,7 @@
 #[doc = "Register block"]
 pub struct RegisterBlock {
    porta: [Porta; 32],
-    portb0: [Portb; 32],
+    portb: [Portb; 32],
    _reserved2: [u8; 0x0efc],
    perid: Perid,
 }
@@ -20,14 +20,14 @@ impl RegisterBlock {
    }
    #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
    #[inline(always)]
-    pub const fn portb0(&self, n: usize) -> &Portb {
-        &self.portb0[n]
+    pub const fn portb(&self, n: usize) -> &Portb {
+        &self.portb[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x80..0x100 - PORTB Pin Configuration Register"]
    #[inline(always)]
-    pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
-        self.portb0.iter()
+    pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> {
+        self.portb.iter()
    }
    #[doc = "0xffc - Peripheral ID Register"]
    #[inline(always)]
@@ -35,16 +35,14 @@ impl RegisterBlock {
        &self.perid
    }
 }
-#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`]
-module"]
+#[doc = "PORTA (rw) register accessor: PORTA Pin Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`porta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`porta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@porta`] module"]
 #[doc(alias = "PORTA")]
 pub type Porta = crate::Reg<porta::PortaSpec>;
 #[doc = "PORTA Pin Configuration Register"]
 pub mod porta;
 pub use porta as portb;
 pub use Porta as Portb;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
-module"]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]
--- a/va108xx/src/ioconfig/porta.rs
+++ b/va108xx/src/ioconfig/porta.rs
@@ -215,57 +215,57 @@ impl R {
 impl W {
    #[doc = "Bits 0:2 - Input Filter Selectoin"]
    #[inline(always)]
-    pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
+    pub fn flttype(&mut self) -> FlttypeW<'_, PortaSpec> {
        FlttypeW::new(self, 0)
    }
    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
    #[inline(always)]
-    pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
+    pub fn fltclk(&mut self) -> FltclkW<'_, PortaSpec> {
        FltclkW::new(self, 3)
    }
    #[doc = "Bit 6 - Input Invert Selection"]
    #[inline(always)]
-    pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
+    pub fn invinp(&mut self) -> InvinpW<'_, PortaSpec> {
        InvinpW::new(self, 6)
    }
    #[doc = "Bit 7 - Input Enable While Output enabled"]
    #[inline(always)]
-    pub fn iewo(&mut self) -> IewoW<PortaSpec> {
+    pub fn iewo(&mut self) -> IewoW<'_, PortaSpec> {
        IewoW::new(self, 7)
    }
    #[doc = "Bit 8 - Output Open Drain Mode"]
    #[inline(always)]
-    pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
+    pub fn opendrn(&mut self) -> OpendrnW<'_, PortaSpec> {
        OpendrnW::new(self, 8)
    }
    #[doc = "Bit 9 - Output Invert Selection"]
    #[inline(always)]
-    pub fn invout(&mut self) -> InvoutW<PortaSpec> {
+    pub fn invout(&mut self) -> InvoutW<'_, PortaSpec> {
        InvoutW::new(self, 9)
    }
    #[doc = "Bit 10 - Internal Pull up/down level"]
    #[inline(always)]
-    pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
+    pub fn plevel(&mut self) -> PlevelW<'_, PortaSpec> {
        PlevelW::new(self, 10)
    }
    #[doc = "Bit 11 - Enable Internal Pull up/down"]
    #[inline(always)]
-    pub fn pen(&mut self) -> PenW<PortaSpec> {
+    pub fn pen(&mut self) -> PenW<'_, PortaSpec> {
        PenW::new(self, 11)
    }
    #[doc = "Bit 12 - Enable Pull when output active"]
    #[inline(always)]
-    pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
+    pub fn pwoa(&mut self) -> PwoaW<'_, PortaSpec> {
        PwoaW::new(self, 12)
    }
    #[doc = "Bits 13:15 - Pin Function Selection"]
    #[inline(always)]
-    pub fn funsel(&mut self) -> FunselW<PortaSpec> {
+    pub fn funsel(&mut self) -> FunselW<'_, PortaSpec> {
        FunselW::new(self, 13)
    }
    #[doc = "Bit 16 - IO Pin Disable"]
    #[inline(always)]
-    pub fn iodis(&mut self) -> IodisW<PortaSpec> {
+    pub fn iodis(&mut self) -> IodisW<'_, PortaSpec> {
        IodisW::new(self, 16)
    }
 }
@@ -279,11 +279,6 @@ impl crate::Readable for PortaSpec {}
 #[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"]
 impl crate::Writable for PortaSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-}
-#[doc = "`reset()` method sets PORTA[%s]
-to value 0"]
-impl crate::Resettable for PortaSpec {
-    const RESET_VALUE: u32 = 0;
 }
+#[doc = "`reset()` method sets PORTA[%s] to value 0"]
+impl crate::Resettable for PortaSpec {}
--- a/va108xx/src/irqsel.rs
+++ b/va108xx/src/irqsel.rs
@@ -1,20 +1,20 @@
 #[repr(C)]
 #[doc = "Register block"]
 pub struct RegisterBlock {
-    porta0: [Porta; 32],
-    portb0: [Portb; 32],
-    tim0: [Tim; 32],
-    uart0: [Uart; 4],
-    spi0: [Spi; 4],
-    i2c_ms0: [I2cMs; 4],
-    i2c_sl0: [I2cSl; 4],
+    porta: [Porta; 32],
+    portb: [Portb; 32],
+    tim: [Tim; 32],
+    uart: [Uart; 4],
+    spi: [Spi; 4],
+    i2c_ms: [I2cMs; 4],
+    i2c_sl: [I2cSl; 4],
    int_ram_sbe: IntRamSbe,
    int_ram_mbe: IntRamMbe,
    int_rom_sbe: IntRomSbe,
    int_rom_mbe: IntRomMbe,
    txev: Txev,
    _reserved12: [u8; 0x062c],
-    irqs0: [Irqs; 32],
+    irqs: [Irqs; 32],
    _reserved13: [u8; 0x68],
    edbgrq: Edbgrq,
    mereset: Mereset,
@@ -27,80 +27,80 @@ pub struct RegisterBlock {
 impl RegisterBlock {
    #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn porta0(&self, n: usize) -> &Porta {
-        &self.porta0[n]
+    pub const fn porta(&self, n: usize) -> &Porta {
+        &self.porta[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x00..0x80 - PORTA Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn porta0_iter(&self) -> impl Iterator<Item = &Porta> {
-        self.porta0.iter()
+    pub fn porta_iter(&self) -> impl Iterator<Item = &Porta> {
+        self.porta.iter()
    }
    #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn portb0(&self, n: usize) -> &Portb {
-        &self.portb0[n]
+    pub const fn portb(&self, n: usize) -> &Portb {
+        &self.portb[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x80..0x100 - PORTB Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn portb0_iter(&self) -> impl Iterator<Item = &Portb> {
-        self.portb0.iter()
+    pub fn portb_iter(&self) -> impl Iterator<Item = &Portb> {
+        self.portb.iter()
    }
    #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn tim0(&self, n: usize) -> &Tim {
-        &self.tim0[n]
+    pub const fn tim(&self, n: usize) -> &Tim {
+        &self.tim[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x100..0x180 - TIM Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn tim0_iter(&self) -> impl Iterator<Item = &Tim> {
-        self.tim0.iter()
+    pub fn tim_iter(&self) -> impl Iterator<Item = &Tim> {
+        self.tim.iter()
    }
    #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn uart0(&self, n: usize) -> &Uart {
-        &self.uart0[n]
+    pub const fn uart(&self, n: usize) -> &Uart {
+        &self.uart[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x180..0x190 - UART Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn uart0_iter(&self) -> impl Iterator<Item = &Uart> {
-        self.uart0.iter()
+    pub fn uart_iter(&self) -> impl Iterator<Item = &Uart> {
+        self.uart.iter()
    }
    #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn spi0(&self, n: usize) -> &Spi {
-        &self.spi0[n]
+    pub const fn spi(&self, n: usize) -> &Spi {
+        &self.spi[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x190..0x1a0 - SPI Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn spi0_iter(&self) -> impl Iterator<Item = &Spi> {
-        self.spi0.iter()
+    pub fn spi_iter(&self) -> impl Iterator<Item = &Spi> {
+        self.spi.iter()
    }
    #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn i2c_ms0(&self, n: usize) -> &I2cMs {
-        &self.i2c_ms0[n]
+    pub const fn i2c_ms(&self, n: usize) -> &I2cMs {
+        &self.i2c_ms[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x1a0..0x1b0 - Master I2C Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn i2c_ms0_iter(&self) -> impl Iterator<Item = &I2cMs> {
-        self.i2c_ms0.iter()
+    pub fn i2c_ms_iter(&self) -> impl Iterator<Item = &I2cMs> {
+        self.i2c_ms.iter()
    }
    #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
    #[inline(always)]
-    pub const fn i2c_sl0(&self, n: usize) -> &I2cSl {
-        &self.i2c_sl0[n]
+    pub const fn i2c_sl(&self, n: usize) -> &I2cSl {
+        &self.i2c_sl[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x1b0..0x1c0 - Slave I2C Interrupt Redirect Selection"]
    #[inline(always)]
-    pub fn i2c_sl0_iter(&self) -> impl Iterator<Item = &I2cSl> {
-        self.i2c_sl0.iter()
+    pub fn i2c_sl_iter(&self) -> impl Iterator<Item = &I2cSl> {
+        self.i2c_sl.iter()
    }
    #[doc = "0x1c0 - Internal Memory RAM SBE Interrupt Redirect Selection"]
    #[inline(always)]
@@ -129,14 +129,14 @@ impl RegisterBlock {
    }
    #[doc = "0x800..0x880 - Interrupt Status Register"]
    #[inline(always)]
-    pub const fn irqs0(&self, n: usize) -> &Irqs {
-        &self.irqs0[n]
+    pub const fn irqs(&self, n: usize) -> &Irqs {
+        &self.irqs[n]
    }
    #[doc = "Iterator for array of:"]
    #[doc = "0x800..0x880 - Interrupt Status Register"]
    #[inline(always)]
-    pub fn irqs0_iter(&self) -> impl Iterator<Item = &Irqs> {
-        self.irqs0.iter()
+    pub fn irqs_iter(&self) -> impl Iterator<Item = &Irqs> {
+        self.irqs.iter()
    }
    #[doc = "0x8e8 - EDBGRQ Status Register"]
    #[inline(always)]
@@ -169,8 +169,7 @@ impl RegisterBlock {
        &self.perid
    }
 }
-#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`]
-module"]
+#[doc = "INT_RAM_SBE (rw) register accessor: Internal Memory RAM SBE Interrupt Redirect Selection\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ram_sbe::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ram_sbe::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ram_sbe`] module"]
 #[doc(alias = "INT_RAM_SBE")]
 pub type IntRamSbe = crate::Reg<int_ram_sbe::IntRamSbeSpec>;
 #[doc = "Internal Memory RAM SBE Interrupt Redirect Selection"]
@@ -197,8 +196,7 @@ pub use IntRamSbe as IntRamMbe;
 pub use IntRamSbe as IntRomSbe;
 pub use IntRamSbe as IntRomMbe;
 pub use IntRamSbe as Txev;
-#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`]
-module"]
+#[doc = "NMI (r) register accessor: NMI Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`nmi::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@nmi`] module"]
 #[doc(alias = "NMI")]
 pub type Nmi = crate::Reg<nmi::NmiSpec>;
 #[doc = "NMI Status Register"]
@@ -213,8 +211,7 @@ pub use Nmi as Watchdog;
 pub use Nmi as Mereset;
 pub use Nmi as Edbgrq;
 pub use Nmi as Irqs;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
-module"]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]
--- a/va108xx/src/irqsel/int_ram_sbe.rs
+++ b/va108xx/src/irqsel/int_ram_sbe.rs
@@ -19,8 +19,6 @@ impl crate::Readable for IntRamSbeSpec {}
 #[doc = "`write(|w| ..)` method takes [`int_ram_sbe::W`](W) writer structure"]
 impl crate::Writable for IntRamSbeSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets INT_RAM_SBE to value 0xffff_ffff"]
 impl crate::Resettable for IntRamSbeSpec {
--- a/va108xx/src/irqsel/nmi.rs
+++ b/va108xx/src/irqsel/nmi.rs
@@ -17,6 +17,4 @@ impl crate::RegisterSpec for NmiSpec {
 #[doc = "`read()` method returns [`nmi::R`](R) reader structure"]
 impl crate::Readable for NmiSpec {}
 #[doc = "`reset()` method sets NMI to value 0"]
-impl crate::Resettable for NmiSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for NmiSpec {}
--- a/va108xx/src/lib.rs
+++ b/va108xx/src/lib.rs
--- a/va108xx/src/porta.rs
+++ b/va108xx/src/porta.rs
@@ -45,7 +45,7 @@ impl RegisterBlock {
    }
    #[doc = "0x04 - Data In Raw Register by Byte"]
    #[inline(always)]
-    pub const fn datainrawbyte0(&self, n: usize) -> &Datainrawbyte {
+    pub const fn datainrawbyte(&self, n: usize) -> &Datainrawbyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() }
@@ -53,7 +53,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x04 - Data In Raw Register by Byte"]
    #[inline(always)]
-    pub fn datainrawbyte0_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
+    pub fn datainrawbyte_iter(&self) -> impl Iterator<Item = &Datainrawbyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(n).cast() })
    }
@@ -83,7 +83,7 @@ impl RegisterBlock {
    }
    #[doc = "0x0c - Data Out Register by Byte"]
    #[inline(always)]
-    pub const fn dataoutrawbyte0(&self, n: usize) -> &Dataoutrawbyte {
+    pub const fn dataoutrawbyte(&self, n: usize) -> &Dataoutrawbyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() }
@@ -91,7 +91,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x0c - Data Out Register by Byte"]
    #[inline(always)]
-    pub fn dataoutrawbyte0_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
+    pub fn dataoutrawbyte_iter(&self) -> impl Iterator<Item = &Dataoutrawbyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(12).add(n).cast() })
    }
@@ -102,7 +102,7 @@ impl RegisterBlock {
    }
    #[doc = "0x10 - Set Out Register by Byte"]
    #[inline(always)]
-    pub const fn setoutbyte0(&self, n: usize) -> &Setoutbyte {
+    pub const fn setoutbyte(&self, n: usize) -> &Setoutbyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() }
@@ -110,7 +110,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x10 - Set Out Register by Byte"]
    #[inline(always)]
-    pub fn setoutbyte0_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
+    pub fn setoutbyte_iter(&self) -> impl Iterator<Item = &Setoutbyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(16).add(n).cast() })
    }
@@ -121,7 +121,7 @@ impl RegisterBlock {
    }
    #[doc = "0x14 - Clear Out Register by Byte"]
    #[inline(always)]
-    pub const fn clroutbyte0(&self, n: usize) -> &Clroutbyte {
+    pub const fn clroutbyte(&self, n: usize) -> &Clroutbyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() }
@@ -129,7 +129,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x14 - Clear Out Register by Byte"]
    #[inline(always)]
-    pub fn clroutbyte0_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
+    pub fn clroutbyte_iter(&self) -> impl Iterator<Item = &Clroutbyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(20).add(n).cast() })
    }
@@ -140,7 +140,7 @@ impl RegisterBlock {
    }
    #[doc = "0x18 - Toggle Out Register by Byte"]
    #[inline(always)]
-    pub const fn togoutbyte0(&self, n: usize) -> &Togoutbyte {
+    pub const fn togoutbyte(&self, n: usize) -> &Togoutbyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() }
@@ -148,7 +148,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x18 - Toggle Out Register by Byte"]
    #[inline(always)]
-    pub fn togoutbyte0_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
+    pub fn togoutbyte_iter(&self) -> impl Iterator<Item = &Togoutbyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).add(n).cast() })
    }
@@ -178,7 +178,7 @@ impl RegisterBlock {
    }
    #[doc = "0x20 - Direction Register by Byte"]
    #[inline(always)]
-    pub const fn dirbyte0(&self, n: usize) -> &Dirbyte {
+    pub const fn dirbyte(&self, n: usize) -> &Dirbyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() }
@@ -186,7 +186,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x20 - Direction Register by Byte"]
    #[inline(always)]
-    pub fn dirbyte0_iter(&self) -> impl Iterator<Item = &Dirbyte> {
+    pub fn dirbyte_iter(&self) -> impl Iterator<Item = &Dirbyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(32).add(n).cast() })
    }
@@ -197,7 +197,7 @@ impl RegisterBlock {
    }
    #[doc = "0x24 - Pulse Mode Register by Byte"]
    #[inline(always)]
-    pub const fn pulsebyte0(&self, n: usize) -> &Pulsebyte {
+    pub const fn pulsebyte(&self, n: usize) -> &Pulsebyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() }
@@ -205,7 +205,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x24 - Pulse Mode Register by Byte"]
    #[inline(always)]
-    pub fn pulsebyte0_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
+    pub fn pulsebyte_iter(&self) -> impl Iterator<Item = &Pulsebyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(36).add(n).cast() })
    }
@@ -216,7 +216,7 @@ impl RegisterBlock {
    }
    #[doc = "0x28 - Pulse Base Mode Register by Byte"]
    #[inline(always)]
-    pub const fn pulsebasebyte0(&self, n: usize) -> &Pulsebasebyte {
+    pub const fn pulsebasebyte(&self, n: usize) -> &Pulsebasebyte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() }
@@ -224,7 +224,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x28 - Pulse Base Mode Register by Byte"]
    #[inline(always)]
-    pub fn pulsebasebyte0_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
+    pub fn pulsebasebyte_iter(&self) -> impl Iterator<Item = &Pulsebasebyte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).add(n).cast() })
    }
@@ -235,7 +235,7 @@ impl RegisterBlock {
    }
    #[doc = "0x2c - Delay1 Register by Byte"]
    #[inline(always)]
-    pub const fn delay1byte0(&self, n: usize) -> &Delay1byte {
+    pub const fn delay1byte(&self, n: usize) -> &Delay1byte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() }
@@ -243,7 +243,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x2c - Delay1 Register by Byte"]
    #[inline(always)]
-    pub fn delay1byte0_iter(&self) -> impl Iterator<Item = &Delay1byte> {
+    pub fn delay1byte_iter(&self) -> impl Iterator<Item = &Delay1byte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(44).add(n).cast() })
    }
@@ -254,7 +254,7 @@ impl RegisterBlock {
    }
    #[doc = "0x30 - Delay2 Register by Byte"]
    #[inline(always)]
-    pub const fn delay2byte0(&self, n: usize) -> &Delay2byte {
+    pub const fn delay2byte(&self, n: usize) -> &Delay2byte {
        #[allow(clippy::no_effect)]
        [(); 4][n];
        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() }
@@ -262,7 +262,7 @@ impl RegisterBlock {
    #[doc = "Iterator for array of:"]
    #[doc = "0x30 - Delay2 Register by Byte"]
    #[inline(always)]
-    pub fn delay2byte0_iter(&self) -> impl Iterator<Item = &Delay2byte> {
+    pub fn delay2byte_iter(&self) -> impl Iterator<Item = &Delay2byte> {
        (0..4)
            .map(move |n| unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(48).add(n).cast() })
    }
@@ -312,14 +312,12 @@ impl RegisterBlock {
        &self.perid
    }
 }
-#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`]
-module"]
+#[doc = "DATAIN (r) register accessor: Data In Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datain::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datain`] module"]
 #[doc(alias = "DATAIN")]
 pub type Datain = crate::Reg<datain::DatainSpec>;
 #[doc = "Data In Register"]
 pub mod datain;
-#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`]
-module"]
+#[doc = "DATAINBYTE (r) register accessor: Data In Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datainbyte::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datainbyte`] module"]
 #[doc(alias = "DATAINBYTE")]
 pub type Datainbyte = crate::Reg<datainbyte::DatainbyteSpec>;
 #[doc = "Data In Register by Byte"]
@@ -328,14 +326,12 @@ pub use datain as datainraw;
 pub use datainbyte as datainrawbyte;
 pub use Datain as Datainraw;
 pub use Datainbyte as Datainrawbyte;
-#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`]
-module"]
+#[doc = "DATAOUT (w) register accessor: Data Out Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataout::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataout`] module"]
 #[doc(alias = "DATAOUT")]
 pub type Dataout = crate::Reg<dataout::DataoutSpec>;
 #[doc = "Data Out Register"]
 pub mod dataout;
-#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`]
-module"]
+#[doc = "DATAOUTBYTE (w) register accessor: Data Out Register by Byte\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dataoutbyte::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dataoutbyte`] module"]
 #[doc(alias = "DATAOUTBYTE")]
 pub type Dataoutbyte = crate::Reg<dataoutbyte::DataoutbyteSpec>;
 #[doc = "Data Out Register by Byte"]
@@ -356,14 +352,12 @@ pub use Dataoutbyte as Dataoutrawbyte;
 pub use Dataoutbyte as Setoutbyte;
 pub use Dataoutbyte as Clroutbyte;
 pub use Dataoutbyte as Togoutbyte;
-#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`]
-module"]
+#[doc = "DATAMASK (rw) register accessor: Data mask Register\n\nYou can [`read`](crate::Reg::read) this register and get [`datamask::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamask::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamask`] module"]
 #[doc(alias = "DATAMASK")]
 pub type Datamask = crate::Reg<datamask::DatamaskSpec>;
 #[doc = "Data mask Register"]
 pub mod datamask;
-#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`]
-module"]
+#[doc = "DATAMASKBYTE (rw) register accessor: Data Out Register by Byte\n\nYou can [`read`](crate::Reg::read) this register and get [`datamaskbyte::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`datamaskbyte::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@datamaskbyte`] module"]
 #[doc(alias = "DATAMASKBYTE")]
 pub type Datamaskbyte = crate::Reg<datamaskbyte::DatamaskbyteSpec>;
 #[doc = "Data Out Register by Byte"]
@@ -388,50 +382,42 @@ pub use Datamaskbyte as Pulsebyte;
 pub use Datamaskbyte as Pulsebasebyte;
 pub use Datamaskbyte as Delay1byte;
 pub use Datamaskbyte as Delay2byte;
-#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`]
-module"]
+#[doc = "IRQ_SEN (rw) register accessor: Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_sen::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_sen::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_sen`] module"]
 #[doc(alias = "IRQ_SEN")]
 pub type IrqSen = crate::Reg<irq_sen::IrqSenSpec>;
 #[doc = "Interrupt Sense Register (1:Level Sensitive, 0:Edge Sensitive)"]
 pub mod irq_sen;
-#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`]
-module"]
+#[doc = "IRQ_EDGE (rw) register accessor: Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_edge::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_edge::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_edge`] module"]
 #[doc(alias = "IRQ_EDGE")]
 pub type IrqEdge = crate::Reg<irq_edge::IrqEdgeSpec>;
 #[doc = "Interrupt Both Edge Register (1:Both Edges, 0:Single Edge)"]
 pub mod irq_edge;
-#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`]
-module"]
+#[doc = "IRQ_EVT (rw) register accessor: Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_evt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_evt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_evt`] module"]
 #[doc(alias = "IRQ_EVT")]
 pub type IrqEvt = crate::Reg<irq_evt::IrqEvtSpec>;
 #[doc = "Interrupt Event Register (1:HighLevel/L->H Edge, 0:LowLevel/H->L Edge)"]
 pub mod irq_evt;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
-module"]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
 pub mod irq_enb;
-#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`]
-module"]
+#[doc = "IRQ_RAW (r) register accessor: Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_raw`] module"]
 #[doc(alias = "IRQ_RAW")]
 pub type IrqRaw = crate::Reg<irq_raw::IrqRawSpec>;
 #[doc = "Raw Interrupt Status"]
 pub mod irq_raw;
-#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`]
-module"]
+#[doc = "IRQ_END (r) register accessor: Masked Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_end`] module"]
 #[doc(alias = "IRQ_END")]
 pub type IrqEnd = crate::Reg<irq_end::IrqEndSpec>;
 #[doc = "Masked Interrupt Status"]
 pub mod irq_end;
-#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`]
-module"]
+#[doc = "EDGE_STATUS (rw) register accessor: Edge Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`edge_status::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`edge_status::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@edge_status`] module"]
 #[doc(alias = "EDGE_STATUS")]
 pub type EdgeStatus = crate::Reg<edge_status::EdgeStatusSpec>;
 #[doc = "Edge Status Register"]
 pub mod edge_status;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
-module"]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]
--- a/va108xx/src/porta/datain.rs
+++ b/va108xx/src/porta/datain.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for DatainSpec {
 #[doc = "`read()` method returns [`datain::R`](R) reader structure"]
 impl crate::Readable for DatainSpec {}
 #[doc = "`reset()` method sets DATAIN to value 0"]
-impl crate::Resettable for DatainSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for DatainSpec {}
--- a/va108xx/src/porta/datainbyte.rs
+++ b/va108xx/src/porta/datainbyte.rs
@@ -13,8 +13,5 @@ impl crate::RegisterSpec for DatainbyteSpec {
 }
 #[doc = "`read()` method returns [`datainbyte::R`](R) reader structure"]
 impl crate::Readable for DatainbyteSpec {}
-#[doc = "`reset()` method sets DATAINBYTE[%s]
-to value 0"]
-impl crate::Resettable for DatainbyteSpec {
-    const RESET_VALUE: u8 = 0;
-}
+#[doc = "`reset()` method sets DATAINBYTE[%s] to value 0"]
+impl crate::Resettable for DatainbyteSpec {}
--- a/va108xx/src/porta/datamask.rs
+++ b/va108xx/src/porta/datamask.rs
@@ -19,10 +19,6 @@ impl crate::Readable for DatamaskSpec {}
 #[doc = "`write(|w| ..)` method takes [`datamask::W`](W) writer structure"]
 impl crate::Writable for DatamaskSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATAMASK to value 0"]
-impl crate::Resettable for DatamaskSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for DatamaskSpec {}
--- a/va108xx/src/porta/datamaskbyte.rs
+++ b/va108xx/src/porta/datamaskbyte.rs
@@ -19,11 +19,6 @@ impl crate::Readable for DatamaskbyteSpec {}
 #[doc = "`write(|w| ..)` method takes [`datamaskbyte::W`](W) writer structure"]
 impl crate::Writable for DatamaskbyteSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-}
-#[doc = "`reset()` method sets DATAMASKBYTE[%s]
-to value 0"]
-impl crate::Resettable for DatamaskbyteSpec {
-    const RESET_VALUE: u8 = 0;
 }
+#[doc = "`reset()` method sets DATAMASKBYTE[%s] to value 0"]
+impl crate::Resettable for DatamaskbyteSpec {}
--- a/va108xx/src/porta/dataout.rs
+++ b/va108xx/src/porta/dataout.rs
@@ -15,10 +15,6 @@ impl crate::RegisterSpec for DataoutSpec {
 #[doc = "`write(|w| ..)` method takes [`dataout::W`](W) writer structure"]
 impl crate::Writable for DataoutSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets DATAOUT to value 0"]
-impl crate::Resettable for DataoutSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for DataoutSpec {}
--- a/va108xx/src/porta/dataoutbyte.rs
+++ b/va108xx/src/porta/dataoutbyte.rs
@@ -15,11 +15,6 @@ impl crate::RegisterSpec for DataoutbyteSpec {
 #[doc = "`write(|w| ..)` method takes [`dataoutbyte::W`](W) writer structure"]
 impl crate::Writable for DataoutbyteSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u8 = 0;
-}
-#[doc = "`reset()` method sets DATAOUTBYTE[%s]
-to value 0"]
-impl crate::Resettable for DataoutbyteSpec {
-    const RESET_VALUE: u8 = 0;
 }
+#[doc = "`reset()` method sets DATAOUTBYTE[%s] to value 0"]
+impl crate::Resettable for DataoutbyteSpec {}
--- a/va108xx/src/porta/edge_status.rs
+++ b/va108xx/src/porta/edge_status.rs
@@ -19,10 +19,6 @@ impl crate::Readable for EdgeStatusSpec {}
 #[doc = "`write(|w| ..)` method takes [`edge_status::W`](W) writer structure"]
 impl crate::Writable for EdgeStatusSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets EDGE_STATUS to value 0"]
-impl crate::Resettable for EdgeStatusSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for EdgeStatusSpec {}
--- a/va108xx/src/porta/irq_edge.rs
+++ b/va108xx/src/porta/irq_edge.rs
@@ -19,10 +19,6 @@ impl crate::Readable for IrqEdgeSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_edge::W`](W) writer structure"]
 impl crate::Writable for IrqEdgeSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_EDGE to value 0"]
-impl crate::Resettable for IrqEdgeSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqEdgeSpec {}
--- a/va108xx/src/porta/irq_enb.rs
+++ b/va108xx/src/porta/irq_enb.rs
@@ -19,10 +19,6 @@ impl crate::Readable for IrqEnbSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
 impl crate::Writable for IrqEnbSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_ENB to value 0"]
-impl crate::Resettable for IrqEnbSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqEnbSpec {}
--- a/va108xx/src/porta/irq_end.rs
+++ b/va108xx/src/porta/irq_end.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for IrqEndSpec {
 #[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
 impl crate::Readable for IrqEndSpec {}
 #[doc = "`reset()` method sets IRQ_END to value 0"]
-impl crate::Resettable for IrqEndSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqEndSpec {}
--- a/va108xx/src/porta/irq_evt.rs
+++ b/va108xx/src/porta/irq_evt.rs
@@ -19,10 +19,6 @@ impl crate::Readable for IrqEvtSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_evt::W`](W) writer structure"]
 impl crate::Writable for IrqEvtSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_EVT to value 0"]
-impl crate::Resettable for IrqEvtSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqEvtSpec {}
--- a/va108xx/src/porta/irq_raw.rs
+++ b/va108xx/src/porta/irq_raw.rs
@@ -14,6 +14,4 @@ impl crate::RegisterSpec for IrqRawSpec {
 #[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
 impl crate::Readable for IrqRawSpec {}
 #[doc = "`reset()` method sets IRQ_RAW to value 0"]
-impl crate::Resettable for IrqRawSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqRawSpec {}
--- a/va108xx/src/porta/irq_sen.rs
+++ b/va108xx/src/porta/irq_sen.rs
@@ -19,10 +19,6 @@ impl crate::Readable for IrqSenSpec {}
 #[doc = "`write(|w| ..)` method takes [`irq_sen::W`](W) writer structure"]
 impl crate::Writable for IrqSenSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets IRQ_SEN to value 0"]
-impl crate::Resettable for IrqSenSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for IrqSenSpec {}
--- a/va108xx/src/spia.rs
+++ b/va108xx/src/spia.rs
@@ -89,38 +89,32 @@ impl RegisterBlock {
        &self.perid
    }
 }
-#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`]
-module"]
+#[doc = "CTRL0 (rw) register accessor: Control Register 0\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl0`] module"]
 #[doc(alias = "CTRL0")]
 pub type Ctrl0 = crate::Reg<ctrl0::Ctrl0Spec>;
 #[doc = "Control Register 0"]
 pub mod ctrl0;
-#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`]
-module"]
+#[doc = "CTRL1 (rw) register accessor: Control Register 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl1`] module"]
 #[doc(alias = "CTRL1")]
 pub type Ctrl1 = crate::Reg<ctrl1::Ctrl1Spec>;
 #[doc = "Control Register 1"]
 pub mod ctrl1;
-#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
-module"]
+#[doc = "DATA (rw) register accessor: Data Input/Output\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`] module"]
 #[doc(alias = "DATA")]
 pub type Data = crate::Reg<data::DataSpec>;
 #[doc = "Data Input/Output"]
 pub mod data;
-#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`]
-module"]
+#[doc = "STATUS (r) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@status`] module"]
 #[doc(alias = "STATUS")]
 pub type Status = crate::Reg<status::StatusSpec>;
 #[doc = "Status Register"]
 pub mod status;
-#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`]
-module"]
+#[doc = "CLKPRESCALE (rw) register accessor: Clock Pre Scale divide value\n\nYou can [`read`](crate::Reg::read) this register and get [`clkprescale::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkprescale::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkprescale`] module"]
 #[doc(alias = "CLKPRESCALE")]
 pub type Clkprescale = crate::Reg<clkprescale::ClkprescaleSpec>;
 #[doc = "Clock Pre Scale divide value"]
 pub mod clkprescale;
-#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`]
-module"]
+#[doc = "IRQ_ENB (rw) register accessor: Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@irq_enb`] module"]
 #[doc(alias = "IRQ_ENB")]
 pub type IrqEnb = crate::Reg<irq_enb::IrqEnbSpec>;
 #[doc = "Interrupt Enable Register"]
@@ -131,32 +125,27 @@ pub use irq_enb as irq_clr;
 pub use IrqEnb as IrqRaw;
 pub use IrqEnb as IrqEnd;
 pub use IrqEnb as IrqClr;
-#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`]
-module"]
+#[doc = "RXFIFOIRQTRG (rw) register accessor: Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rxfifoirqtrg`] module"]
 #[doc(alias = "RXFIFOIRQTRG")]
 pub type Rxfifoirqtrg = crate::Reg<rxfifoirqtrg::RxfifoirqtrgSpec>;
 #[doc = "Rx FIFO IRQ Trigger Level"]
 pub mod rxfifoirqtrg;
-#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`]
-module"]
+#[doc = "TXFIFOIRQTRG (rw) register accessor: Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::Reg::read) this register and get [`txfifoirqtrg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txfifoirqtrg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@txfifoirqtrg`] module"]
 #[doc(alias = "TXFIFOIRQTRG")]
 pub type Txfifoirqtrg = crate::Reg<txfifoirqtrg::TxfifoirqtrgSpec>;
 #[doc = "Tx FIFO IRQ Trigger Level"]
 pub mod txfifoirqtrg;
-#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`]
-module"]
+#[doc = "FIFO_CLR (w) register accessor: Clear FIFO Register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@fifo_clr`] module"]
 #[doc(alias = "FIFO_CLR")]
 pub type FifoClr = crate::Reg<fifo_clr::FifoClrSpec>;
 #[doc = "Clear FIFO Register"]
 pub mod fifo_clr;
-#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`]
-module"]
+#[doc = "STATE (r) register accessor: Internal STATE of SPI Controller\n\nYou can [`read`](crate::Reg::read) this register and get [`state::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@state`] module"]
 #[doc(alias = "STATE")]
 pub type State = crate::Reg<state::StateSpec>;
 #[doc = "Internal STATE of SPI Controller"]
 pub mod state;
-#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`]
-module"]
+#[doc = "PERID (r) register accessor: Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@perid`] module"]
 #[doc(alias = "PERID")]
 pub type Perid = crate::Reg<perid::PeridSpec>;
 #[doc = "Peripheral ID Register"]
--- a/va108xx/src/spia/clkprescale.rs
+++ b/va108xx/src/spia/clkprescale.rs
@@ -19,10 +19,6 @@ impl crate::Readable for ClkprescaleSpec {}
 #[doc = "`write(|w| ..)` method takes [`clkprescale::W`](W) writer structure"]
 impl crate::Writable for ClkprescaleSpec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CLKPRESCALE to value 0"]
-impl crate::Resettable for ClkprescaleSpec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for ClkprescaleSpec {}
--- a/va108xx/src/spia/ctrl0.rs
+++ b/va108xx/src/spia/ctrl0.rs
@@ -43,22 +43,22 @@ impl R {
 impl W {
    #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
    #[inline(always)]
-    pub fn size(&mut self) -> SizeW<Ctrl0Spec> {
+    pub fn size(&mut self) -> SizeW<'_, Ctrl0Spec> {
        SizeW::new(self, 0)
    }
    #[doc = "Bit 6 - SPI Clock Polarity"]
    #[inline(always)]
-    pub fn spo(&mut self) -> SpoW<Ctrl0Spec> {
+    pub fn spo(&mut self) -> SpoW<'_, Ctrl0Spec> {
        SpoW::new(self, 6)
    }
    #[doc = "Bit 7 - SPI Clock Phase"]
    #[inline(always)]
-    pub fn sph(&mut self) -> SphW<Ctrl0Spec> {
+    pub fn sph(&mut self) -> SphW<'_, Ctrl0Spec> {
        SphW::new(self, 7)
    }
    #[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
    #[inline(always)]
-    pub fn scrdv(&mut self) -> ScrdvW<Ctrl0Spec> {
+    pub fn scrdv(&mut self) -> ScrdvW<'_, Ctrl0Spec> {
        ScrdvW::new(self, 8)
    }
 }
@@ -72,10 +72,6 @@ impl crate::Readable for Ctrl0Spec {}
 #[doc = "`write(|w| ..)` method takes [`ctrl0::W`](W) writer structure"]
 impl crate::Writable for Ctrl0Spec {
    type Safety = crate::Unsafe;
-    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
-    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
 }
 #[doc = "`reset()` method sets CTRL0 to value 0"]
-impl crate::Resettable for Ctrl0Spec {
-    const RESET_VALUE: u32 = 0;
-}
+impl crate::Resettable for Ctrl0Spec {}
--- a/Show More
+++ b/Show More
Author	SHA1	Message	Date
Robin Mueller	2f94f5085b	fix simple example	2025-10-27 22:18:57 +01:00
Robin Müller	4d085756e6	Merge pull request 'prepare va108xx-embassy and vorago-reb1 release' (#80 ) from prepare-embassy-bsp-release into main Reviewed-on: #80	2025-09-03 11:33:56 +02:00
Robin Mueller	a16dc412e0	prepare va108xx-embassy and vorago-reb1 release	2025-09-03 11:30:18 +02:00
Robin Müller	8c8e01775d	Merge pull request 'bump HAL and PAC' (#79 ) from bump-hal-pac into main Reviewed-on: #79	2025-09-03 11:24:17 +02:00
Robin Mueller	c5a43356cc	bump HAL and PAC	2025-09-03 11:22:35 +02:00
Robin Mueller	07d8bc7952	README fix	2025-09-03 10:01:26 +02:00
Robin Mueller	02642dc5bb	better config template naming	2025-09-03 09:56:27 +02:00
Robin Müller	3856a9184c	Merge pull request 'update some dependencies' (#78 ) from update-some-dependencies into main Reviewed-on: #78	2025-09-03 09:54:50 +02:00
Robin Mueller	e12fc9c319	update some dependencies	2025-09-03 09:53:28 +02:00
Robin Müller	c2be8b2e44	Merge pull request 'update PAC using svd2rust v0.37' (#77 ) from update-pac into main Reviewed-on: #77	2025-09-03 09:46:19 +02:00
Robin Mueller	e5b2ee0bc8	update PAC using svd2rust v0.37	2025-09-03 09:45:28 +02:00
Robin Müller	7b144b9022	Merge pull request 'patch release va108xx' (#76 ) from prep-va108xx-release into main Reviewed-on: #76	2025-07-22 12:09:12 +02:00
Robin Mueller	a248947441	patch release va108xx	2025-07-22 12:08:37 +02:00
Robin Müller	6017a52d2c	Merge pull request 'update dependencies' (#75 ) from update-dependencies into main Reviewed-on: #75	2025-07-22 12:05:37 +02:00
Robin Mueller	ec80f55b78	update dependencies	2025-07-22 11:23:15 +02:00
Robin Müller	41a59eabeb	Merge pull request 'updated flashloader test applications' (#74 ) from update-flashloader-testapps into main Reviewed-on: #74	2025-05-12 14:49:49 +02:00
Robin Müller	0774ea85e3	Merge branch 'main' into update-flashloader-testapps	2025-05-12 14:49:45 +02:00
Robin Mueller	4114878e98	updated flashloader test applications	2025-05-12 14:44:45 +02:00
Robin Mueller	3d240d5481	README tweak	2025-04-24 22:46:32 +02:00
Robin Mueller	6583064454	small note on shared periph crate	2025-04-24 22:45:15 +02:00
Robin Müller	f2e39993ed	Merge pull request 'Rework of library structure' (#73 ) from rework-typestate-introduce-shared-peripherals into main Reviewed-on: #73	2025-04-24 22:41:13 +02:00
Robin Mueller	58934e293f	Rework library structure Changed: - Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs) which is mostly re-exported in this crate. - All HAL API constructors now have a more consistent argument order: PAC structures and resource management structures first, then clock configuration, then any other configuration. - Overhaul and simplification of several HAL APIs. The system configuration and IRQ router peripheral instance generally does not need to be passed to HAL API anymore. - All HAL drivers are now type erased. The constructors will still expect and consume the PAC singleton component for resource management purposes, but are not cached anymore. - Refactoring of GPIO library to be more inline with embassy GPIO API. Added: - I2C clock timeout feature support.	2025-04-24 22:33:46 +02:00