First building PAC version
Generated a first building version of the PAC. The PAC was generated with a specially patched version of svd2rust 0.19.0: https://github.com/robamu/svd2rust/tree/mueller/develop
This commit is contained in:
parent
45d12c83bb
commit
e97cd64ba6
18
Cargo.toml
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18
Cargo.toml
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@ -0,0 +1,18 @@
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[package]
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name = "va108xx"
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version = "0.1.0"
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edition = "2018"
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description = "Peripheral access API for Vorago VA108XX microcontrollers"
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license = "Apache-2.0 or MIT"
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authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
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[dependencies]
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cortex-m = "0.7.3"
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vcell = "0.1.3"
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[dependencies.cortex-m-rt]
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optional = true
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version = ">=0.6.15,<0.8"
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[features]
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rt = ["cortex-m-rt/device"]
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17
build.rs
17
build.rs
@ -1 +1,16 @@
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use std :: env ; use std :: fs :: File ; use std :: io :: Write ; use std :: path :: PathBuf ; fn main () { if env :: var_os ("CARGO_FEATURE_RT") . is_some () { let out = & PathBuf :: from (env :: var_os ("OUT_DIR") . unwrap ()) ; File :: create (out . join ("device.x")) . unwrap () . write_all (include_bytes ! ("device.x")) . unwrap () ; println ! ("cargo:rustc-link-search={}" , out . display ()) ; println ! ("cargo:rerun-if-changed=device.x") ; } println ! ("cargo:rerun-if-changed=build.rs") ; }
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use std::env;
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use std::fs::File;
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use std::io::Write;
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use std::path::PathBuf;
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fn main() {
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if env::var_os("CARGO_FEATURE_RT").is_some() {
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let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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File::create(out.join("device.x"))
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.unwrap()
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.write_all(include_bytes!("device.x"))
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.unwrap();
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println!("cargo:rustc-link-search={}", out.display());
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println!("cargo:rerun-if-changed=device.x");
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}
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println!("cargo:rerun-if-changed=build.rs");
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}
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260
src/generic.rs
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260
src/generic.rs
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@ -0,0 +1,260 @@
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use core::marker;
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#[doc = " Raw register type"]
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pub trait RegisterSpec {
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#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
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type Ux: Copy;
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}
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#[doc = " Trait implemented by readable registers to enable the `read` method."]
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#[doc = ""]
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#[doc = " Registers marked with `Writable` can be also `modify`'ed."]
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pub trait Readable: RegisterSpec {
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#[doc = " Result from a call to `read` and argument to `modify`."]
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type Reader: From<R<Self>> + core::ops::Deref<Target = R<Self>>;
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}
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#[doc = " Trait implemented by writeable registers."]
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#[doc = ""]
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#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
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#[doc = ""]
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#[doc = " Registers marked with `Readable` can be also `modify`'ed."]
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pub trait Writable: RegisterSpec {
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#[doc = " Writer type argument to `write`, et al."]
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type Writer: From<W<Self>> + core::ops::DerefMut<Target = W<Self>>;
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}
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#[doc = " Reset value of the register."]
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#[doc = ""]
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#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
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#[doc = " register by using the `reset` method."]
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pub trait Resettable: RegisterSpec {
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#[doc = " Reset value of the register."]
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fn reset_value() -> Self::Ux;
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}
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#[doc = " This structure provides volatile access to registers."]
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#[repr(transparent)]
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pub struct Reg<REG: RegisterSpec> {
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register: vcell::VolatileCell<REG::Ux>,
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_marker: marker::PhantomData<REG>,
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}
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unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
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impl<REG: RegisterSpec> Reg<REG> {
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#[doc = " Returns the underlying memory address of register."]
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#[doc = ""]
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#[doc = " ```ignore"]
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#[doc = " let reg_ptr = periph.reg.as_ptr();"]
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#[doc = " ```"]
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#[inline(always)]
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pub fn as_ptr(&self) -> *mut REG::Ux {
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self.register.as_ptr()
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}
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}
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impl<REG: Readable> Reg<REG> {
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#[doc = " Reads the contents of a `Readable` register."]
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#[doc = ""]
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#[doc = " You can read the raw contents of a register by using `bits`:"]
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#[doc = " ```ignore"]
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#[doc = " let bits = periph.reg.read().bits();"]
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#[doc = " ```"]
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#[doc = " or get the content of a particular field of a register:"]
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#[doc = " ```ignore"]
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#[doc = " let reader = periph.reg.read();"]
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#[doc = " let bits = reader.field1().bits();"]
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#[doc = " let flag = reader.field2().bit_is_set();"]
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#[doc = " ```"]
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#[inline(always)]
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pub fn read(&self) -> REG::Reader {
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REG::Reader::from(R {
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bits: self.register.get(),
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_reg: marker::PhantomData,
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})
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}
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}
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impl<REG: Resettable + Writable> Reg<REG> {
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#[doc = " Writes the reset value to `Writable` register."]
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#[doc = ""]
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#[doc = " Resets the register to its initial state."]
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#[inline(always)]
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pub fn reset(&self) {
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self.register.set(REG::reset_value())
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}
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#[doc = " Writes bits to a `Writable` register."]
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#[doc = ""]
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#[doc = " You can write raw bits into a register:"]
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#[doc = " ```ignore"]
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#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
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#[doc = " ```"]
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#[doc = " or write only the fields you need:"]
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#[doc = " ```ignore"]
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#[doc = " periph.reg.write(|w| w"]
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#[doc = " .field1().bits(newfield1bits)"]
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#[doc = " .field2().set_bit()"]
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#[doc = " .field3().variant(VARIANT)"]
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#[doc = " );"]
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#[doc = " ```"]
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#[doc = " In the latter case, other fields will be set to their reset value."]
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#[inline(always)]
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pub fn write<F>(&self, f: F)
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where
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F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
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{
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self.register.set(
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f(&mut REG::Writer::from(W {
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bits: REG::reset_value(),
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_reg: marker::PhantomData,
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}))
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.bits,
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);
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}
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}
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impl<REG: Writable> Reg<REG>
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where
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REG::Ux: Default,
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{
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#[doc = " Writes 0 to a `Writable` register."]
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#[doc = ""]
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#[doc = " Similar to `write`, but unused bits will contain 0."]
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#[inline(always)]
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pub unsafe fn write_with_zero<F>(&self, f: F)
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where
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F: FnOnce(&mut REG::Writer) -> &mut W<REG>,
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{
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self.register.set(
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(*f(&mut REG::Writer::from(W {
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bits: REG::Ux::default(),
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_reg: marker::PhantomData,
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})))
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.bits,
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);
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}
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}
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impl<REG: Readable + Writable> Reg<REG> {
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#[doc = " Modifies the contents of the register by reading and then writing it."]
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#[doc = ""]
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#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
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#[doc = " ```ignore"]
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#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
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#[doc = " r.bits() | 3"]
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#[doc = " ) });"]
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#[doc = " ```"]
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#[doc = " or"]
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#[doc = " ```ignore"]
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#[doc = " periph.reg.modify(|_, w| w"]
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#[doc = " .field1().bits(newfield1bits)"]
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#[doc = " .field2().set_bit()"]
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#[doc = " .field3().variant(VARIANT)"]
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#[doc = " );"]
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#[doc = " ```"]
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#[doc = " Other fields will have the value they had before the call to `modify`."]
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#[inline(always)]
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pub fn modify<F>(&self, f: F)
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where
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for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W<REG>,
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{
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let bits = self.register.get();
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self.register.set(
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f(
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®::Reader::from(R {
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bits,
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_reg: marker::PhantomData,
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}),
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&mut REG::Writer::from(W {
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bits,
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_reg: marker::PhantomData,
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}),
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)
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.bits,
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);
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}
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}
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#[doc = " Register reader."]
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#[doc = ""]
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#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
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#[doc = " method."]
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pub struct R<REG: RegisterSpec + ?Sized> {
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pub(crate) bits: REG::Ux,
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_reg: marker::PhantomData<REG>,
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}
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impl<REG: RegisterSpec> R<REG> {
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#[doc = " Reads raw bits from register."]
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#[inline(always)]
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pub fn bits(&self) -> REG::Ux {
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self.bits
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}
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}
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impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
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where
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REG::Ux: PartialEq,
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FI: Copy + Into<REG::Ux>,
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{
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#[inline(always)]
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fn eq(&self, other: &FI) -> bool {
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self.bits.eq(&(*other).into())
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}
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}
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#[doc = " Register writer."]
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#[doc = ""]
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#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
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pub struct W<REG: RegisterSpec + ?Sized> {
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#[doc = "Writable bits"]
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pub(crate) bits: REG::Ux,
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_reg: marker::PhantomData<REG>,
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}
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impl<REG: RegisterSpec> W<REG> {
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#[doc = " Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
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self.bits = bits;
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self
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}
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}
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#[doc = " Field reader."]
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#[doc = ""]
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#[doc = " Result of the `read` methods of fields."]
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pub struct FieldReader<U, T> {
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pub(crate) bits: U,
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_reg: marker::PhantomData<T>,
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}
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impl<U, T> FieldReader<U, T>
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where
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U: Copy,
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{
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#[doc = " Creates a new instance of the reader."]
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#[allow(unused)]
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#[inline(always)]
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pub(crate) fn new(bits: U) -> Self {
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Self {
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bits,
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_reg: marker::PhantomData,
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}
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}
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#[doc = " Reads raw bits from field."]
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#[inline(always)]
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pub fn bits(&self) -> U {
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self.bits
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}
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}
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impl<U, T, FI> PartialEq<FI> for FieldReader<U, T>
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where
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U: PartialEq,
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FI: Copy + Into<U>,
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{
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#[inline(always)]
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fn eq(&self, other: &FI) -> bool {
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self.bits.eq(&(*other).into())
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}
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}
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impl<FI> FieldReader<bool, FI> {
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#[doc = " Value of the field as raw bits."]
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#[inline(always)]
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pub fn bit(&self) -> bool {
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self.bits
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}
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#[doc = " Returns `true` if the bit is clear (0)."]
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#[inline(always)]
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pub fn bit_is_clear(&self) -> bool {
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!self.bit()
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}
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#[doc = " Returns `true` if the bit is set (1)."]
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#[inline(always)]
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pub fn bit_is_set(&self) -> bool {
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self.bit()
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}
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}
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240
src/i2ca.rs
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240
src/i2ca.rs
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#[doc = r"Register block"]
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#[repr(C)]
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pub struct RegisterBlock {
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#[doc = "0x00 - Control Register"]
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pub ctrl: crate::Reg<ctrl::CTRL_SPEC>,
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#[doc = "0x04 - Clock Scale divide value"]
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pub clkscale: crate::Reg<clkscale::CLKSCALE_SPEC>,
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#[doc = "0x08 - Word Count value"]
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pub words: crate::Reg<words::WORDS_SPEC>,
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#[doc = "0x0c - I2C Address value"]
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pub address: crate::Reg<address::ADDRESS_SPEC>,
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#[doc = "0x10 - Data Input/Output"]
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pub data: crate::Reg<data::DATA_SPEC>,
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#[doc = "0x14 - Command Register"]
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pub cmd: crate::Reg<cmd::CMD_SPEC>,
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#[doc = "0x18 - I2C Controller Status Register"]
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pub status: crate::Reg<status::STATUS_SPEC>,
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#[doc = "0x1c - Internal STATE of I2C Master Controller"]
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pub state: crate::Reg<state::STATE_SPEC>,
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#[doc = "0x20 - TX Count Register"]
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pub txcount: crate::Reg<txcount::TXCOUNT_SPEC>,
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#[doc = "0x24 - RX Count Register"]
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pub rxcount: crate::Reg<rxcount::RXCOUNT_SPEC>,
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#[doc = "0x28 - Interrupt Enable Register"]
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pub irq_enb: crate::Reg<irq_enb::IRQ_ENB_SPEC>,
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#[doc = "0x2c - Raw Interrupt Status Register"]
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pub irq_raw: crate::Reg<irq_raw::IRQ_RAW_SPEC>,
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#[doc = "0x30 - Enabled Interrupt Status Register"]
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pub irq_end: crate::Reg<irq_end::IRQ_END_SPEC>,
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#[doc = "0x34 - Clear Interrupt Status Register"]
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pub irq_clr: crate::Reg<irq_clr::IRQ_CLR_SPEC>,
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#[doc = "0x38 - Rx FIFO IRQ Trigger Level"]
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pub rxfifoirqtrg: crate::Reg<rxfifoirqtrg::RXFIFOIRQTRG_SPEC>,
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#[doc = "0x3c - Tx FIFO IRQ Trigger Level"]
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pub txfifoirqtrg: crate::Reg<txfifoirqtrg::TXFIFOIRQTRG_SPEC>,
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#[doc = "0x40 - Clear FIFO Register"]
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pub fifo_clr: crate::Reg<fifo_clr::FIFO_CLR_SPEC>,
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#[doc = "0x44 - Timing Config Register"]
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pub tmconfig: crate::Reg<tmconfig::TMCONFIG_SPEC>,
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#[doc = "0x48 - Clock Low Timeout Limit Register"]
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pub clktolimit: crate::Reg<clktolimit::CLKTOLIMIT_SPEC>,
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_reserved19: [u8; 0xb4],
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#[doc = "0x100 - Slave Control Register"]
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pub s0_ctrl: crate::Reg<s0_ctrl::S0_CTRL_SPEC>,
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#[doc = "0x104 - Slave MaxWords Register"]
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pub s0_maxwords: crate::Reg<s0_maxwords::S0_MAXWORDS_SPEC>,
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#[doc = "0x108 - Slave I2C Address Value"]
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pub s0_address: crate::Reg<s0_address::S0_ADDRESS_SPEC>,
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#[doc = "0x10c - Slave I2C Address Mask value"]
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pub s0_addressmask: crate::Reg<s0_addressmask::S0_ADDRESSMASK_SPEC>,
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#[doc = "0x110 - Slave Data Input/Output"]
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pub s0_data: crate::Reg<s0_data::S0_DATA_SPEC>,
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#[doc = "0x114 - Slave I2C Last Address value"]
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pub s0_lastaddress: crate::Reg<s0_lastaddress::S0_LASTADDRESS_SPEC>,
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#[doc = "0x118 - Slave I2C Controller Status Register"]
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pub s0_status: crate::Reg<s0_status::S0_STATUS_SPEC>,
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#[doc = "0x11c - Internal STATE of I2C Slave Controller"]
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pub s0_state: crate::Reg<s0_state::S0_STATE_SPEC>,
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#[doc = "0x120 - Slave TX Count Register"]
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pub s0_txcount: crate::Reg<s0_txcount::S0_TXCOUNT_SPEC>,
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#[doc = "0x124 - Slave RX Count Register"]
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pub s0_rxcount: crate::Reg<s0_rxcount::S0_RXCOUNT_SPEC>,
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#[doc = "0x128 - Slave Interrupt Enable Register"]
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pub s0_irq_enb: crate::Reg<s0_irq_enb::S0_IRQ_ENB_SPEC>,
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#[doc = "0x12c - Slave Raw Interrupt Status Register"]
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pub s0_irq_raw: crate::Reg<s0_irq_raw::S0_IRQ_RAW_SPEC>,
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#[doc = "0x130 - Slave Enabled Interrupt Status Register"]
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pub s0_irq_end: crate::Reg<s0_irq_end::S0_IRQ_END_SPEC>,
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#[doc = "0x134 - Slave Clear Interrupt Status Register"]
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pub s0_irq_clr: crate::Reg<s0_irq_clr::S0_IRQ_CLR_SPEC>,
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#[doc = "0x138 - Slave Rx FIFO IRQ Trigger Level"]
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pub s0_rxfifoirqtrg: crate::Reg<s0_rxfifoirqtrg::S0_RXFIFOIRQTRG_SPEC>,
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#[doc = "0x13c - Slave Tx FIFO IRQ Trigger Level"]
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pub s0_txfifoirqtrg: crate::Reg<s0_txfifoirqtrg::S0_TXFIFOIRQTRG_SPEC>,
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#[doc = "0x140 - Slave Clear FIFO Register"]
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pub s0_fifo_clr: crate::Reg<s0_fifo_clr::S0_FIFO_CLR_SPEC>,
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#[doc = "0x144 - Slave I2C Address B Value"]
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pub s0_addressb: crate::Reg<s0_addressb::S0_ADDRESSB_SPEC>,
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#[doc = "0x148 - Slave I2C Address B Mask value"]
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pub s0_addressmaskb: crate::Reg<s0_addressmaskb::S0_ADDRESSMASKB_SPEC>,
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_reserved38: [u8; 0x0eb0],
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#[doc = "0xffc - Peripheral ID Register"]
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pub perid: crate::Reg<perid::PERID_SPEC>,
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}
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#[doc = "CTRL register accessor: an alias for `Reg<CTRL_SPEC>`"]
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pub type CTRL = crate::Reg<ctrl::CTRL_SPEC>;
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#[doc = "Control Register"]
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pub mod ctrl;
|
||||
#[doc = "CLKSCALE register accessor: an alias for `Reg<CLKSCALE_SPEC>`"]
|
||||
pub type CLKSCALE = crate::Reg<clkscale::CLKSCALE_SPEC>;
|
||||
#[doc = "Clock Scale divide value"]
|
||||
pub mod clkscale;
|
||||
#[doc = "WORDS register accessor: an alias for `Reg<WORDS_SPEC>`"]
|
||||
pub type WORDS = crate::Reg<words::WORDS_SPEC>;
|
||||
#[doc = "Word Count value"]
|
||||
pub mod words;
|
||||
#[doc = "ADDRESS register accessor: an alias for `Reg<ADDRESS_SPEC>`"]
|
||||
pub type ADDRESS = crate::Reg<address::ADDRESS_SPEC>;
|
||||
#[doc = "I2C Address value"]
|
||||
pub mod address;
|
||||
#[doc = "DATA register accessor: an alias for `Reg<DATA_SPEC>`"]
|
||||
pub type DATA = crate::Reg<data::DATA_SPEC>;
|
||||
#[doc = "Data Input/Output"]
|
||||
pub mod data;
|
||||
#[doc = "CMD register accessor: an alias for `Reg<CMD_SPEC>`"]
|
||||
pub type CMD = crate::Reg<cmd::CMD_SPEC>;
|
||||
#[doc = "Command Register"]
|
||||
pub mod cmd;
|
||||
#[doc = "STATUS register accessor: an alias for `Reg<STATUS_SPEC>`"]
|
||||
pub type STATUS = crate::Reg<status::STATUS_SPEC>;
|
||||
#[doc = "I2C Controller Status Register"]
|
||||
pub mod status;
|
||||
#[doc = "STATE register accessor: an alias for `Reg<STATE_SPEC>`"]
|
||||
pub type STATE = crate::Reg<state::STATE_SPEC>;
|
||||
#[doc = "Internal STATE of I2C Master Controller"]
|
||||
pub mod state;
|
||||
#[doc = "TXCOUNT register accessor: an alias for `Reg<TXCOUNT_SPEC>`"]
|
||||
pub type TXCOUNT = crate::Reg<txcount::TXCOUNT_SPEC>;
|
||||
#[doc = "TX Count Register"]
|
||||
pub mod txcount;
|
||||
#[doc = "RXCOUNT register accessor: an alias for `Reg<RXCOUNT_SPEC>`"]
|
||||
pub type RXCOUNT = crate::Reg<rxcount::RXCOUNT_SPEC>;
|
||||
#[doc = "RX Count Register"]
|
||||
pub mod rxcount;
|
||||
#[doc = "IRQ_ENB register accessor: an alias for `Reg<IRQ_ENB_SPEC>`"]
|
||||
pub type IRQ_ENB = crate::Reg<irq_enb::IRQ_ENB_SPEC>;
|
||||
#[doc = "Interrupt Enable Register"]
|
||||
pub mod irq_enb;
|
||||
#[doc = "IRQ_RAW register accessor: an alias for `Reg<IRQ_RAW_SPEC>`"]
|
||||
pub type IRQ_RAW = crate::Reg<irq_raw::IRQ_RAW_SPEC>;
|
||||
#[doc = "Raw Interrupt Status Register"]
|
||||
pub mod irq_raw;
|
||||
#[doc = "IRQ_END register accessor: an alias for `Reg<IRQ_END_SPEC>`"]
|
||||
pub type IRQ_END = crate::Reg<irq_end::IRQ_END_SPEC>;
|
||||
#[doc = "Enabled Interrupt Status Register"]
|
||||
pub mod irq_end;
|
||||
#[doc = "IRQ_CLR register accessor: an alias for `Reg<IRQ_CLR_SPEC>`"]
|
||||
pub type IRQ_CLR = crate::Reg<irq_clr::IRQ_CLR_SPEC>;
|
||||
#[doc = "Clear Interrupt Status Register"]
|
||||
pub mod irq_clr;
|
||||
#[doc = "RXFIFOIRQTRG register accessor: an alias for `Reg<RXFIFOIRQTRG_SPEC>`"]
|
||||
pub type RXFIFOIRQTRG = crate::Reg<rxfifoirqtrg::RXFIFOIRQTRG_SPEC>;
|
||||
#[doc = "Rx FIFO IRQ Trigger Level"]
|
||||
pub mod rxfifoirqtrg;
|
||||
#[doc = "TXFIFOIRQTRG register accessor: an alias for `Reg<TXFIFOIRQTRG_SPEC>`"]
|
||||
pub type TXFIFOIRQTRG = crate::Reg<txfifoirqtrg::TXFIFOIRQTRG_SPEC>;
|
||||
#[doc = "Tx FIFO IRQ Trigger Level"]
|
||||
pub mod txfifoirqtrg;
|
||||
#[doc = "FIFO_CLR register accessor: an alias for `Reg<FIFO_CLR_SPEC>`"]
|
||||
pub type FIFO_CLR = crate::Reg<fifo_clr::FIFO_CLR_SPEC>;
|
||||
#[doc = "Clear FIFO Register"]
|
||||
pub mod fifo_clr;
|
||||
#[doc = "TMCONFIG register accessor: an alias for `Reg<TMCONFIG_SPEC>`"]
|
||||
pub type TMCONFIG = crate::Reg<tmconfig::TMCONFIG_SPEC>;
|
||||
#[doc = "Timing Config Register"]
|
||||
pub mod tmconfig;
|
||||
#[doc = "CLKTOLIMIT register accessor: an alias for `Reg<CLKTOLIMIT_SPEC>`"]
|
||||
pub type CLKTOLIMIT = crate::Reg<clktolimit::CLKTOLIMIT_SPEC>;
|
||||
#[doc = "Clock Low Timeout Limit Register"]
|
||||
pub mod clktolimit;
|
||||
#[doc = "S0_CTRL register accessor: an alias for `Reg<S0_CTRL_SPEC>`"]
|
||||
pub type S0_CTRL = crate::Reg<s0_ctrl::S0_CTRL_SPEC>;
|
||||
#[doc = "Slave Control Register"]
|
||||
pub mod s0_ctrl;
|
||||
#[doc = "S0_MAXWORDS register accessor: an alias for `Reg<S0_MAXWORDS_SPEC>`"]
|
||||
pub type S0_MAXWORDS = crate::Reg<s0_maxwords::S0_MAXWORDS_SPEC>;
|
||||
#[doc = "Slave MaxWords Register"]
|
||||
pub mod s0_maxwords;
|
||||
#[doc = "S0_ADDRESS register accessor: an alias for `Reg<S0_ADDRESS_SPEC>`"]
|
||||
pub type S0_ADDRESS = crate::Reg<s0_address::S0_ADDRESS_SPEC>;
|
||||
#[doc = "Slave I2C Address Value"]
|
||||
pub mod s0_address;
|
||||
#[doc = "S0_ADDRESSMASK register accessor: an alias for `Reg<S0_ADDRESSMASK_SPEC>`"]
|
||||
pub type S0_ADDRESSMASK = crate::Reg<s0_addressmask::S0_ADDRESSMASK_SPEC>;
|
||||
#[doc = "Slave I2C Address Mask value"]
|
||||
pub mod s0_addressmask;
|
||||
#[doc = "S0_DATA register accessor: an alias for `Reg<S0_DATA_SPEC>`"]
|
||||
pub type S0_DATA = crate::Reg<s0_data::S0_DATA_SPEC>;
|
||||
#[doc = "Slave Data Input/Output"]
|
||||
pub mod s0_data;
|
||||
#[doc = "S0_LASTADDRESS register accessor: an alias for `Reg<S0_LASTADDRESS_SPEC>`"]
|
||||
pub type S0_LASTADDRESS = crate::Reg<s0_lastaddress::S0_LASTADDRESS_SPEC>;
|
||||
#[doc = "Slave I2C Last Address value"]
|
||||
pub mod s0_lastaddress;
|
||||
#[doc = "S0_STATUS register accessor: an alias for `Reg<S0_STATUS_SPEC>`"]
|
||||
pub type S0_STATUS = crate::Reg<s0_status::S0_STATUS_SPEC>;
|
||||
#[doc = "Slave I2C Controller Status Register"]
|
||||
pub mod s0_status;
|
||||
#[doc = "S0_STATE register accessor: an alias for `Reg<S0_STATE_SPEC>`"]
|
||||
pub type S0_STATE = crate::Reg<s0_state::S0_STATE_SPEC>;
|
||||
#[doc = "Internal STATE of I2C Slave Controller"]
|
||||
pub mod s0_state;
|
||||
#[doc = "S0_TXCOUNT register accessor: an alias for `Reg<S0_TXCOUNT_SPEC>`"]
|
||||
pub type S0_TXCOUNT = crate::Reg<s0_txcount::S0_TXCOUNT_SPEC>;
|
||||
#[doc = "Slave TX Count Register"]
|
||||
pub mod s0_txcount;
|
||||
#[doc = "S0_RXCOUNT register accessor: an alias for `Reg<S0_RXCOUNT_SPEC>`"]
|
||||
pub type S0_RXCOUNT = crate::Reg<s0_rxcount::S0_RXCOUNT_SPEC>;
|
||||
#[doc = "Slave RX Count Register"]
|
||||
pub mod s0_rxcount;
|
||||
#[doc = "S0_IRQ_ENB register accessor: an alias for `Reg<S0_IRQ_ENB_SPEC>`"]
|
||||
pub type S0_IRQ_ENB = crate::Reg<s0_irq_enb::S0_IRQ_ENB_SPEC>;
|
||||
#[doc = "Slave Interrupt Enable Register"]
|
||||
pub mod s0_irq_enb;
|
||||
#[doc = "S0_IRQ_RAW register accessor: an alias for `Reg<S0_IRQ_RAW_SPEC>`"]
|
||||
pub type S0_IRQ_RAW = crate::Reg<s0_irq_raw::S0_IRQ_RAW_SPEC>;
|
||||
#[doc = "Slave Raw Interrupt Status Register"]
|
||||
pub mod s0_irq_raw;
|
||||
#[doc = "S0_IRQ_END register accessor: an alias for `Reg<S0_IRQ_END_SPEC>`"]
|
||||
pub type S0_IRQ_END = crate::Reg<s0_irq_end::S0_IRQ_END_SPEC>;
|
||||
#[doc = "Slave Enabled Interrupt Status Register"]
|
||||
pub mod s0_irq_end;
|
||||
#[doc = "S0_IRQ_CLR register accessor: an alias for `Reg<S0_IRQ_CLR_SPEC>`"]
|
||||
pub type S0_IRQ_CLR = crate::Reg<s0_irq_clr::S0_IRQ_CLR_SPEC>;
|
||||
#[doc = "Slave Clear Interrupt Status Register"]
|
||||
pub mod s0_irq_clr;
|
||||
#[doc = "S0_RXFIFOIRQTRG register accessor: an alias for `Reg<S0_RXFIFOIRQTRG_SPEC>`"]
|
||||
pub type S0_RXFIFOIRQTRG = crate::Reg<s0_rxfifoirqtrg::S0_RXFIFOIRQTRG_SPEC>;
|
||||
#[doc = "Slave Rx FIFO IRQ Trigger Level"]
|
||||
pub mod s0_rxfifoirqtrg;
|
||||
#[doc = "S0_TXFIFOIRQTRG register accessor: an alias for `Reg<S0_TXFIFOIRQTRG_SPEC>`"]
|
||||
pub type S0_TXFIFOIRQTRG = crate::Reg<s0_txfifoirqtrg::S0_TXFIFOIRQTRG_SPEC>;
|
||||
#[doc = "Slave Tx FIFO IRQ Trigger Level"]
|
||||
pub mod s0_txfifoirqtrg;
|
||||
#[doc = "S0_FIFO_CLR register accessor: an alias for `Reg<S0_FIFO_CLR_SPEC>`"]
|
||||
pub type S0_FIFO_CLR = crate::Reg<s0_fifo_clr::S0_FIFO_CLR_SPEC>;
|
||||
#[doc = "Slave Clear FIFO Register"]
|
||||
pub mod s0_fifo_clr;
|
||||
#[doc = "S0_ADDRESSB register accessor: an alias for `Reg<S0_ADDRESSB_SPEC>`"]
|
||||
pub type S0_ADDRESSB = crate::Reg<s0_addressb::S0_ADDRESSB_SPEC>;
|
||||
#[doc = "Slave I2C Address B Value"]
|
||||
pub mod s0_addressb;
|
||||
#[doc = "S0_ADDRESSMASKB register accessor: an alias for `Reg<S0_ADDRESSMASKB_SPEC>`"]
|
||||
pub type S0_ADDRESSMASKB = crate::Reg<s0_addressmaskb::S0_ADDRESSMASKB_SPEC>;
|
||||
#[doc = "Slave I2C Address B Mask value"]
|
||||
pub mod s0_addressmaskb;
|
||||
#[doc = "PERID register accessor: an alias for `Reg<PERID_SPEC>`"]
|
||||
pub type PERID = crate::Reg<perid::PERID_SPEC>;
|
||||
#[doc = "Peripheral ID Register"]
|
||||
pub mod perid;
|
||||
64
src/i2ca/address.rs
Normal file
64
src/i2ca/address.rs
Normal file
@ -0,0 +1,64 @@
|
||||
#[doc = "Register `ADDRESS` reader"]
|
||||
pub struct R(crate::R<ADDRESS_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<ADDRESS_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<ADDRESS_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<ADDRESS_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `ADDRESS` writer"]
|
||||
pub struct W(crate::W<ADDRESS_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<ADDRESS_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<ADDRESS_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<ADDRESS_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "I2C Address value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [address](index.html) module"]
|
||||
pub struct ADDRESS_SPEC;
|
||||
impl crate::RegisterSpec for ADDRESS_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [address::R](R) reader structure"]
|
||||
impl crate::Readable for ADDRESS_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [address::W](W) writer structure"]
|
||||
impl crate::Writable for ADDRESS_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets ADDRESS to value 0"]
|
||||
impl crate::Resettable for ADDRESS_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
150
src/i2ca/clkscale.rs
Normal file
150
src/i2ca/clkscale.rs
Normal file
@ -0,0 +1,150 @@
|
||||
#[doc = "Register `CLKSCALE` reader"]
|
||||
pub struct R(crate::R<CLKSCALE_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<CLKSCALE_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<CLKSCALE_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<CLKSCALE_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `CLKSCALE` writer"]
|
||||
pub struct W(crate::W<CLKSCALE_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<CLKSCALE_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<CLKSCALE_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<CLKSCALE_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `VALUE` reader - Enable FastMode"]
|
||||
pub struct VALUE_R(crate::FieldReader<u32, u32>);
|
||||
impl VALUE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: u32) -> Self {
|
||||
VALUE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for VALUE_R {
|
||||
type Target = crate::FieldReader<u32, u32>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `VALUE` writer - Enable FastMode"]
|
||||
pub struct VALUE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> VALUE_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u32) -> &'a mut W {
|
||||
self.w.bits = value as u32;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `FASTMODE` reader - Enable FastMode"]
|
||||
pub struct FASTMODE_R(crate::FieldReader<bool, bool>);
|
||||
impl FASTMODE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
FASTMODE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for FASTMODE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `FASTMODE` writer - Enable FastMode"]
|
||||
pub struct FASTMODE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> FASTMODE_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bits 0:30 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
pub fn value(&self) -> VALUE_R {
|
||||
VALUE_R::new(self.bits as u32)
|
||||
}
|
||||
#[doc = "Bit 31 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
pub fn fastmode(&self) -> FASTMODE_R {
|
||||
FASTMODE_R::new(((self.bits >> 31) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:30 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
pub fn value(&mut self) -> VALUE_W {
|
||||
VALUE_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 31 - Enable FastMode"]
|
||||
#[inline(always)]
|
||||
pub fn fastmode(&mut self) -> FASTMODE_W {
|
||||
FASTMODE_W { w: self }
|
||||
}
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Clock Scale divide value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkscale](index.html) module"]
|
||||
pub struct CLKSCALE_SPEC;
|
||||
impl crate::RegisterSpec for CLKSCALE_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [clkscale::R](R) reader structure"]
|
||||
impl crate::Readable for CLKSCALE_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [clkscale::W](W) writer structure"]
|
||||
impl crate::Writable for CLKSCALE_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets CLKSCALE to value 0"]
|
||||
impl crate::Resettable for CLKSCALE_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
64
src/i2ca/clktolimit.rs
Normal file
64
src/i2ca/clktolimit.rs
Normal file
@ -0,0 +1,64 @@
|
||||
#[doc = "Register `CLKTOLIMIT` reader"]
|
||||
pub struct R(crate::R<CLKTOLIMIT_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<CLKTOLIMIT_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<CLKTOLIMIT_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<CLKTOLIMIT_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `CLKTOLIMIT` writer"]
|
||||
pub struct W(crate::W<CLKTOLIMIT_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<CLKTOLIMIT_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<CLKTOLIMIT_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<CLKTOLIMIT_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Clock Low Timeout Limit Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clktolimit](index.html) module"]
|
||||
pub struct CLKTOLIMIT_SPEC;
|
||||
impl crate::RegisterSpec for CLKTOLIMIT_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [clktolimit::R](R) reader structure"]
|
||||
impl crate::Readable for CLKTOLIMIT_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [clktolimit::W](W) writer structure"]
|
||||
impl crate::Writable for CLKTOLIMIT_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets CLKTOLIMIT to value 0"]
|
||||
impl crate::Resettable for CLKTOLIMIT_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
64
src/i2ca/cmd.rs
Normal file
64
src/i2ca/cmd.rs
Normal file
@ -0,0 +1,64 @@
|
||||
#[doc = "Register `CMD` reader"]
|
||||
pub struct R(crate::R<CMD_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<CMD_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<CMD_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<CMD_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `CMD` writer"]
|
||||
pub struct W(crate::W<CMD_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<CMD_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<CMD_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<CMD_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Command Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmd](index.html) module"]
|
||||
pub struct CMD_SPEC;
|
||||
impl crate::RegisterSpec for CMD_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [cmd::R](R) reader structure"]
|
||||
impl crate::Readable for CMD_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [cmd::W](W) writer structure"]
|
||||
impl crate::Writable for CMD_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets CMD to value 0"]
|
||||
impl crate::Resettable for CMD_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
489
src/i2ca/ctrl.rs
Normal file
489
src/i2ca/ctrl.rs
Normal file
@ -0,0 +1,489 @@
|
||||
#[doc = "Register `CTRL` reader"]
|
||||
pub struct R(crate::R<CTRL_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<CTRL_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<CTRL_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<CTRL_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `CTRL` writer"]
|
||||
pub struct W(crate::W<CTRL_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<CTRL_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<CTRL_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<CTRL_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `CLKENABLED` reader - I2C CLK Enabled"]
|
||||
pub struct CLKENABLED_R(crate::FieldReader<bool, bool>);
|
||||
impl CLKENABLED_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
CLKENABLED_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for CLKENABLED_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `CLKENABLED` writer - I2C CLK Enabled"]
|
||||
pub struct CLKENABLED_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> CLKENABLED_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = value as u32;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ENABLED` reader - I2C Activated"]
|
||||
pub struct ENABLED_R(crate::FieldReader<bool, bool>);
|
||||
impl ENABLED_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
ENABLED_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for ENABLED_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ENABLED` writer - I2C Activated"]
|
||||
pub struct ENABLED_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ENABLED_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ENABLE` reader - I2C Active"]
|
||||
pub struct ENABLE_R(crate::FieldReader<bool, bool>);
|
||||
impl ENABLE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
ENABLE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for ENABLE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ENABLE` writer - I2C Active"]
|
||||
pub struct ENABLE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ENABLE_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXFEMD` reader - TX FIFIO Empty Mode"]
|
||||
pub struct TXFEMD_R(crate::FieldReader<bool, bool>);
|
||||
impl TXFEMD_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TXFEMD_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TXFEMD_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXFEMD` writer - TX FIFIO Empty Mode"]
|
||||
pub struct TXFEMD_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> TXFEMD_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXFFMD` reader - RX FIFO Full Mode"]
|
||||
pub struct RXFFMD_R(crate::FieldReader<bool, bool>);
|
||||
impl RXFFMD_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RXFFMD_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RXFFMD_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXFFMD` writer - RX FIFO Full Mode"]
|
||||
pub struct RXFFMD_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RXFFMD_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ALGFILTER` reader - Enable Input Analog Glitch Filter"]
|
||||
pub struct ALGFILTER_R(crate::FieldReader<bool, bool>);
|
||||
impl ALGFILTER_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
ALGFILTER_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for ALGFILTER_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ALGFILTER` writer - Enable Input Analog Glitch Filter"]
|
||||
pub struct ALGFILTER_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ALGFILTER_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `DLGFILTER` reader - Enable Input Digital Glitch Filter"]
|
||||
pub struct DLGFILTER_R(crate::FieldReader<bool, bool>);
|
||||
impl DLGFILTER_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
DLGFILTER_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for DLGFILTER_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `DLGFILTER` writer - Enable Input Digital Glitch Filter"]
|
||||
pub struct DLGFILTER_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> DLGFILTER_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `LOOPBACK` reader - Enable LoopBack Mode"]
|
||||
pub struct LOOPBACK_R(crate::FieldReader<bool, bool>);
|
||||
impl LOOPBACK_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
LOOPBACK_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for LOOPBACK_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `LOOPBACK` writer - Enable LoopBack Mode"]
|
||||
pub struct LOOPBACK_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> LOOPBACK_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TMCONFIGENB` reader - Enable Timing Config Register"]
|
||||
pub struct TMCONFIGENB_R(crate::FieldReader<bool, bool>);
|
||||
impl TMCONFIGENB_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TMCONFIGENB_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TMCONFIGENB_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TMCONFIGENB` writer - Enable Timing Config Register"]
|
||||
pub struct TMCONFIGENB_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> TMCONFIGENB_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - I2C CLK Enabled"]
|
||||
#[inline(always)]
|
||||
pub fn clkenabled(&self) -> CLKENABLED_R {
|
||||
CLKENABLED_R::new(self.bits != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - I2C Activated"]
|
||||
#[inline(always)]
|
||||
pub fn enabled(&self) -> ENABLED_R {
|
||||
ENABLED_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - I2C Active"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) -> ENABLE_R {
|
||||
ENABLE_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
|
||||
#[inline(always)]
|
||||
pub fn txfemd(&self) -> TXFEMD_R {
|
||||
TXFEMD_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - RX FIFO Full Mode"]
|
||||
#[inline(always)]
|
||||
pub fn rxffmd(&self) -> RXFFMD_R {
|
||||
RXFFMD_R::new(((self.bits >> 4) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
|
||||
#[inline(always)]
|
||||
pub fn algfilter(&self) -> ALGFILTER_R {
|
||||
ALGFILTER_R::new(((self.bits >> 5) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
|
||||
#[inline(always)]
|
||||
pub fn dlgfilter(&self) -> DLGFILTER_R {
|
||||
DLGFILTER_R::new(((self.bits >> 6) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - Enable LoopBack Mode"]
|
||||
#[inline(always)]
|
||||
pub fn loopback(&self) -> LOOPBACK_R {
|
||||
LOOPBACK_R::new(((self.bits >> 8) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - Enable Timing Config Register"]
|
||||
#[inline(always)]
|
||||
pub fn tmconfigenb(&self) -> TMCONFIGENB_R {
|
||||
TMCONFIGENB_R::new(((self.bits >> 9) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - I2C CLK Enabled"]
|
||||
#[inline(always)]
|
||||
pub fn clkenabled(&mut self) -> CLKENABLED_W {
|
||||
CLKENABLED_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - I2C Activated"]
|
||||
#[inline(always)]
|
||||
pub fn enabled(&mut self) -> ENABLED_W {
|
||||
ENABLED_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - I2C Active"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&mut self) -> ENABLE_W {
|
||||
ENABLE_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 3 - TX FIFIO Empty Mode"]
|
||||
#[inline(always)]
|
||||
pub fn txfemd(&mut self) -> TXFEMD_W {
|
||||
TXFEMD_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 4 - RX FIFO Full Mode"]
|
||||
#[inline(always)]
|
||||
pub fn rxffmd(&mut self) -> RXFFMD_W {
|
||||
RXFFMD_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 5 - Enable Input Analog Glitch Filter"]
|
||||
#[inline(always)]
|
||||
pub fn algfilter(&mut self) -> ALGFILTER_W {
|
||||
ALGFILTER_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 6 - Enable Input Digital Glitch Filter"]
|
||||
#[inline(always)]
|
||||
pub fn dlgfilter(&mut self) -> DLGFILTER_W {
|
||||
DLGFILTER_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 8 - Enable LoopBack Mode"]
|
||||
#[inline(always)]
|
||||
pub fn loopback(&mut self) -> LOOPBACK_W {
|
||||
LOOPBACK_W { w: self }
|
||||
}
|
||||