First building PAC version
Generated a first building version of the PAC. The PAC was generated with a specially patched version of svd2rust 0.19.0: https://github.com/robamu/svd2rust/tree/mueller/develop
This commit is contained in:
64
src/spia/clkprescale.rs
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64
src/spia/clkprescale.rs
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@ -0,0 +1,64 @@
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#[doc = "Register `CLKPRESCALE` reader"]
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pub struct R(crate::R<CLKPRESCALE_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<CLKPRESCALE_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl From<crate::R<CLKPRESCALE_SPEC>> for R {
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#[inline(always)]
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fn from(reader: crate::R<CLKPRESCALE_SPEC>) -> Self {
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R(reader)
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}
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}
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#[doc = "Register `CLKPRESCALE` writer"]
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pub struct W(crate::W<CLKPRESCALE_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<CLKPRESCALE_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<CLKPRESCALE_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<CLKPRESCALE_SPEC>) -> Self {
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W(writer)
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}
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}
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impl W {
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "Clock Pre Scale divide value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clkprescale](index.html) module"]
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pub struct CLKPRESCALE_SPEC;
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impl crate::RegisterSpec for CLKPRESCALE_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [clkprescale::R](R) reader structure"]
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impl crate::Readable for CLKPRESCALE_SPEC {
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type Reader = R;
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}
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#[doc = "`write(|w| ..)` method takes [clkprescale::W](W) writer structure"]
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impl crate::Writable for CLKPRESCALE_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets CLKPRESCALE to value 0"]
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impl crate::Resettable for CLKPRESCALE_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
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}
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234
src/spia/ctrl0.rs
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234
src/spia/ctrl0.rs
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@ -0,0 +1,234 @@
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#[doc = "Register `CTRL0` reader"]
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pub struct R(crate::R<CTRL0_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<CTRL0_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl From<crate::R<CTRL0_SPEC>> for R {
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#[inline(always)]
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fn from(reader: crate::R<CTRL0_SPEC>) -> Self {
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R(reader)
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}
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}
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#[doc = "Register `CTRL0` writer"]
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pub struct W(crate::W<CTRL0_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<CTRL0_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<CTRL0_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<CTRL0_SPEC>) -> Self {
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W(writer)
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}
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}
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#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"]
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pub struct SIZE_R(crate::FieldReader<u8, u8>);
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impl SIZE_R {
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#[inline(always)]
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pub(crate) fn new(bits: u8) -> Self {
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SIZE_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for SIZE_R {
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type Target = crate::FieldReader<u8, u8>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"]
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pub struct SIZE_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SIZE_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = value as u32;
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self.w
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}
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}
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#[doc = "Field `SPO` reader - SPI Clock Polarity"]
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pub struct SPO_R(crate::FieldReader<bool, bool>);
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impl SPO_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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SPO_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for SPO_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `SPO` writer - SPI Clock Polarity"]
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pub struct SPO_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SPO_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
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self.w
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}
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}
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#[doc = "Field `SPH` reader - SPI Clock Phase"]
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pub struct SPH_R(crate::FieldReader<bool, bool>);
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impl SPH_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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SPH_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for SPH_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `SPH` writer - SPI Clock Phase"]
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pub struct SPH_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SPH_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
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self.w
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}
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}
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#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"]
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pub struct SCRDV_R(crate::FieldReader<u8, u8>);
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impl SCRDV_R {
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#[inline(always)]
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pub(crate) fn new(bits: u8) -> Self {
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SCRDV_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for SCRDV_R {
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type Target = crate::FieldReader<u8, u8>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"]
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pub struct SCRDV_W<'a> {
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w: &'a mut W,
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}
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impl<'a> SCRDV_W<'a> {
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub unsafe fn bits(self, value: u8) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
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self.w
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}
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}
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impl R {
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#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
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#[inline(always)]
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pub fn size(&self) -> SIZE_R {
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SIZE_R::new(self.bits as u8)
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}
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#[doc = "Bit 6 - SPI Clock Polarity"]
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#[inline(always)]
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pub fn spo(&self) -> SPO_R {
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SPO_R::new(((self.bits >> 6) & 0x01) != 0)
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}
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#[doc = "Bit 7 - SPI Clock Phase"]
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#[inline(always)]
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pub fn sph(&self) -> SPH_R {
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SPH_R::new(((self.bits >> 7) & 0x01) != 0)
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}
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#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
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#[inline(always)]
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pub fn scrdv(&self) -> SCRDV_R {
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SCRDV_R::new(((self.bits >> 8) & 0xff) as u8)
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}
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}
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impl W {
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#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
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#[inline(always)]
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pub fn size(&mut self) -> SIZE_W {
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SIZE_W { w: self }
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}
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#[doc = "Bit 6 - SPI Clock Polarity"]
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#[inline(always)]
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pub fn spo(&mut self) -> SPO_W {
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SPO_W { w: self }
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}
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#[doc = "Bit 7 - SPI Clock Phase"]
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#[inline(always)]
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pub fn sph(&mut self) -> SPH_W {
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SPH_W { w: self }
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}
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#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
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#[inline(always)]
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pub fn scrdv(&mut self) -> SCRDV_W {
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SCRDV_W { w: self }
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl0](index.html) module"]
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pub struct CTRL0_SPEC;
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impl crate::RegisterSpec for CTRL0_SPEC {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [ctrl0::R](R) reader structure"]
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impl crate::Readable for CTRL0_SPEC {
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type Reader = R;
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}
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#[doc = "`write(|w| ..)` method takes [ctrl0::W](W) writer structure"]
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impl crate::Writable for CTRL0_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets CTRL0 to value 0"]
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impl crate::Resettable for CTRL0_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
|
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}
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526
src/spia/ctrl1.rs
Normal file
526
src/spia/ctrl1.rs
Normal file
@ -0,0 +1,526 @@
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#[doc = "Register `CTRL1` reader"]
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pub struct R(crate::R<CTRL1_SPEC>);
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impl core::ops::Deref for R {
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type Target = crate::R<CTRL1_SPEC>;
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#[inline(always)]
|
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fn deref(&self) -> &Self::Target {
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&self.0
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||||
}
|
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}
|
||||
impl From<crate::R<CTRL1_SPEC>> for R {
|
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#[inline(always)]
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fn from(reader: crate::R<CTRL1_SPEC>) -> Self {
|
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R(reader)
|
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}
|
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}
|
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#[doc = "Register `CTRL1` writer"]
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pub struct W(crate::W<CTRL1_SPEC>);
|
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impl core::ops::Deref for W {
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type Target = crate::W<CTRL1_SPEC>;
|
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#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
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fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<CTRL1_SPEC>> for W {
|
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#[inline(always)]
|
||||
fn from(writer: crate::W<CTRL1_SPEC>) -> Self {
|
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W(writer)
|
||||
}
|
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}
|
||||
#[doc = "Field `LBM` reader - Loop Back"]
|
||||
pub struct LBM_R(crate::FieldReader<bool, bool>);
|
||||
impl LBM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
LBM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for LBM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `LBM` writer - Loop Back"]
|
||||
pub struct LBM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> LBM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = value as u32;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ENABLE` reader - Enable"]
|
||||
pub struct ENABLE_R(crate::FieldReader<bool, bool>);
|
||||
impl ENABLE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
ENABLE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for ENABLE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `ENABLE` writer - Enable"]
|
||||
pub struct ENABLE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> ENABLE_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MS` reader - Master/Slave (0:Master, 1:Slave)"]
|
||||
pub struct MS_R(crate::FieldReader<bool, bool>);
|
||||
impl MS_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
MS_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for MS_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MS` writer - Master/Slave (0:Master, 1:Slave)"]
|
||||
pub struct MS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> MS_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `SOD` reader - Slave output Disable"]
|
||||
pub struct SOD_R(crate::FieldReader<bool, bool>);
|
||||
impl SOD_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
SOD_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for SOD_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `SOD` writer - Slave output Disable"]
|
||||
pub struct SOD_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> SOD_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `SS` reader - Slave Select"]
|
||||
pub struct SS_R(crate::FieldReader<u8, u8>);
|
||||
impl SS_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: u8) -> Self {
|
||||
SS_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for SS_R {
|
||||
type Target = crate::FieldReader<u8, u8>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `SS` writer - Slave Select"]
|
||||
pub struct SS_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> SS_W<'a> {
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: u8) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x07 << 4)) | ((value as u32 & 0x07) << 4);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BLOCKMODE` reader - Block Mode Enable"]
|
||||
pub struct BLOCKMODE_R(crate::FieldReader<bool, bool>);
|
||||
impl BLOCKMODE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
BLOCKMODE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for BLOCKMODE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BLOCKMODE` writer - Block Mode Enable"]
|
||||
pub struct BLOCKMODE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> BLOCKMODE_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BMSTART` reader - Block Mode Start Status Enable"]
|
||||
pub struct BMSTART_R(crate::FieldReader<bool, bool>);
|
||||
impl BMSTART_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
BMSTART_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for BMSTART_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BMSTART` writer - Block Mode Start Status Enable"]
|
||||
pub struct BMSTART_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> BMSTART_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BMSTALL` reader - Block Mode Stall Enable"]
|
||||
pub struct BMSTALL_R(crate::FieldReader<bool, bool>);
|
||||
impl BMSTALL_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
BMSTALL_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for BMSTALL_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BMSTALL` writer - Block Mode Stall Enable"]
|
||||
pub struct BMSTALL_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> BMSTALL_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MDLYCAP` reader - Master Delayed Capture Enable"]
|
||||
pub struct MDLYCAP_R(crate::FieldReader<bool, bool>);
|
||||
impl MDLYCAP_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
MDLYCAP_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for MDLYCAP_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MDLYCAP` writer - Master Delayed Capture Enable"]
|
||||
pub struct MDLYCAP_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> MDLYCAP_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MTXPAUSE` reader - Master Tx Pause Enable"]
|
||||
pub struct MTXPAUSE_R(crate::FieldReader<bool, bool>);
|
||||
impl MTXPAUSE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
MTXPAUSE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for MTXPAUSE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MTXPAUSE` writer - Master Tx Pause Enable"]
|
||||
pub struct MTXPAUSE_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> MTXPAUSE_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Loop Back"]
|
||||
#[inline(always)]
|
||||
pub fn lbm(&self) -> LBM_R {
|
||||
LBM_R::new(self.bits != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Enable"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&self) -> ENABLE_R {
|
||||
ENABLE_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
|
||||
#[inline(always)]
|
||||
pub fn ms(&self) -> MS_R {
|
||||
MS_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Slave output Disable"]
|
||||
#[inline(always)]
|
||||
pub fn sod(&self) -> SOD_R {
|
||||
SOD_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bits 4:6 - Slave Select"]
|
||||
#[inline(always)]
|
||||
pub fn ss(&self) -> SS_R {
|
||||
SS_R::new(((self.bits >> 4) & 0x07) as u8)
|
||||
}
|
||||
#[doc = "Bit 7 - Block Mode Enable"]
|
||||
#[inline(always)]
|
||||
pub fn blockmode(&self) -> BLOCKMODE_R {
|
||||
BLOCKMODE_R::new(((self.bits >> 7) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - Block Mode Start Status Enable"]
|
||||
#[inline(always)]
|
||||
pub fn bmstart(&self) -> BMSTART_R {
|
||||
BMSTART_R::new(((self.bits >> 8) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - Block Mode Stall Enable"]
|
||||
#[inline(always)]
|
||||
pub fn bmstall(&self) -> BMSTALL_R {
|
||||
BMSTALL_R::new(((self.bits >> 9) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 10 - Master Delayed Capture Enable"]
|
||||
#[inline(always)]
|
||||
pub fn mdlycap(&self) -> MDLYCAP_R {
|
||||
MDLYCAP_R::new(((self.bits >> 10) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 11 - Master Tx Pause Enable"]
|
||||
#[inline(always)]
|
||||
pub fn mtxpause(&self) -> MTXPAUSE_R {
|
||||
MTXPAUSE_R::new(((self.bits >> 11) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Loop Back"]
|
||||
#[inline(always)]
|
||||
pub fn lbm(&mut self) -> LBM_W {
|
||||
LBM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - Enable"]
|
||||
#[inline(always)]
|
||||
pub fn enable(&mut self) -> ENABLE_W {
|
||||
ENABLE_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - Master/Slave (0:Master, 1:Slave)"]
|
||||
#[inline(always)]
|
||||
pub fn ms(&mut self) -> MS_W {
|
||||
MS_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 3 - Slave output Disable"]
|
||||
#[inline(always)]
|
||||
pub fn sod(&mut self) -> SOD_W {
|
||||
SOD_W { w: self }
|
||||
}
|
||||
#[doc = "Bits 4:6 - Slave Select"]
|
||||
#[inline(always)]
|
||||
pub fn ss(&mut self) -> SS_W {
|
||||
SS_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 7 - Block Mode Enable"]
|
||||
#[inline(always)]
|
||||
pub fn blockmode(&mut self) -> BLOCKMODE_W {
|
||||
BLOCKMODE_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 8 - Block Mode Start Status Enable"]
|
||||
#[inline(always)]
|
||||
pub fn bmstart(&mut self) -> BMSTART_W {
|
||||
BMSTART_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 9 - Block Mode Stall Enable"]
|
||||
#[inline(always)]
|
||||
pub fn bmstall(&mut self) -> BMSTALL_W {
|
||||
BMSTALL_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 10 - Master Delayed Capture Enable"]
|
||||
#[inline(always)]
|
||||
pub fn mdlycap(&mut self) -> MDLYCAP_W {
|
||||
MDLYCAP_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 11 - Master Tx Pause Enable"]
|
||||
#[inline(always)]
|
||||
pub fn mtxpause(&mut self) -> MTXPAUSE_W {
|
||||
MTXPAUSE_W { w: self }
|
||||
}
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl1](index.html) module"]
|
||||
pub struct CTRL1_SPEC;
|
||||
impl crate::RegisterSpec for CTRL1_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [ctrl1::R](R) reader structure"]
|
||||
impl crate::Readable for CTRL1_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [ctrl1::W](W) writer structure"]
|
||||
impl crate::Writable for CTRL1_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets CTRL1 to value 0"]
|
||||
impl crate::Resettable for CTRL1_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
64
src/spia/data.rs
Normal file
64
src/spia/data.rs
Normal file
@ -0,0 +1,64 @@
|
||||
#[doc = "Register `DATA` reader"]
|
||||
pub struct R(crate::R<DATA_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<DATA_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<DATA_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<DATA_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `DATA` writer"]
|
||||
pub struct W(crate::W<DATA_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<DATA_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<DATA_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<DATA_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Data Input/Output\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"]
|
||||
pub struct DATA_SPEC;
|
||||
impl crate::RegisterSpec for DATA_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [data::R](R) reader structure"]
|
||||
impl crate::Readable for DATA_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"]
|
||||
impl crate::Writable for DATA_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets DATA to value 0"]
|
||||
impl crate::Resettable for DATA_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
99
src/spia/fifo_clr.rs
Normal file
99
src/spia/fifo_clr.rs
Normal file
@ -0,0 +1,99 @@
|
||||
#[doc = "Register `FIFO_CLR` writer"]
|
||||
pub struct W(crate::W<FIFO_CLR_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<FIFO_CLR_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<FIFO_CLR_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<FIFO_CLR_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
|
||||
pub struct RXFIFO_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RXFIFO_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = value as u32;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
|
||||
pub struct TXFIFO_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> TXFIFO_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Clear Rx FIFO"]
|
||||
#[inline(always)]
|
||||
pub fn rxfifo(&mut self) -> RXFIFO_W {
|
||||
RXFIFO_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - Clear Tx FIFO"]
|
||||
#[inline(always)]
|
||||
pub fn txfifo(&mut self) -> TXFIFO_W {
|
||||
TXFIFO_W { w: self }
|
||||
}
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Clear FIFO Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_clr](index.html) module"]
|
||||
pub struct FIFO_CLR_SPEC;
|
||||
impl crate::RegisterSpec for FIFO_CLR_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [fifo_clr::W](W) writer structure"]
|
||||
impl crate::Writable for FIFO_CLR_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets FIFO_CLR to value 0"]
|
||||
impl crate::Resettable for FIFO_CLR_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
153
src/spia/irq_clr.rs
Normal file
153
src/spia/irq_clr.rs
Normal file
@ -0,0 +1,153 @@
|
||||
#[doc = "Register `IRQ_CLR` writer"]
|
||||
pub struct W(crate::W<IRQ_CLR_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<IRQ_CLR_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<IRQ_CLR_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<IRQ_CLR_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RORIM` writer - RX Overrun"]
|
||||
pub struct RORIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RORIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = value as u32;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RTIM` writer - RX Timeout"]
|
||||
pub struct RTIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RTIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXIM` writer - RX Fifo is at least half full"]
|
||||
pub struct RXIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RXIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"]
|
||||
pub struct TXIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> TXIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - RX Overrun"]
|
||||
#[inline(always)]
|
||||
pub fn rorim(&mut self) -> RORIM_W {
|
||||
RORIM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - RX Timeout"]
|
||||
#[inline(always)]
|
||||
pub fn rtim(&mut self) -> RTIM_W {
|
||||
RTIM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - RX Fifo is at least half full"]
|
||||
#[inline(always)]
|
||||
pub fn rxim(&mut self) -> RXIM_W {
|
||||
RXIM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 3 - TX Fifo is at least half empty"]
|
||||
#[inline(always)]
|
||||
pub fn txim(&mut self) -> TXIM_W {
|
||||
TXIM_W { w: self }
|
||||
}
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"]
|
||||
pub struct IRQ_CLR_SPEC;
|
||||
impl crate::RegisterSpec for IRQ_CLR_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"]
|
||||
impl crate::Writable for IRQ_CLR_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets IRQ_CLR to value 0"]
|
||||
impl crate::Resettable for IRQ_CLR_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
254
src/spia/irq_enb.rs
Normal file
254
src/spia/irq_enb.rs
Normal file
@ -0,0 +1,254 @@
|
||||
#[doc = "Register `IRQ_ENB` reader"]
|
||||
pub struct R(crate::R<IRQ_ENB_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<IRQ_ENB_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<IRQ_ENB_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<IRQ_ENB_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `IRQ_ENB` writer"]
|
||||
pub struct W(crate::W<IRQ_ENB_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<IRQ_ENB_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<IRQ_ENB_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<IRQ_ENB_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RORIM` reader - RX Overrun"]
|
||||
pub struct RORIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RORIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RORIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RORIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RORIM` writer - RX Overrun"]
|
||||
pub struct RORIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RORIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = value as u32;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RTIM` reader - RX Timeout"]
|
||||
pub struct RTIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RTIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RTIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RTIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RTIM` writer - RX Timeout"]
|
||||
pub struct RTIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RTIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXIM` reader - RX Fifo is at least half full"]
|
||||
pub struct RXIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RXIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RXIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RXIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXIM` writer - RX Fifo is at least half full"]
|
||||
pub struct RXIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> RXIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"]
|
||||
pub struct TXIM_R(crate::FieldReader<bool, bool>);
|
||||
impl TXIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TXIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TXIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"]
|
||||
pub struct TXIM_W<'a> {
|
||||
w: &'a mut W,
|
||||
}
|
||||
impl<'a> TXIM_W<'a> {
|
||||
#[doc = r"Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W {
|
||||
self.bit(true)
|
||||
}
|
||||
#[doc = r"Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W {
|
||||
self.bit(false)
|
||||
}
|
||||
#[doc = r"Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W {
|
||||
self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - RX Overrun"]
|
||||
#[inline(always)]
|
||||
pub fn rorim(&self) -> RORIM_R {
|
||||
RORIM_R::new(self.bits != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - RX Timeout"]
|
||||
#[inline(always)]
|
||||
pub fn rtim(&self) -> RTIM_R {
|
||||
RTIM_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - RX Fifo is at least half full"]
|
||||
#[inline(always)]
|
||||
pub fn rxim(&self) -> RXIM_R {
|
||||
RXIM_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - TX Fifo is at least half empty"]
|
||||
#[inline(always)]
|
||||
pub fn txim(&self) -> TXIM_R {
|
||||
TXIM_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - RX Overrun"]
|
||||
#[inline(always)]
|
||||
pub fn rorim(&mut self) -> RORIM_W {
|
||||
RORIM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 1 - RX Timeout"]
|
||||
#[inline(always)]
|
||||
pub fn rtim(&mut self) -> RTIM_W {
|
||||
RTIM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 2 - RX Fifo is at least half full"]
|
||||
#[inline(always)]
|
||||
pub fn rxim(&mut self) -> RXIM_W {
|
||||
RXIM_W { w: self }
|
||||
}
|
||||
#[doc = "Bit 3 - TX Fifo is at least half empty"]
|
||||
#[inline(always)]
|
||||
pub fn txim(&mut self) -> TXIM_W {
|
||||
TXIM_W { w: self }
|
||||
}
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_enb](index.html) module"]
|
||||
pub struct IRQ_ENB_SPEC;
|
||||
impl crate::RegisterSpec for IRQ_ENB_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [irq_enb::R](R) reader structure"]
|
||||
impl crate::Readable for IRQ_ENB_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [irq_enb::W](W) writer structure"]
|
||||
impl crate::Writable for IRQ_ENB_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets IRQ_ENB to value 0"]
|
||||
impl crate::Resettable for IRQ_ENB_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
113
src/spia/irq_end.rs
Normal file
113
src/spia/irq_end.rs
Normal file
@ -0,0 +1,113 @@
|
||||
#[doc = "Register `IRQ_END` reader"]
|
||||
pub struct R(crate::R<IRQ_END_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<IRQ_END_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<IRQ_END_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<IRQ_END_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RORIM` reader - RX Overrun"]
|
||||
pub struct RORIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RORIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RORIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RORIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RTIM` reader - RX Timeout"]
|
||||
pub struct RTIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RTIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RTIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RTIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXIM` reader - RX Fifo is at least half full"]
|
||||
pub struct RXIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RXIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RXIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RXIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"]
|
||||
pub struct TXIM_R(crate::FieldReader<bool, bool>);
|
||||
impl TXIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TXIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TXIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - RX Overrun"]
|
||||
#[inline(always)]
|
||||
pub fn rorim(&self) -> RORIM_R {
|
||||
RORIM_R::new(self.bits != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - RX Timeout"]
|
||||
#[inline(always)]
|
||||
pub fn rtim(&self) -> RTIM_R {
|
||||
RTIM_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - RX Fifo is at least half full"]
|
||||
#[inline(always)]
|
||||
pub fn rxim(&self) -> RXIM_R {
|
||||
RXIM_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - TX Fifo is at least half empty"]
|
||||
#[inline(always)]
|
||||
pub fn txim(&self) -> TXIM_R {
|
||||
TXIM_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Enabled Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_end](index.html) module"]
|
||||
pub struct IRQ_END_SPEC;
|
||||
impl crate::RegisterSpec for IRQ_END_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [irq_end::R](R) reader structure"]
|
||||
impl crate::Readable for IRQ_END_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`reset()` method sets IRQ_END to value 0"]
|
||||
impl crate::Resettable for IRQ_END_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
113
src/spia/irq_raw.rs
Normal file
113
src/spia/irq_raw.rs
Normal file
@ -0,0 +1,113 @@
|
||||
#[doc = "Register `IRQ_RAW` reader"]
|
||||
pub struct R(crate::R<IRQ_RAW_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<IRQ_RAW_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<IRQ_RAW_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<IRQ_RAW_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RORIM` reader - RX Overrun"]
|
||||
pub struct RORIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RORIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RORIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RORIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RTIM` reader - RX Timeout"]
|
||||
pub struct RTIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RTIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RTIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RTIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXIM` reader - RX Fifo is at least half full"]
|
||||
pub struct RXIM_R(crate::FieldReader<bool, bool>);
|
||||
impl RXIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RXIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RXIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXIM` reader - TX Fifo is at least half empty"]
|
||||
pub struct TXIM_R(crate::FieldReader<bool, bool>);
|
||||
impl TXIM_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TXIM_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TXIM_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - RX Overrun"]
|
||||
#[inline(always)]
|
||||
pub fn rorim(&self) -> RORIM_R {
|
||||
RORIM_R::new(self.bits != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - RX Timeout"]
|
||||
#[inline(always)]
|
||||
pub fn rtim(&self) -> RTIM_R {
|
||||
RTIM_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - RX Fifo is at least half full"]
|
||||
#[inline(always)]
|
||||
pub fn rxim(&self) -> RXIM_R {
|
||||
RXIM_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - TX Fifo is at least half empty"]
|
||||
#[inline(always)]
|
||||
pub fn txim(&self) -> TXIM_R {
|
||||
TXIM_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Raw Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_raw](index.html) module"]
|
||||
pub struct IRQ_RAW_SPEC;
|
||||
impl crate::RegisterSpec for IRQ_RAW_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [irq_raw::R](R) reader structure"]
|
||||
impl crate::Readable for IRQ_RAW_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`reset()` method sets IRQ_RAW to value 0"]
|
||||
impl crate::Resettable for IRQ_RAW_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
31
src/spia/perid.rs
Normal file
31
src/spia/perid.rs
Normal file
@ -0,0 +1,31 @@
|
||||
#[doc = "Register `PERID` reader"]
|
||||
pub struct R(crate::R<PERID_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<PERID_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<PERID_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<PERID_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Peripheral ID Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perid](index.html) module"]
|
||||
pub struct PERID_SPEC;
|
||||
impl crate::RegisterSpec for PERID_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [perid::R](R) reader structure"]
|
||||
impl crate::Readable for PERID_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`reset()` method sets PERID to value 0x0012_07e1"]
|
||||
impl crate::Resettable for PERID_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0x0012_07e1
|
||||
}
|
||||
}
|
||||
64
src/spia/rxfifoirqtrg.rs
Normal file
64
src/spia/rxfifoirqtrg.rs
Normal file
@ -0,0 +1,64 @@
|
||||
#[doc = "Register `RXFIFOIRQTRG` reader"]
|
||||
pub struct R(crate::R<RXFIFOIRQTRG_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<RXFIFOIRQTRG_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<RXFIFOIRQTRG_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<RXFIFOIRQTRG_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
||||
pub struct W(crate::W<RXFIFOIRQTRG_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<RXFIFOIRQTRG_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<RXFIFOIRQTRG_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<RXFIFOIRQTRG_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Rx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxfifoirqtrg](index.html) module"]
|
||||
pub struct RXFIFOIRQTRG_SPEC;
|
||||
impl crate::RegisterSpec for RXFIFOIRQTRG_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [rxfifoirqtrg::R](R) reader structure"]
|
||||
impl crate::Readable for RXFIFOIRQTRG_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [rxfifoirqtrg::W](W) writer structure"]
|
||||
impl crate::Writable for RXFIFOIRQTRG_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
|
||||
impl crate::Resettable for RXFIFOIRQTRG_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
31
src/spia/state.rs
Normal file
31
src/spia/state.rs
Normal file
@ -0,0 +1,31 @@
|
||||
#[doc = "Register `STATE` reader"]
|
||||
pub struct R(crate::R<STATE_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<STATE_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<STATE_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<STATE_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Internal STATE of SPI Controller\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [state](index.html) module"]
|
||||
pub struct STATE_SPEC;
|
||||
impl crate::RegisterSpec for STATE_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [state::R](R) reader structure"]
|
||||
impl crate::Readable for STATE_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`reset()` method sets STATE to value 0"]
|
||||
impl crate::Resettable for STATE_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
193
src/spia/status.rs
Normal file
193
src/spia/status.rs
Normal file
@ -0,0 +1,193 @@
|
||||
#[doc = "Register `STATUS` reader"]
|
||||
pub struct R(crate::R<STATUS_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<STATUS_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<STATUS_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<STATUS_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TFE` reader - Transmit FIFO empty"]
|
||||
pub struct TFE_R(crate::FieldReader<bool, bool>);
|
||||
impl TFE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TFE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TFE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TNF` reader - Transmit FIFO not full"]
|
||||
pub struct TNF_R(crate::FieldReader<bool, bool>);
|
||||
impl TNF_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TNF_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TNF_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RNE` reader - Receive FIFO not empty"]
|
||||
pub struct RNE_R(crate::FieldReader<bool, bool>);
|
||||
impl RNE_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RNE_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RNE_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RFF` reader - Receive FIFO Full"]
|
||||
pub struct RFF_R(crate::FieldReader<bool, bool>);
|
||||
impl RFF_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RFF_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RFF_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `BUSY` reader - Busy"]
|
||||
pub struct BUSY_R(crate::FieldReader<bool, bool>);
|
||||
impl BUSY_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
BUSY_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for BUSY_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXDATAFIRST` reader - Pending Data is first Byte in BLOCKMODE"]
|
||||
pub struct RXDATAFIRST_R(crate::FieldReader<bool, bool>);
|
||||
impl RXDATAFIRST_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RXDATAFIRST_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RXDATAFIRST_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
|
||||
pub struct RXTRIGGER_R(crate::FieldReader<bool, bool>);
|
||||
impl RXTRIGGER_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
RXTRIGGER_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for RXTRIGGER_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
|
||||
pub struct TXTRIGGER_R(crate::FieldReader<bool, bool>);
|
||||
impl TXTRIGGER_R {
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(bits: bool) -> Self {
|
||||
TXTRIGGER_R(crate::FieldReader::new(bits))
|
||||
}
|
||||
}
|
||||
impl core::ops::Deref for TXTRIGGER_R {
|
||||
type Target = crate::FieldReader<bool, bool>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Transmit FIFO empty"]
|
||||
#[inline(always)]
|
||||
pub fn tfe(&self) -> TFE_R {
|
||||
TFE_R::new(self.bits != 0)
|
||||
}
|
||||
#[doc = "Bit 1 - Transmit FIFO not full"]
|
||||
#[inline(always)]
|
||||
pub fn tnf(&self) -> TNF_R {
|
||||
TNF_R::new(((self.bits >> 1) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 2 - Receive FIFO not empty"]
|
||||
#[inline(always)]
|
||||
pub fn rne(&self) -> RNE_R {
|
||||
RNE_R::new(((self.bits >> 2) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 3 - Receive FIFO Full"]
|
||||
#[inline(always)]
|
||||
pub fn rff(&self) -> RFF_R {
|
||||
RFF_R::new(((self.bits >> 3) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 4 - Busy"]
|
||||
#[inline(always)]
|
||||
pub fn busy(&self) -> BUSY_R {
|
||||
BUSY_R::new(((self.bits >> 4) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 5 - Pending Data is first Byte in BLOCKMODE"]
|
||||
#[inline(always)]
|
||||
pub fn rxdatafirst(&self) -> RXDATAFIRST_R {
|
||||
RXDATAFIRST_R::new(((self.bits >> 5) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 6 - RX FIFO Above Trigger Level"]
|
||||
#[inline(always)]
|
||||
pub fn rxtrigger(&self) -> RXTRIGGER_R {
|
||||
RXTRIGGER_R::new(((self.bits >> 6) & 0x01) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - TX FIFO Below Trigger Level"]
|
||||
#[inline(always)]
|
||||
pub fn txtrigger(&self) -> TXTRIGGER_R {
|
||||
TXTRIGGER_R::new(((self.bits >> 7) & 0x01) != 0)
|
||||
}
|
||||
}
|
||||
#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
|
||||
pub struct STATUS_SPEC;
|
||||
impl crate::RegisterSpec for STATUS_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [status::R](R) reader structure"]
|
||||
impl crate::Readable for STATUS_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`reset()` method sets STATUS to value 0"]
|
||||
impl crate::Resettable for STATUS_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
64
src/spia/txfifoirqtrg.rs
Normal file
64
src/spia/txfifoirqtrg.rs
Normal file
@ -0,0 +1,64 @@
|
||||
#[doc = "Register `TXFIFOIRQTRG` reader"]
|
||||
pub struct R(crate::R<TXFIFOIRQTRG_SPEC>);
|
||||
impl core::ops::Deref for R {
|
||||
type Target = crate::R<TXFIFOIRQTRG_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::R<TXFIFOIRQTRG_SPEC>> for R {
|
||||
#[inline(always)]
|
||||
fn from(reader: crate::R<TXFIFOIRQTRG_SPEC>) -> Self {
|
||||
R(reader)
|
||||
}
|
||||
}
|
||||
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
||||
pub struct W(crate::W<TXFIFOIRQTRG_SPEC>);
|
||||
impl core::ops::Deref for W {
|
||||
type Target = crate::W<TXFIFOIRQTRG_SPEC>;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
&self.0
|
||||
}
|
||||
}
|
||||
impl core::ops::DerefMut for W {
|
||||
#[inline(always)]
|
||||
fn deref_mut(&mut self) -> &mut Self::Target {
|
||||
&mut self.0
|
||||
}
|
||||
}
|
||||
impl From<crate::W<TXFIFOIRQTRG_SPEC>> for W {
|
||||
#[inline(always)]
|
||||
fn from(writer: crate::W<TXFIFOIRQTRG_SPEC>) -> Self {
|
||||
W(writer)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||
self.0.bits(bits);
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = "Tx FIFO IRQ Trigger Level\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [txfifoirqtrg](index.html) module"]
|
||||
pub struct TXFIFOIRQTRG_SPEC;
|
||||
impl crate::RegisterSpec for TXFIFOIRQTRG_SPEC {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [txfifoirqtrg::R](R) reader structure"]
|
||||
impl crate::Readable for TXFIFOIRQTRG_SPEC {
|
||||
type Reader = R;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [txfifoirqtrg::W](W) writer structure"]
|
||||
impl crate::Writable for TXFIFOIRQTRG_SPEC {
|
||||
type Writer = W;
|
||||
}
|
||||
#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
|
||||
impl crate::Resettable for TXFIFOIRQTRG_SPEC {
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
0
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user