Compare commits
8 Commits
Author | SHA1 | Date | |
---|---|---|---|
f626e33e72 | |||
4da8267c9c | |||
002b277ae2 | |||
6a8c58bfce | |||
a5e5f02f7c | |||
91a2db0f6f | |||
cba43bc221 | |||
ed22f9a76f |
5
.github/workflows/ci.yml
vendored
5
.github/workflows/ci.yml
vendored
|
@ -16,9 +16,7 @@ jobs:
|
||||||
override: true
|
override: true
|
||||||
- uses: actions-rs/cargo@v1
|
- uses: actions-rs/cargo@v1
|
||||||
with:
|
with:
|
||||||
use-cross: true
|
|
||||||
command: check
|
command: check
|
||||||
args: --target thumbv6m-none-eabi
|
|
||||||
|
|
||||||
fmt:
|
fmt:
|
||||||
name: Rustfmt
|
name: Rustfmt
|
||||||
|
@ -50,9 +48,8 @@ jobs:
|
||||||
- run: rustup component add clippy
|
- run: rustup component add clippy
|
||||||
- uses: actions-rs/cargo@v1
|
- uses: actions-rs/cargo@v1
|
||||||
with:
|
with:
|
||||||
use-cross: true
|
|
||||||
command: clippy
|
command: clippy
|
||||||
args: --target thumbv6m-none-eabi -- -D warnings
|
args: -- -D warnings
|
||||||
|
|
||||||
ci:
|
ci:
|
||||||
if: ${{ success() }}
|
if: ${{ success() }}
|
||||||
|
|
|
@ -8,7 +8,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
||||||
|
|
||||||
## [unreleased]
|
## [unreleased]
|
||||||
|
|
||||||
- Added peripheral reset fields for PERIPHERAL_RESET register
|
## [v0.2.4]
|
||||||
|
|
||||||
|
- Added missing bitfield `CSDTRG2` in `CSD_CTRL` register of `TIM0` peripheral
|
||||||
|
|
||||||
|
## [v0.2.3]
|
||||||
|
|
||||||
|
- Added peripheral reset fields for `PERIPHERAL_RESET` register
|
||||||
|
|
||||||
## [v0.2.2]
|
## [v0.2.2]
|
||||||
|
|
||||||
|
|
|
@ -1,11 +1,11 @@
|
||||||
[package]
|
[package]
|
||||||
name = "va108xx"
|
name = "va108xx"
|
||||||
version = "0.2.3"
|
version = "0.2.4"
|
||||||
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
||||||
edition = "2021"
|
edition = "2021"
|
||||||
description = "PAC for the Vorago VA108xx family of microcontrollers"
|
description = "PAC for the Vorago VA108xx family of microcontrollers"
|
||||||
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
|
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
|
||||||
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
|
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
|
||||||
license = "Apache-2.0"
|
license = "Apache-2.0"
|
||||||
keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
|
keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
|
||||||
categories = ["embedded", "no-std", "hardware-support"]
|
categories = ["embedded", "no-std", "hardware-support"]
|
||||||
|
|
|
@ -10,7 +10,7 @@ Voragos VA108xx series of Cortex-M0 based microcontrollers.
|
||||||
The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
|
The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
|
||||||
|
|
||||||
If you are interested in higher-level abstractions, it is recommended you visit
|
If you are interested in higher-level abstractions, it is recommended you visit
|
||||||
the [`va108xx-hal` HAL crate](https://github.com/robamu-org/va108xx-hal-rs) and
|
the [`va108xx-hal` HAL crate](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal) and
|
||||||
the [`vorago-reb1` BSP crate](https://github.com/robamu-org/vorago-reb1-rs) which build on top of
|
the [`vorago-reb1` BSP crate](https://github.com/robamu-org/vorago-reb1-rs) which build on top of
|
||||||
this PAC and provide application examples as well.
|
this PAC and provide application examples as well.
|
||||||
|
|
||||||
|
|
4
automation/Jenkinsfile
vendored
4
automation/Jenkinsfile
vendored
|
@ -24,7 +24,7 @@ pipeline {
|
||||||
sh 'cargo fmt'
|
sh 'cargo fmt'
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
stage('Build') {
|
stage('Check') {
|
||||||
agent {
|
agent {
|
||||||
dockerfile {
|
dockerfile {
|
||||||
dir 'automation'
|
dir 'automation'
|
||||||
|
@ -32,7 +32,7 @@ pipeline {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
steps {
|
steps {
|
||||||
sh 'cargo build'
|
sh 'cargo check --target thumbv6m-none-eabi'
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -404,6 +404,43 @@ impl<'a> CSDXXX2_W<'a> {
|
||||||
self.w
|
self.w
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
|
||||||
|
pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
|
||||||
|
impl CSDTRG2_R {
|
||||||
|
#[inline(always)]
|
||||||
|
pub(crate) fn new(bits: bool) -> Self {
|
||||||
|
CSDTRG2_R(crate::FieldReader::new(bits))
|
||||||
|
}
|
||||||
|
}
|
||||||
|
impl core::ops::Deref for CSDTRG2_R {
|
||||||
|
type Target = crate::FieldReader<bool, bool>;
|
||||||
|
#[inline(always)]
|
||||||
|
fn deref(&self) -> &Self::Target {
|
||||||
|
&self.0
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
|
||||||
|
pub struct CSDTRG2_W<'a> {
|
||||||
|
w: &'a mut W,
|
||||||
|
}
|
||||||
|
impl<'a> CSDTRG2_W<'a> {
|
||||||
|
#[doc = r"Sets the field bit"]
|
||||||
|
#[inline(always)]
|
||||||
|
pub fn set_bit(self) -> &'a mut W {
|
||||||
|
self.bit(true)
|
||||||
|
}
|
||||||
|
#[doc = r"Clears the field bit"]
|
||||||
|
#[inline(always)]
|
||||||
|
pub fn clear_bit(self) -> &'a mut W {
|
||||||
|
self.bit(false)
|
||||||
|
}
|
||||||
|
#[doc = r"Writes raw bits to the field"]
|
||||||
|
#[inline(always)]
|
||||||
|
pub fn bit(self, value: bool) -> &'a mut W {
|
||||||
|
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
|
||||||
|
self.w
|
||||||
|
}
|
||||||
|
}
|
||||||
impl R {
|
impl R {
|
||||||
#[doc = "Bit 0 - Cascade 0 Enable"]
|
#[doc = "Bit 0 - Cascade 0 Enable"]
|
||||||
#[inline(always)]
|
#[inline(always)]
|
||||||
|
@ -455,6 +492,11 @@ impl R {
|
||||||
pub fn csdxxx2(&self) -> CSDXXX2_R {
|
pub fn csdxxx2(&self) -> CSDXXX2_R {
|
||||||
CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
|
CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
|
||||||
}
|
}
|
||||||
|
#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
|
||||||
|
#[inline(always)]
|
||||||
|
pub fn csdtrg2(&self) -> CSDTRG2_R {
|
||||||
|
CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
|
||||||
|
}
|
||||||
}
|
}
|
||||||
impl W {
|
impl W {
|
||||||
#[doc = "Bit 0 - Cascade 0 Enable"]
|
#[doc = "Bit 0 - Cascade 0 Enable"]
|
||||||
|
@ -507,6 +549,11 @@ impl W {
|
||||||
pub fn csdxxx2(&mut self) -> CSDXXX2_W {
|
pub fn csdxxx2(&mut self) -> CSDXXX2_W {
|
||||||
CSDXXX2_W { w: self }
|
CSDXXX2_W { w: self }
|
||||||
}
|
}
|
||||||
|
#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
|
||||||
|
#[inline(always)]
|
||||||
|
pub fn csdtrg2(&mut self) -> CSDTRG2_W {
|
||||||
|
CSDTRG2_W { w: self }
|
||||||
|
}
|
||||||
#[doc = "Writes raw bits to the register."]
|
#[doc = "Writes raw bits to the register."]
|
||||||
#[inline(always)]
|
#[inline(always)]
|
||||||
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
|
||||||
|
|
|
@ -1296,7 +1296,8 @@
|
||||||
<description>Cascade 2 test mode</description>
|
<description>Cascade 2 test mode</description>
|
||||||
<bitRange>[11:11]</bitRange>
|
<bitRange>[11:11]</bitRange>
|
||||||
</field>
|
</field>
|
||||||
</fields>
|
<field><name>CSDTRG2</name><description>Cascade 2 Enabled as Trigger</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
|
||||||
|
</fields>
|
||||||
</register>
|
</register>
|
||||||
<register>
|
<register>
|
||||||
<name>CASCADE0</name>
|
<name>CASCADE0</name>
|
||||||
|
|
|
@ -126,3 +126,12 @@ I2CA:
|
||||||
description: Controller is Idle
|
description: Controller is Idle
|
||||||
bitOffset: 1
|
bitOffset: 1
|
||||||
bitWidth: 1
|
bitWidth: 1
|
||||||
|
|
||||||
|
# All TIMs are derived from TIM0
|
||||||
|
TIM0:
|
||||||
|
CSD_CTRL:
|
||||||
|
_add:
|
||||||
|
CSDTRG2:
|
||||||
|
description: Cascade 2 Enabled as Trigger
|
||||||
|
bitOffset: 10
|
||||||
|
bitWidth: 1
|
||||||
|
|
Loading…
Reference in New Issue
Block a user