Compare commits
8 Commits
Author | SHA1 | Date | |
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f626e33e72 | |||
4da8267c9c | |||
002b277ae2 | |||
6a8c58bfce | |||
a5e5f02f7c | |||
91a2db0f6f | |||
cba43bc221 | |||
ed22f9a76f |
5
.github/workflows/ci.yml
vendored
5
.github/workflows/ci.yml
vendored
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@ -16,9 +16,7 @@ jobs:
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override: true
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- uses: actions-rs/cargo@v1
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with:
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use-cross: true
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command: check
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args: --target thumbv6m-none-eabi
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fmt:
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name: Rustfmt
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@ -50,9 +48,8 @@ jobs:
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- run: rustup component add clippy
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- uses: actions-rs/cargo@v1
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with:
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use-cross: true
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command: clippy
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args: --target thumbv6m-none-eabi -- -D warnings
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args: -- -D warnings
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ci:
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if: ${{ success() }}
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@ -8,7 +8,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [unreleased]
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- Added peripheral reset fields for PERIPHERAL_RESET register
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## [v0.2.4]
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- Added missing bitfield `CSDTRG2` in `CSD_CTRL` register of `TIM0` peripheral
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## [v0.2.3]
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- Added peripheral reset fields for `PERIPHERAL_RESET` register
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## [v0.2.2]
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@ -1,11 +1,11 @@
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[package]
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name = "va108xx"
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version = "0.2.3"
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version = "0.2.4"
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authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
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edition = "2021"
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description = "PAC for the Vorago VA108xx family of microcontrollers"
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homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
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repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
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homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
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repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
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license = "Apache-2.0"
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keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
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categories = ["embedded", "no-std", "hardware-support"]
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@ -10,7 +10,7 @@ Voragos VA108xx series of Cortex-M0 based microcontrollers.
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The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
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If you are interested in higher-level abstractions, it is recommended you visit
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the [`va108xx-hal` HAL crate](https://github.com/robamu-org/va108xx-hal-rs) and
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the [`va108xx-hal` HAL crate](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal) and
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the [`vorago-reb1` BSP crate](https://github.com/robamu-org/vorago-reb1-rs) which build on top of
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this PAC and provide application examples as well.
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4
automation/Jenkinsfile
vendored
4
automation/Jenkinsfile
vendored
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@ -24,7 +24,7 @@ pipeline {
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sh 'cargo fmt'
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}
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}
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stage('Build') {
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stage('Check') {
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agent {
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dockerfile {
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dir 'automation'
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@ -32,7 +32,7 @@ pipeline {
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}
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}
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steps {
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sh 'cargo build'
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sh 'cargo check --target thumbv6m-none-eabi'
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}
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}
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}
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@ -404,6 +404,43 @@ impl<'a> CSDXXX2_W<'a> {
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self.w
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}
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}
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#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
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pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
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impl CSDTRG2_R {
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#[inline(always)]
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pub(crate) fn new(bits: bool) -> Self {
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CSDTRG2_R(crate::FieldReader::new(bits))
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}
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}
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impl core::ops::Deref for CSDTRG2_R {
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type Target = crate::FieldReader<bool, bool>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
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pub struct CSDTRG2_W<'a> {
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w: &'a mut W,
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}
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impl<'a> CSDTRG2_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
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self.w
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}
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}
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impl R {
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#[doc = "Bit 0 - Cascade 0 Enable"]
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#[inline(always)]
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@ -455,6 +492,11 @@ impl R {
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pub fn csdxxx2(&self) -> CSDXXX2_R {
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CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
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}
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#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
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#[inline(always)]
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pub fn csdtrg2(&self) -> CSDTRG2_R {
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CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Cascade 0 Enable"]
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@ -507,6 +549,11 @@ impl W {
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pub fn csdxxx2(&mut self) -> CSDXXX2_W {
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CSDXXX2_W { w: self }
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}
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#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
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#[inline(always)]
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pub fn csdtrg2(&mut self) -> CSDTRG2_W {
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CSDTRG2_W { w: self }
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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@ -1296,7 +1296,8 @@
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<description>Cascade 2 test mode</description>
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<bitRange>[11:11]</bitRange>
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</field>
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</fields>
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<field><name>CSDTRG2</name><description>Cascade 2 Enabled as Trigger</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
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</fields>
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</register>
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<register>
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<name>CASCADE0</name>
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@ -126,3 +126,12 @@ I2CA:
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description: Controller is Idle
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bitOffset: 1
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bitWidth: 1
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# All TIMs are derived from TIM0
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TIM0:
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CSD_CTRL:
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_add:
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CSDTRG2:
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description: Cascade 2 Enabled as Trigger
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bitOffset: 10
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bitWidth: 1
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Block a user