simplify CI

Reviewed-on: rust/va108xx-rs#5

.github/workflows/ci.yml

@@ -16,9 +16,7 @@ jobs:
           override: true
       - uses: actions-rs/cargo@v1
         with:
-          use-cross: true
           command: check
-          args: --target thumbv6m-none-eabi
 
   fmt:
     name: Rustfmt
@@ -50,9 +48,8 @@ jobs:
       - run: rustup component add clippy
       - uses: actions-rs/cargo@v1
         with:
-          use-cross: true
           command: clippy
-          args: --target thumbv6m-none-eabi -- -D warnings
+          args: -- -D warnings
 
   ci:
       if: ${{ success() }}

CHANGELOG.md

@@ -8,7 +8,13 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
-- Added peripheral reset fields for PERIPHERAL_RESET register
+## [v0.2.4]
+
+- Added missing bitfield `CSDTRG2` in `CSD_CTRL` register of `TIM0` peripheral
+
+## [v0.2.3]
+
+- Added peripheral reset fields for `PERIPHERAL_RESET` register
 
 ## [v0.2.2]
 

Cargo.toml

@@ -1,11 +1,11 @@
 [package]
 name = "va108xx"
-version = "0.2.3"
+version = "0.2.4"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "PAC for the Vorago VA108xx family of microcontrollers"
-homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
-repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx-rs"
+homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
+repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
 license = "Apache-2.0"
 keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
 categories = ["embedded", "no-std", "hardware-support"]

README.md

@@ -10,7 +10,7 @@ Voragos VA108xx series of Cortex-M0 based microcontrollers.
 The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
 
 If you are interested in higher-level abstractions, it is recommended you visit
-the [`va108xx-hal` HAL crate](https://github.com/robamu-org/va108xx-hal-rs) and
+the [`va108xx-hal` HAL crate](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal) and
 the [`vorago-reb1` BSP crate](https://github.com/robamu-org/vorago-reb1-rs) which build on top of
 this PAC and provide application examples as well.
 

automation/Jenkinsfile

@@ -24,7 +24,7 @@ pipeline {
                 sh 'cargo fmt'
             }
         }
-        stage('Build') {
+        stage('Check') {
             agent {
                 dockerfile {
                     dir 'automation'
@@ -32,7 +32,7 @@ pipeline {
                 }
             }
             steps {
-                sh 'cargo build'
+                sh 'cargo check --target thumbv6m-none-eabi'
             }
         }
     }

src/tim0/csd_ctrl.rs

@@ -404,6 +404,43 @@ impl<'a> CSDXXX2_W<'a> {
         self.w
     }
 }
+#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
+pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
+impl CSDTRG2_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CSDTRG2_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CSDTRG2_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
+pub struct CSDTRG2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CSDTRG2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
 impl R {
     #[doc = "Bit 0 - Cascade 0 Enable"]
     #[inline(always)]
@@ -455,6 +492,11 @@ impl R {
     pub fn csdxxx2(&self) -> CSDXXX2_R {
         CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
     }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&self) -> CSDTRG2_R {
+        CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
 }
 impl W {
     #[doc = "Bit 0 - Cascade 0 Enable"]
@@ -507,6 +549,11 @@ impl W {
     pub fn csdxxx2(&mut self) -> CSDXXX2_W {
         CSDXXX2_W { w: self }
     }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&mut self) -> CSDTRG2_W {
+        CSDTRG2_W { w: self }
+    }
     #[doc = "Writes raw bits to the register."]
     #[inline(always)]
     pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {

svd/va108xx-base.svd.patched

@@ -1296,7 +1296,8 @@
               <description>Cascade 2 test  mode</description>
               <bitRange>[11:11]</bitRange>
             </field>
-          </fields>
+          <field><name>CSDTRG2</name><description>Cascade 2 Enabled as Trigger</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
+            </fields>
         </register>
         <register>
           <name>CASCADE0</name>

svd/va108xx-patch.yml

@@ -126,3 +126,12 @@ I2CA:
         description: Controller is Idle
         bitOffset: 1
         bitWidth: 1
+
+# All TIMs are derived from TIM0
+TIM0:
+  CSD_CTRL:
+    _add:
+      CSDTRG2:
+        description: Cascade 2 Enabled as Trigger
+        bitOffset: 10
+        bitWidth: 1