Init Commit

Monorepo for Rust support of VA416XX family of radiation hardened MCUs

va416xx/src/uart0/addr9.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `ADDR9` reader"]
+pub type R = crate::R<Addr9Spec>;
+#[doc = "Register `ADDR9` writer"]
+pub type W = crate::W<Addr9Spec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Address9 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Addr9Spec;
+impl crate::RegisterSpec for Addr9Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`addr9::R`](R) reader structure"]
+impl crate::Readable for Addr9Spec {}
+#[doc = "`write(|w| ..)` method takes [`addr9::W`](W) writer structure"]
+impl crate::Writable for Addr9Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ADDR9 to value 0"]
+impl crate::Resettable for Addr9Spec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/addr9mask.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `ADDR9MASK` reader"]
+pub type R = crate::R<Addr9maskSpec>;
+#[doc = "Register `ADDR9MASK` writer"]
+pub type W = crate::W<Addr9maskSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Address9 Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`addr9mask::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`addr9mask::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct Addr9maskSpec;
+impl crate::RegisterSpec for Addr9maskSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`addr9mask::R`](R) reader structure"]
+impl crate::Readable for Addr9maskSpec {}
+#[doc = "`write(|w| ..)` method takes [`addr9mask::W`](W) writer structure"]
+impl crate::Writable for Addr9maskSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ADDR9MASK to value 0"]
+impl crate::Resettable for Addr9maskSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/clkscale.rs

@@ -0,0 +1,63 @@
+#[doc = "Register `CLKSCALE` reader"]
+pub type R = crate::R<ClkscaleSpec>;
+#[doc = "Register `CLKSCALE` writer"]
+pub type W = crate::W<ClkscaleSpec>;
+#[doc = "Field `FRAC` reader - Fractional Divide (64ths)"]
+pub type FracR = crate::FieldReader;
+#[doc = "Field `FRAC` writer - Fractional Divide (64ths)"]
+pub type FracW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
+#[doc = "Field `INT` reader - Integer Divide"]
+pub type IntR = crate::FieldReader<u32>;
+#[doc = "Field `INT` writer - Integer Divide"]
+pub type IntW<'a, REG> = crate::FieldWriter<'a, REG, 18, u32>;
+#[doc = "Field `RESET` writer - Reset Baud Counter"]
+pub type ResetW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bits 0:5 - Fractional Divide (64ths)"]
+    #[inline(always)]
+    pub fn frac(&self) -> FracR {
+        FracR::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bits 6:23 - Integer Divide"]
+    #[inline(always)]
+    pub fn int(&self) -> IntR {
+        IntR::new((self.bits >> 6) & 0x0003_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 0:5 - Fractional Divide (64ths)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn frac(&mut self) -> FracW<ClkscaleSpec> {
+        FracW::new(self, 0)
+    }
+    #[doc = "Bits 6:23 - Integer Divide"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int(&mut self) -> IntW<ClkscaleSpec> {
+        IntW::new(self, 6)
+    }
+    #[doc = "Bit 31 - Reset Baud Counter"]
+    #[inline(always)]
+    #[must_use]
+    pub fn reset(&mut self) -> ResetW<ClkscaleSpec> {
+        ResetW::new(self, 31)
+    }
+}
+#[doc = "Clock Scale Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkscale::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkscale::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ClkscaleSpec;
+impl crate::RegisterSpec for ClkscaleSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`clkscale::R`](R) reader structure"]
+impl crate::Readable for ClkscaleSpec {}
+#[doc = "`write(|w| ..)` method takes [`clkscale::W`](W) writer structure"]
+impl crate::Writable for ClkscaleSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CLKSCALE to value 0"]
+impl crate::Resettable for ClkscaleSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/ctrl.rs

@@ -0,0 +1,190 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CtrlSpec>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CtrlSpec>;
+#[doc = "Field `PAREN` reader - Parity Enable"]
+pub type ParenR = crate::BitReader;
+#[doc = "Field `PAREN` writer - Parity Enable"]
+pub type ParenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PAREVEN` reader - Parity Even/Odd(1/0)"]
+pub type ParevenR = crate::BitReader;
+#[doc = "Field `PAREVEN` writer - Parity Even/Odd(1/0)"]
+pub type ParevenW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `PARSTK` reader - Parity Sticky"]
+pub type ParstkR = crate::BitReader;
+#[doc = "Field `PARSTK` writer - Parity Sticky"]
+pub type ParstkW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `STOPBITS` reader - Stop Bits 1/2(0/1)"]
+pub type StopbitsR = crate::BitReader;
+#[doc = "Field `STOPBITS` writer - Stop Bits 1/2(0/1)"]
+pub type StopbitsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `WORDSIZE` reader - Word Size in Bits 5/6/7/8(00/01/10/11)"]
+pub type WordsizeR = crate::FieldReader;
+#[doc = "Field `WORDSIZE` writer - Word Size in Bits 5/6/7/8(00/01/10/11)"]
+pub type WordsizeW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
+#[doc = "Field `LOOPBACK` reader - Loopback Enable"]
+pub type LoopbackR = crate::BitReader;
+#[doc = "Field `LOOPBACK` writer - Loopback Enable"]
+pub type LoopbackW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `LOOPBACKBLK` reader - Loopback Block"]
+pub type LoopbackblkR = crate::BitReader;
+#[doc = "Field `LOOPBACKBLK` writer - Loopback Block"]
+pub type LoopbackblkW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AUTOCTS` reader - Enable Auto CTS mode"]
+pub type AutoctsR = crate::BitReader;
+#[doc = "Field `AUTOCTS` writer - Enable Auto CTS mode"]
+pub type AutoctsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `DEFRTS` reader - Default RTSn value"]
+pub type DefrtsR = crate::BitReader;
+#[doc = "Field `DEFRTS` writer - Default RTSn value"]
+pub type DefrtsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `AUTORTS` reader - Enable Auto RTS mode"]
+pub type AutortsR = crate::BitReader;
+#[doc = "Field `AUTORTS` writer - Enable Auto RTS mode"]
+pub type AutortsW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `BAUD8` reader - Enable BAUD8 mode"]
+pub type Baud8R = crate::BitReader;
+#[doc = "Field `BAUD8` writer - Enable BAUD8 mode"]
+pub type Baud8W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Parity Enable"]
+    #[inline(always)]
+    pub fn paren(&self) -> ParenR {
+        ParenR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Parity Even/Odd(1/0)"]
+    #[inline(always)]
+    pub fn pareven(&self) -> ParevenR {
+        ParevenR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Parity Sticky"]
+    #[inline(always)]
+    pub fn parstk(&self) -> ParstkR {
+        ParstkR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Stop Bits 1/2(0/1)"]
+    #[inline(always)]
+    pub fn stopbits(&self) -> StopbitsR {
+        StopbitsR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"]
+    #[inline(always)]
+    pub fn wordsize(&self) -> WordsizeR {
+        WordsizeR::new(((self.bits >> 4) & 3) as u8)
+    }
+    #[doc = "Bit 6 - Loopback Enable"]
+    #[inline(always)]
+    pub fn loopback(&self) -> LoopbackR {
+        LoopbackR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - Loopback Block"]
+    #[inline(always)]
+    pub fn loopbackblk(&self) -> LoopbackblkR {
+        LoopbackblkR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - Enable Auto CTS mode"]
+    #[inline(always)]
+    pub fn autocts(&self) -> AutoctsR {
+        AutoctsR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Default RTSn value"]
+    #[inline(always)]
+    pub fn defrts(&self) -> DefrtsR {
+        DefrtsR::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 10 - Enable Auto RTS mode"]
+    #[inline(always)]
+    pub fn autorts(&self) -> AutortsR {
+        AutortsR::new(((self.bits >> 10) & 1) != 0)
+    }
+    #[doc = "Bit 11 - Enable BAUD8 mode"]
+    #[inline(always)]
+    pub fn baud8(&self) -> Baud8R {
+        Baud8R::new(((self.bits >> 11) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Parity Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn paren(&mut self) -> ParenW<CtrlSpec> {
+        ParenW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Parity Even/Odd(1/0)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn pareven(&mut self) -> ParevenW<CtrlSpec> {
+        ParevenW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Parity Sticky"]
+    #[inline(always)]
+    #[must_use]
+    pub fn parstk(&mut self) -> ParstkW<CtrlSpec> {
+        ParstkW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Stop Bits 1/2(0/1)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn stopbits(&mut self) -> StopbitsW<CtrlSpec> {
+        StopbitsW::new(self, 3)
+    }
+    #[doc = "Bits 4:5 - Word Size in Bits 5/6/7/8(00/01/10/11)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn wordsize(&mut self) -> WordsizeW<CtrlSpec> {
+        WordsizeW::new(self, 4)
+    }
+    #[doc = "Bit 6 - Loopback Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn loopback(&mut self) -> LoopbackW<CtrlSpec> {
+        LoopbackW::new(self, 6)
+    }
+    #[doc = "Bit 7 - Loopback Block"]
+    #[inline(always)]
+    #[must_use]
+    pub fn loopbackblk(&mut self) -> LoopbackblkW<CtrlSpec> {
+        LoopbackblkW::new(self, 7)
+    }
+    #[doc = "Bit 8 - Enable Auto CTS mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn autocts(&mut self) -> AutoctsW<CtrlSpec> {
+        AutoctsW::new(self, 8)
+    }
+    #[doc = "Bit 9 - Default RTSn value"]
+    #[inline(always)]
+    #[must_use]
+    pub fn defrts(&mut self) -> DefrtsW<CtrlSpec> {
+        DefrtsW::new(self, 9)
+    }
+    #[doc = "Bit 10 - Enable Auto RTS mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn autorts(&mut self) -> AutortsW<CtrlSpec> {
+        AutortsW::new(self, 10)
+    }
+    #[doc = "Bit 11 - Enable BAUD8 mode"]
+    #[inline(always)]
+    #[must_use]
+    pub fn baud8(&mut self) -> Baud8W<CtrlSpec> {
+        Baud8W::new(self, 11)
+    }
+}
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlSpec;
+impl crate::RegisterSpec for CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/data.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `DATA` reader"]
+pub type R = crate::R<DataSpec>;
+#[doc = "Register `DATA` writer"]
+pub type W = crate::W<DataSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Data In/Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`data::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`data::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DataSpec;
+impl crate::RegisterSpec for DataSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`data::R`](R) reader structure"]
+impl crate::Readable for DataSpec {}
+#[doc = "`write(|w| ..)` method takes [`data::W`](W) writer structure"]
+impl crate::Writable for DataSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DATA to value 0"]
+impl crate::Resettable for DataSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/enable.rs

@@ -0,0 +1,55 @@
+#[doc = "Register `ENABLE` reader"]
+pub type R = crate::R<EnableSpec>;
+#[doc = "Register `ENABLE` writer"]
+pub type W = crate::W<EnableSpec>;
+#[doc = "Field `RXENABLE` reader - Rx Enable"]
+pub type RxenableR = crate::BitReader;
+#[doc = "Field `RXENABLE` writer - Rx Enable"]
+pub type RxenableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXENABLE` reader - Tx Enable"]
+pub type TxenableR = crate::BitReader;
+#[doc = "Field `TXENABLE` writer - Tx Enable"]
+pub type TxenableW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Rx Enable"]
+    #[inline(always)]
+    pub fn rxenable(&self) -> RxenableR {
+        RxenableR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Tx Enable"]
+    #[inline(always)]
+    pub fn txenable(&self) -> TxenableR {
+        TxenableR::new(((self.bits >> 1) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Rx Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxenable(&mut self) -> RxenableW<EnableSpec> {
+        RxenableW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Tx Enable"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txenable(&mut self) -> TxenableW<EnableSpec> {
+        TxenableW::new(self, 1)
+    }
+}
+#[doc = "Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct EnableSpec;
+impl crate::RegisterSpec for EnableSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`enable::R`](R) reader structure"]
+impl crate::Readable for EnableSpec {}
+#[doc = "`write(|w| ..)` method takes [`enable::W`](W) writer structure"]
+impl crate::Writable for EnableSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ENABLE to value 0"]
+impl crate::Resettable for EnableSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/fifo_clr.rs

@@ -0,0 +1,35 @@
+#[doc = "Register `FIFO_CLR` writer"]
+pub type W = crate::W<FifoClrSpec>;
+#[doc = "Field `RXFIFO` writer - Clear Rx FIFO"]
+pub type RxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TXFIFO` writer - Clear Tx FIFO"]
+pub type TxfifoW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clear Rx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn rxfifo(&mut self) -> RxfifoW<FifoClrSpec> {
+        RxfifoW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clear Tx FIFO"]
+    #[inline(always)]
+    #[must_use]
+    pub fn txfifo(&mut self) -> TxfifoW<FifoClrSpec> {
+        TxfifoW::new(self, 1)
+    }
+}
+#[doc = "Clear FIFO Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoClrSpec;
+impl crate::RegisterSpec for FifoClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
+impl crate::Writable for FifoClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIFO_CLR to value 0"]
+impl crate::Resettable for FifoClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/irq_enb.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `IRQ_RX` reader - RX Interrupt"]
+pub type IrqRxR = crate::BitReader;
+#[doc = "Field `IRQ_RX` writer - RX Interrupt"]
+pub type IrqRxW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_RX_STATUS` reader - RX Status Interrupt"]
+pub type IrqRxStatusR = crate::BitReader;
+#[doc = "Field `IRQ_RX_STATUS` writer - RX Status Interrupt"]
+pub type IrqRxStatusW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_RX_TO` reader - RX Timeout Interrupt"]
+pub type IrqRxToR = crate::BitReader;
+#[doc = "Field `IRQ_RX_TO` writer - RX Timeout Interrupt"]
+pub type IrqRxToW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_TX` reader - TX Interrupt"]
+pub type IrqTxR = crate::BitReader;
+#[doc = "Field `IRQ_TX` writer - TX Interrupt"]
+pub type IrqTxW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_TX_STATUS` reader - TX Status Interrupt"]
+pub type IrqTxStatusR = crate::BitReader;
+#[doc = "Field `IRQ_TX_STATUS` writer - TX Status Interrupt"]
+pub type IrqTxStatusW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_TX_EMPTY` reader - TX Empty Interrupt"]
+pub type IrqTxEmptyR = crate::BitReader;
+#[doc = "Field `IRQ_TX_EMPTY` writer - TX Empty Interrupt"]
+pub type IrqTxEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `IRQ_TX_CTS` reader - TX CTS Change Interrupt"]
+pub type IrqTxCtsR = crate::BitReader;
+#[doc = "Field `IRQ_TX_CTS` writer - TX CTS Change Interrupt"]
+pub type IrqTxCtsW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - RX Interrupt"]
+    #[inline(always)]
+    pub fn irq_rx(&self) -> IrqRxR {
+        IrqRxR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - RX Status Interrupt"]
+    #[inline(always)]
+    pub fn irq_rx_status(&self) -> IrqRxStatusR {
+        IrqRxStatusR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RX Timeout Interrupt"]
+    #[inline(always)]
+    pub fn irq_rx_to(&self) -> IrqRxToR {
+        IrqRxToR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 4 - TX Interrupt"]
+    #[inline(always)]
+    pub fn irq_tx(&self) -> IrqTxR {
+        IrqTxR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - TX Status Interrupt"]
+    #[inline(always)]
+    pub fn irq_tx_status(&self) -> IrqTxStatusR {
+        IrqTxStatusR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - TX Empty Interrupt"]
+    #[inline(always)]
+    pub fn irq_tx_empty(&self) -> IrqTxEmptyR {
+        IrqTxEmptyR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - TX CTS Change Interrupt"]
+    #[inline(always)]
+    pub fn irq_tx_cts(&self) -> IrqTxCtsR {
+        IrqTxCtsR::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - RX Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_rx(&mut self) -> IrqRxW<IrqEnbSpec> {
+        IrqRxW::new(self, 0)
+    }
+    #[doc = "Bit 1 - RX Status Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_rx_status(&mut self) -> IrqRxStatusW<IrqEnbSpec> {
+        IrqRxStatusW::new(self, 1)
+    }
+    #[doc = "Bit 2 - RX Timeout Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_rx_to(&mut self) -> IrqRxToW<IrqEnbSpec> {
+        IrqRxToW::new(self, 2)
+    }
+    #[doc = "Bit 4 - TX Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_tx(&mut self) -> IrqTxW<IrqEnbSpec> {
+        IrqTxW::new(self, 4)
+    }
+    #[doc = "Bit 5 - TX Status Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_tx_status(&mut self) -> IrqTxStatusW<IrqEnbSpec> {
+        IrqTxStatusW::new(self, 5)
+    }
+    #[doc = "Bit 6 - TX Empty Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_tx_empty(&mut self) -> IrqTxEmptyW<IrqEnbSpec> {
+        IrqTxEmptyW::new(self, 6)
+    }
+    #[doc = "Bit 7 - TX CTS Change Interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn irq_tx_cts(&mut self) -> IrqTxCtsW<IrqEnbSpec> {
+        IrqTxCtsW::new(self, 7)
+    }
+}
+#[doc = "IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0212_07e9"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0212_07e9;
+}

va416xx/src/uart0/rxfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `RXFIFOIRQTRG` reader"]
+pub type R = crate::R<RxfifoirqtrgSpec>;
+#[doc = "Register `RXFIFOIRQTRG` writer"]
+pub type W = crate::W<RxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Rx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxfifoirqtrgSpec;
+impl crate::RegisterSpec for RxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for RxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for RxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0"]
+impl crate::Resettable for RxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/rxfifortstrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `RXFIFORTSTRG` reader"]
+pub type R = crate::R<RxfifortstrgSpec>;
+#[doc = "Register `RXFIFORTSTRG` writer"]
+pub type W = crate::W<RxfifortstrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Rx FIFO RTS Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifortstrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifortstrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxfifortstrgSpec;
+impl crate::RegisterSpec for RxfifortstrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxfifortstrg::R`](R) reader structure"]
+impl crate::Readable for RxfifortstrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`rxfifortstrg::W`](W) writer structure"]
+impl crate::Writable for RxfifortstrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXFIFORTSTRG to value 0"]
+impl crate::Resettable for RxfifortstrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/rxstatus.rs

@@ -0,0 +1,92 @@
+#[doc = "Register `RXSTATUS` reader"]
+pub type R = crate::R<RxstatusSpec>;
+#[doc = "Field `RDAVL` reader - Read Data Available"]
+pub type RdavlR = crate::BitReader;
+#[doc = "Field `RDNFULL` reader - Read Fifo NOT Full"]
+pub type RdnfullR = crate::BitReader;
+#[doc = "Field `RXBUSY` reader - RX Busy Receiving"]
+pub type RxbusyR = crate::BitReader;
+#[doc = "Field `RXTO` reader - RX Receive Timeout"]
+pub type RxtoR = crate::BitReader;
+#[doc = "Field `RXOVR` reader - Read Fifo Overflow"]
+pub type RxovrR = crate::BitReader;
+#[doc = "Field `RXFRM` reader - RX Framing Error"]
+pub type RxfrmR = crate::BitReader;
+#[doc = "Field `RXPAR` reader - RX Parity Error"]
+pub type RxparR = crate::BitReader;
+#[doc = "Field `RXBRK` reader - RX Break Error"]
+pub type RxbrkR = crate::BitReader;
+#[doc = "Field `RXBUSYBRK` reader - RX Busy Receiving Break"]
+pub type RxbusybrkR = crate::BitReader;
+#[doc = "Field `RXADDR9` reader - Address Match for 9 bit mode"]
+pub type Rxaddr9R = crate::BitReader;
+#[doc = "Field `RXRTSN` reader - RX RTSn Output Value"]
+pub type RxrtsnR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Read Data Available"]
+    #[inline(always)]
+    pub fn rdavl(&self) -> RdavlR {
+        RdavlR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Read Fifo NOT Full"]
+    #[inline(always)]
+    pub fn rdnfull(&self) -> RdnfullR {
+        RdnfullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - RX Busy Receiving"]
+    #[inline(always)]
+    pub fn rxbusy(&self) -> RxbusyR {
+        RxbusyR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - RX Receive Timeout"]
+    #[inline(always)]
+    pub fn rxto(&self) -> RxtoR {
+        RxtoR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Read Fifo Overflow"]
+    #[inline(always)]
+    pub fn rxovr(&self) -> RxovrR {
+        RxovrR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - RX Framing Error"]
+    #[inline(always)]
+    pub fn rxfrm(&self) -> RxfrmR {
+        RxfrmR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - RX Parity Error"]
+    #[inline(always)]
+    pub fn rxpar(&self) -> RxparR {
+        RxparR::new(((self.bits >> 6) & 1) != 0)
+    }
+    #[doc = "Bit 7 - RX Break Error"]
+    #[inline(always)]
+    pub fn rxbrk(&self) -> RxbrkR {
+        RxbrkR::new(((self.bits >> 7) & 1) != 0)
+    }
+    #[doc = "Bit 8 - RX Busy Receiving Break"]
+    #[inline(always)]
+    pub fn rxbusybrk(&self) -> RxbusybrkR {
+        RxbusybrkR::new(((self.bits >> 8) & 1) != 0)
+    }
+    #[doc = "Bit 9 - Address Match for 9 bit mode"]
+    #[inline(always)]
+    pub fn rxaddr9(&self) -> Rxaddr9R {
+        Rxaddr9R::new(((self.bits >> 9) & 1) != 0)
+    }
+    #[doc = "Bit 15 - RX RTSn Output Value"]
+    #[inline(always)]
+    pub fn rxrtsn(&self) -> RxrtsnR {
+        RxrtsnR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxstatusSpec;
+impl crate::RegisterSpec for RxstatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxstatus::R`](R) reader structure"]
+impl crate::Readable for RxstatusSpec {}
+#[doc = "`reset()` method sets RXSTATUS to value 0"]
+impl crate::Resettable for RxstatusSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/state.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `STATE` reader"]
+pub type R = crate::R<StateSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Internal STATE of UART Controller\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`state::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StateSpec;
+impl crate::RegisterSpec for StateSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`state::R`](R) reader structure"]
+impl crate::Readable for StateSpec {}
+#[doc = "`reset()` method sets STATE to value 0"]
+impl crate::Resettable for StateSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/txbreak.rs

@@ -0,0 +1,23 @@
+#[doc = "Register `TXBREAK` writer"]
+pub type W = crate::W<TxbreakSpec>;
+impl core::fmt::Debug for crate::generic::Reg<TxbreakSpec> {
+    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
+        write!(f, "(not readable)")
+    }
+}
+impl W {}
+#[doc = "Break Transmit Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txbreak::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TxbreakSpec;
+impl crate::RegisterSpec for TxbreakSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`txbreak::W`](W) writer structure"]
+impl crate::Writable for TxbreakSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TXBREAK to value 0"]
+impl crate::Resettable for TxbreakSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/txfifoirqtrg.rs

@@ -0,0 +1,27 @@
+#[doc = "Register `TXFIFOIRQTRG` reader"]
+pub type R = crate::R<TxfifoirqtrgSpec>;
+#[doc = "Register `TXFIFOIRQTRG` writer"]
+pub type W = crate::W<TxfifoirqtrgSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+impl W {}
+#[doc = "Tx FIFO IRQ Trigger Level\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`txfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TxfifoirqtrgSpec;
+impl crate::RegisterSpec for TxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`txfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for TxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`txfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for TxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets TXFIFOIRQTRG to value 0"]
+impl crate::Resettable for TxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/uart0/txstatus.rs

@@ -0,0 +1,50 @@
+#[doc = "Register `TXSTATUS` reader"]
+pub type R = crate::R<TxstatusSpec>;
+#[doc = "Field `WRRDY` reader - Write Fifo NOT Full"]
+pub type WrrdyR = crate::BitReader;
+#[doc = "Field `WRBUSY` reader - Write Fifo Full"]
+pub type WrbusyR = crate::BitReader;
+#[doc = "Field `TXBUSY` reader - TX Busy Transmitting"]
+pub type TxbusyR = crate::BitReader;
+#[doc = "Field `WRLOST` reader - Write Data Lost (Fifo Overflow)"]
+pub type WrlostR = crate::BitReader;
+#[doc = "Field `TXCTSN` reader - TX CTSn Input Value"]
+pub type TxctsnR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Write Fifo NOT Full"]
+    #[inline(always)]
+    pub fn wrrdy(&self) -> WrrdyR {
+        WrrdyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Write Fifo Full"]
+    #[inline(always)]
+    pub fn wrbusy(&self) -> WrbusyR {
+        WrbusyR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - TX Busy Transmitting"]
+    #[inline(always)]
+    pub fn txbusy(&self) -> TxbusyR {
+        TxbusyR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Write Data Lost (Fifo Overflow)"]
+    #[inline(always)]
+    pub fn wrlost(&self) -> WrlostR {
+        WrlostR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 15 - TX CTSn Input Value"]
+    #[inline(always)]
+    pub fn txctsn(&self) -> TxctsnR {
+        TxctsnR::new(((self.bits >> 15) & 1) != 0)
+    }
+}
+#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`txstatus::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct TxstatusSpec;
+impl crate::RegisterSpec for TxstatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`txstatus::R`](R) reader structure"]
+impl crate::Readable for TxstatusSpec {}
+#[doc = "`reset()` method sets TXSTATUS to value 0"]
+impl crate::Resettable for TxstatusSpec {
+    const RESET_VALUE: u32 = 0;
+}