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12
README.md
12
README.md
@ -14,7 +14,7 @@ This workspace contains the following crates:
|
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PAC crate containing basic low-level register definition
|
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- The [`va416xx-hal`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-hal)
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HAL crate containing higher-level abstractions on top of the PAC register crate.
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- The [`va416xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va108xx-embassy)
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- The [`va416xx-embassy`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx-embassy)
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crate containing support for running the embassy-rs RTOS.
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- The [`vorago-peb1`](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/vorago-peb1)
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BSP crate containing support for the PEB1 development board.
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@ -155,3 +155,13 @@ example.
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The Segger RTT viewer can be used to display log messages received from the target. The base
|
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address for the RTT block placement is 0x1fff8000. It is recommended to use a search range of
|
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0x1000 around that base address when using the RTT viewer.
|
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|
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## Learning (Embedded) Rust
|
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|
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If you are unfamiliar with Rust on Embedded Systems or Rust in general, the following resources
|
||||
are recommended:
|
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|
||||
- [Rust Book](https://doc.rust-lang.org/book/)
|
||||
- [Embedded Rust Book](https://docs.rust-embedded.org/book/)
|
||||
- [Embedded Rust Discovery](https://docs.rust-embedded.org/discovery/microbit/)
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||||
- [Awesome Embedded Rust](https://github.com/rust-embedded/awesome-embedded-rust)
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@ -7,14 +7,14 @@ edition = "2021"
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cortex-m = "0.7"
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cortex-m-rt = "0.7"
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embedded-hal = "1"
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panic-rtt-target = { version = "0.1.3" }
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panic-halt = { version = "0.2" }
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rtt-target = { version = "0.5" }
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panic-rtt-target = { version = "0.2" }
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panic-halt = { version = "1" }
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rtt-target = { version = "0.6" }
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crc = "3"
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static_assertions = "1"
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[dependencies.va416xx-hal]
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path = "../va416xx-hal"
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version = "0.5"
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features = ["va41630"]
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[features]
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@ -12,9 +12,9 @@ embedded-io = "0.6"
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embedded-hal-async = "1"
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embedded-io-async = "0.6"
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rtt-target = { version = "0.5" }
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rtt-target = { version = "0.6" }
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heapless = "0.8"
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panic-rtt-target = { version = "0.1" }
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panic-rtt-target = { version = "0.2" }
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static_cell = "2"
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critical-section = "1"
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once_cell = { version = "1", default-features = false, features = ["critical-section"] }
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@ -28,11 +28,8 @@ embassy-executor = { version = "0.7", features = [
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"executor-interrupt"
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]}
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va416xx-embassy = { path = "../../va416xx-embassy", default-features = false }
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[dependencies.va416xx-hal]
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path = "../../va416xx-hal"
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features = ["va41630"]
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va416xx-hal = { version = "0.5" }
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va416xx-embassy = { version = "0.1", default-features = false }
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[features]
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default = ["ticks-hz-1_000", "va416xx-embassy/irq-tim14-tim15"]
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@ -132,7 +132,7 @@ fn UART0_RX() {
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RX.lock(|static_rx| {
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let mut rx_borrow = static_rx.borrow_mut();
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let rx_mut_ref = rx_borrow.as_mut().unwrap();
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let result = rx_mut_ref.irq_handler(&mut buf);
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let result = rx_mut_ref.on_interrupt(&mut buf);
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read_len = result.bytes_read;
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if result.errors.is_some() {
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errors = result.errors;
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@ -7,13 +7,11 @@ edition = "2021"
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cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
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cortex-m-rt = "0.7"
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embedded-hal = "1"
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rtt-target = { version = "0.5" }
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rtt-target = { version = "0.6" }
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rtic-sync = { version = "1.3", features = ["defmt-03"] }
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panic-rtt-target = { version = "0.1.3" }
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panic-rtt-target = { version = "0.2" }
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|
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[dependencies.va416xx-hal]
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path = "../../va416xx-hal"
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features = ["va41630"]
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va416xx-hal = { version = "0.5", features = ["va41630"] }
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[dependencies.rtic]
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version = "2"
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|
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@ -7,17 +7,16 @@ edition = "2021"
|
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cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
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cortex-m-rt = "0.7"
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critical-section = "1"
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panic-rtt-target = { version = "0.1.3" }
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rtt-target = { version = "0.5" }
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panic-rtt-target = { version = "0.2" }
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rtt-target = { version = "0.6" }
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embedded-hal = "1"
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embedded-hal-nb = "1"
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nb = "1"
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embedded-io = "0.6"
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panic-halt = "0.2"
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panic-halt = "1"
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accelerometer = "0.12"
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[dependencies.va416xx-hal]
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path = "../../va416xx-hal"
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va416xx-hal = { version = "0.5", features = ["va41630"] }
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[dependencies.vorago-peb1]
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path = "../../vorago-peb1"
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@ -9,44 +9,20 @@ cortex-m-rt = "0.7"
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embedded-hal = "1"
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embedded-hal-nb = "1"
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embedded-io = "0.6"
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panic-rtt-target = { version = "0.1.3" }
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rtt-target = { version = "0.5" }
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rtt-log = "0.3"
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panic-rtt-target = { version = "0.2" }
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rtt-target = { version = "0.6" }
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rtt-log = "0.5"
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log = "0.4"
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crc = "3"
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rtic-sync = "1"
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static_cell = "2"
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satrs = { version = "0.3.0-alpha.0", default-features = false }
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ringbuf = { version = "0.4", default-features = false }
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once_cell = { version = "1", default-features = false, features = ["critical-section"] }
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spacepackets = { version = "0.13", default-features = false }
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cobs = { version = "0.3", default-features = false }
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|
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[dependencies.satrs]
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version = "0.2"
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default-features = false
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va416xx-hal = { version = "0.5", features = ["va41630"] }
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[dependencies.ringbuf]
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version = "0.4"
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default-features = false
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|
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[dependencies.once_cell]
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version = "1"
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default-features = false
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features = ["critical-section"]
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[dependencies.spacepackets]
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version = "0.11"
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default-features = false
|
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|
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[dependencies.cobs]
|
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git = "https://github.com/robamu/cobs.rs.git"
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branch = "all_features"
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default-features = false
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|
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[dependencies.va416xx-hal]
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path = "../va416xx-hal"
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features = ["va41630"]
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[dependencies.rtic]
|
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version = "2"
|
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features = ["thumbv7-backend"]
|
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|
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[dependencies.rtic-monotonics]
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version = "2"
|
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features = ["cortex-m-systick"]
|
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rtic = { version = "2", features = ["thumbv7-backend"] }
|
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rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
|
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|
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@ -11,7 +11,7 @@ panic-rtt-target = { version = "0.1.3" }
|
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rtt-target = { version = "0.5" }
|
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cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
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embedded-hal = "1"
|
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va416xx-hal = { path = "../../va416xx-hal", features = ["va41630"] }
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va416xx-hal = { path = "0.4", features = ["va41630"] }
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|
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[profile.dev]
|
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codegen-units = 1
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@ -11,7 +11,7 @@ panic-rtt-target = { version = "0.1.3" }
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rtt-target = { version = "0.5" }
|
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cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
|
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embedded-hal = "1"
|
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va416xx-hal = { path = "../../va416xx-hal", features = ["va41630"] }
|
||||
va416xx-hal = { path = "0.4", features = ["va41630"] }
|
||||
|
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[profile.dev]
|
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codegen-units = 1
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|
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@ -256,7 +256,7 @@ mod app {
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match cx
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.local
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.uart_rx
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.irq_handler_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
|
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.on_interrupt_max_size_or_timeout_based(cx.local.rx_context, cx.local.rx_buf)
|
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{
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Ok(result) => {
|
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if RX_DEBUGGING {
|
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|
||||
@ -8,6 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
||||
|
||||
## [unreleased]
|
||||
|
||||
## [v0.1.0] 2025-02-13
|
||||
## [v0.1.1] 2025-03-07
|
||||
|
||||
- Bumped allowed HAL dependency to v0.5
|
||||
|
||||
## [v0.1.0] 2025-02-18
|
||||
|
||||
Initial release
|
||||
|
||||
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-embassy-v0.1.1...HEAD
|
||||
[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-embassy-v0.1.0...va416xx-embassy-v0.1.1
|
||||
[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/va416xx-embassy-v0.1.0
|
||||
|
||||
@ -1,6 +1,6 @@
|
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[package]
|
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name = "va416xx-embassy"
|
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version = "0.1.0"
|
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version = "0.1.1"
|
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edition = "2021"
|
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authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
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description = "Embassy-rs support for the Vorago VA416xx family of microcontrollers"
|
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@ -21,17 +21,20 @@ portable-atomic = "1"
|
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|
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once_cell = { version = "1", default-features = false, features = ["critical-section"] }
|
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|
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va416xx-hal = { version = "0.4", path = "../va416xx-hal" }
|
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va416xx-hal = { version = ">=0.4, <=0.5" }
|
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|
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[features]
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default = ["irq-tim14-tim15"]
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irqs-in-lib = []
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|
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# This determines the reserved interrupt functions for the embassy time drivers. Only one
|
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# is allowed to be selected!
|
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irq-tim14-tim15 = ["irqs-in-lib"]
|
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irq-tim13-tim14 = ["irqs-in-lib"]
|
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irq-tim14-tim15 = ["_irqs-in-lib"]
|
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irq-tim13-tim14 = ["_irqs-in-lib"]
|
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# These TIMs are clocked slower!
|
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irq-tim22-tim23 = ["irqs-in-lib"]
|
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irq-tim22-tim23 = ["_irqs-in-lib"]
|
||||
|
||||
# Private feature.
|
||||
_irqs-in-lib = []
|
||||
|
||||
[package.metadata.docs.rs]
|
||||
rustdoc-args = ["--generate-link-to-definition"]
|
||||
|
||||
@ -136,13 +136,13 @@ pub unsafe fn init<
|
||||
alarm: AlarmTim,
|
||||
clocks: &Clocks,
|
||||
) {
|
||||
#[cfg(feature = "irqs-in-lib")]
|
||||
#[cfg(feature = "_irqs-in-lib")]
|
||||
assert_eq!(
|
||||
TimekeeperTim::ID,
|
||||
TIMEKEEPER_IRQ as u8 - TIM_IRQ_OFFSET as u8,
|
||||
"Timekeeper TIM and IRQ missmatch"
|
||||
);
|
||||
#[cfg(feature = "irqs-in-lib")]
|
||||
#[cfg(feature = "_irqs-in-lib")]
|
||||
assert_eq!(
|
||||
AlarmTim::ID,
|
||||
ALARM_IRQ as u8 - TIM_IRQ_OFFSET as u8,
|
||||
|
||||
@ -8,6 +8,27 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
||||
|
||||
# [unreleased]
|
||||
|
||||
# [v0.5.1] 2025-03-10
|
||||
|
||||
## Fixed
|
||||
|
||||
- Fix `embedded_io` UART implementation to implement the documented contract properly.
|
||||
The implementation will now block until at least one byte is available or can be written, unless
|
||||
the send or receive buffer is empty.
|
||||
|
||||
# [v0.5.0] 2025-03-07
|
||||
|
||||
- Bugfix for I2C `TimingCfg::reg`
|
||||
- Simplified UART error handling. All APIs are now infallible because writing to a FIFO or
|
||||
reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or
|
||||
`Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided
|
||||
interrupt handlers.
|
||||
|
||||
# [v0.4.1] 2025-02-18
|
||||
|
||||
- Chip selection is not enforced anymore, but advised through documentation. This makes using
|
||||
the HAL in libraries a lot easier.
|
||||
|
||||
# [v0.4.0] 2025-02-18
|
||||
|
||||
## Changed
|
||||
@ -96,3 +117,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
||||
# [v0.1.0] 2024-07-01
|
||||
|
||||
- Initial release with basic HAL drivers
|
||||
|
||||
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.5.0...HEAD
|
||||
[v0.5.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.5.0...va416xx-hal-v0.5.1
|
||||
[v0.5.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.4.1...va416xx-hal-v0.5.0
|
||||
[v0.4.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.4.0...va416xx-hal-v0.4.1
|
||||
[v0.4.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.3.0...va416xx-hal-v0.4.0
|
||||
[v0.3.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.2.0...va108xx-hal-v0.3.0
|
||||
[v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/va416xx-hal-v0.1.0...va108xx-hal-v0.2.0
|
||||
[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/va416xx-hal-v0.1.0
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
[package]
|
||||
name = "va416xx-hal"
|
||||
version = "0.4.0"
|
||||
version = "0.5.1"
|
||||
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
||||
edition = "2021"
|
||||
description = "HAL for the Vorago VA416xx family of MCUs"
|
||||
@ -23,9 +23,9 @@ embedded-io-async = "0.6"
|
||||
num_enum = { version = "0.7", default-features = false }
|
||||
typenum = "1"
|
||||
bitflags = "2"
|
||||
bitfield = "0.17"
|
||||
bitfield = { version = ">=0.17, <=0.18"}
|
||||
fugit = "0.3"
|
||||
delegate = "0.12"
|
||||
delegate = ">=0.12, <=0.13"
|
||||
heapless = "0.8"
|
||||
void = { version = "1", default-features = false }
|
||||
thiserror = { version = "2", default-features = false }
|
||||
|
||||
@ -11,14 +11,17 @@ raw PAC. This crate also implements traits specified by the
|
||||
[embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
|
||||
various drivers in the embedded rust ecosystem.
|
||||
|
||||
You have to enable one of the following device features to use this crate depending on
|
||||
which chip you are using:
|
||||
It is generally advised to enable ONE of the following device features to use this crate
|
||||
depending on which chip you are using:
|
||||
|
||||
- `va41630`
|
||||
- `va41629`
|
||||
- `va41628`
|
||||
- `va41620`
|
||||
|
||||
If no chip is specified, only access to APIs which are common for all families or
|
||||
which are not disabled for specific families is granted.
|
||||
|
||||
## Building
|
||||
|
||||
Building an application requires the `thumbv7em-none-eabihf` cross-compiler toolchain.
|
||||
|
||||
@ -212,13 +212,13 @@ impl TimingCfg {
|
||||
}
|
||||
|
||||
pub fn reg(&self) -> u32 {
|
||||
(self.tbuf as u32) << 28
|
||||
| (self.thd_sta as u32) << 24
|
||||
| (self.tsu_sta as u32) << 20
|
||||
| (self.tsu_sto as u32) << 16
|
||||
| (self.tlow as u32) << 12
|
||||
| (self.thigh as u32) << 8
|
||||
| (self.tf as u32) << 4
|
||||
((self.tbuf as u32) << 28)
|
||||
| ((self.thd_sta as u32) << 24)
|
||||
| ((self.tsu_sta as u32) << 20)
|
||||
| ((self.tsu_sto as u32) << 16)
|
||||
| ((self.tlow as u32) << 12)
|
||||
| ((self.thigh as u32) << 8)
|
||||
| ((self.tf as u32) << 4)
|
||||
| (self.tr as u32)
|
||||
}
|
||||
}
|
||||
@ -390,7 +390,7 @@ impl<I2c: Instance> I2cBase<I2c> {
|
||||
if let Some(max_words) = max_words {
|
||||
self.i2c
|
||||
.s0_maxwords()
|
||||
.write(|w| unsafe { w.bits(1 << 31 | max_words as u32) });
|
||||
.write(|w| unsafe { w.bits((1 << 31) | max_words as u32) });
|
||||
}
|
||||
let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr);
|
||||
// The first bit is the read/write value. Normally, both read and write are matched
|
||||
@ -451,7 +451,7 @@ impl<I2c: Instance> I2cBase<I2c> {
|
||||
let clk_div = self.calc_clk_div(speed_mode)?;
|
||||
self.i2c
|
||||
.clkscale()
|
||||
.write(|w| unsafe { w.bits((speed_mode as u32) << 31 | clk_div as u32) });
|
||||
.write(|w| unsafe { w.bits(((speed_mode as u32) << 31) | clk_div as u32) });
|
||||
Ok(())
|
||||
}
|
||||
|
||||
|
||||
@ -1,20 +1,23 @@
|
||||
//! This is the **H**ardware **A**bstraction **L**ayer (HAL) for the VA416xx MCU family.
|
||||
//!
|
||||
//! It is an additional hardware abstraction on top of the [peripheral access API](https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/branch/main/va416xx).
|
||||
|
||||
//!
|
||||
//! It is the result of reading the datasheet for the device and encoding a type-safe layer over the
|
||||
//! raw PAC. This crate also implements traits specified by the
|
||||
//! [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
|
||||
//! various drivers in the embedded rust ecosystem.
|
||||
|
||||
//! You have to enable one of the following device features to use this crate depending on
|
||||
//! which chip you are using:
|
||||
|
||||
//!
|
||||
//! It is generally advised to enable ONE of the following device features to use this crate
|
||||
//! depending on which chip you are using:
|
||||
//!
|
||||
//! - `va41630`
|
||||
//! - `va41629`
|
||||
//! - `va41628`
|
||||
//! - `va41620`
|
||||
//!
|
||||
//! If no option is specified, only access to APIs which are common for all families or
|
||||
//! which are not disabled for specific families is granted.
|
||||
//!
|
||||
//! When using this HAL and writing applications for the VA416xx family in general, it is strongly
|
||||
//! recommended that you set up the clock properly, because the default internal HBO clock
|
||||
//! is not very accurate. You can use the [crate::clock] module for this. If you are working
|
||||
@ -26,15 +29,6 @@
|
||||
#[cfg(test)]
|
||||
extern crate std;
|
||||
|
||||
#[cfg(not(feature = "device-selected"))]
|
||||
compile_error!(
|
||||
"This crate requires one of the following device features enabled:
|
||||
va41630
|
||||
va41629
|
||||
va41628
|
||||
"
|
||||
);
|
||||
|
||||
use gpio::Port;
|
||||
pub use va416xx as device;
|
||||
pub use va416xx as pac;
|
||||
|
||||
@ -82,56 +82,6 @@ impl RxPin<Uart2> for Pin<PF9, AltFunc1> {}
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub struct TransferPendingError;
|
||||
|
||||
#[derive(Debug, PartialEq, Eq)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub enum RxError {
|
||||
Overrun,
|
||||
Framing,
|
||||
Parity,
|
||||
}
|
||||
#[derive(Debug, PartialEq, Eq)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub enum Error {
|
||||
Rx(RxError),
|
||||
BreakCondition,
|
||||
}
|
||||
|
||||
impl From<RxError> for Error {
|
||||
fn from(value: RxError) -> Self {
|
||||
Self::Rx(value)
|
||||
}
|
||||
}
|
||||
|
||||
impl embedded_io::Error for Error {
|
||||
fn kind(&self) -> embedded_io::ErrorKind {
|
||||
embedded_io::ErrorKind::Other
|
||||
}
|
||||
}
|
||||
|
||||
impl embedded_io::Error for RxError {
|
||||
fn kind(&self) -> embedded_io::ErrorKind {
|
||||
embedded_io::ErrorKind::Other
|
||||
}
|
||||
}
|
||||
impl embedded_hal_nb::serial::Error for RxError {
|
||||
fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
|
||||
match self {
|
||||
RxError::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
|
||||
RxError::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
|
||||
RxError::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl embedded_hal_nb::serial::Error for Error {
|
||||
fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
|
||||
match self {
|
||||
Error::Rx(rx_error) => embedded_hal_nb::serial::Error::kind(rx_error),
|
||||
Error::BreakCondition => embedded_hal_nb::serial::ErrorKind::Other,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, PartialEq, Eq, Copy, Clone)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub enum Event {
|
||||
@ -626,22 +576,27 @@ impl<Uart: Instance> UartBase<Uart> {
|
||||
self.uart
|
||||
}
|
||||
|
||||
/// Poll receiver errors.
|
||||
pub fn poll_rx_errors(&self) -> Option<UartErrors> {
|
||||
self.rx.poll_errors()
|
||||
}
|
||||
|
||||
pub fn split(self) -> (Tx<Uart>, Rx<Uart>) {
|
||||
(self.tx, self.rx)
|
||||
}
|
||||
}
|
||||
|
||||
impl<UartInstance> embedded_io::ErrorType for UartBase<UartInstance> {
|
||||
type Error = Error;
|
||||
type Error = Infallible;
|
||||
}
|
||||
|
||||
impl<UartInstance> embedded_hal_nb::serial::ErrorType for UartBase<UartInstance> {
|
||||
type Error = Error;
|
||||
type Error = Infallible;
|
||||
}
|
||||
|
||||
impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for UartBase<Uart> {
|
||||
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
||||
self.rx.read().map_err(|e| e.map(Error::Rx))
|
||||
self.rx.read()
|
||||
}
|
||||
}
|
||||
|
||||
@ -729,6 +684,8 @@ impl<TxPinInst: TxPin<UartInstance>, RxPinInst: RxPin<UartInstance>, UartInstanc
|
||||
|
||||
delegate::delegate! {
|
||||
to self.inner {
|
||||
/// Poll receiver errors.
|
||||
pub fn poll_rx_errors(&self) -> Option<UartErrors>;
|
||||
#[inline]
|
||||
pub fn enable_rx(&mut self);
|
||||
#[inline]
|
||||
@ -813,6 +770,23 @@ impl<Uart: Instance> Rx<Uart> {
|
||||
&self.0
|
||||
}
|
||||
|
||||
pub fn poll_errors(&self) -> Option<UartErrors> {
|
||||
let mut errors = UartErrors::default();
|
||||
|
||||
let uart = unsafe { &(*Uart::ptr()) };
|
||||
let status_reader = uart.rxstatus().read();
|
||||
if status_reader.rxovr().bit_is_set() {
|
||||
errors.overflow = true;
|
||||
} else if status_reader.rxfrm().bit_is_set() {
|
||||
errors.framing = true;
|
||||
} else if status_reader.rxpar().bit_is_set() {
|
||||
errors.parity = true;
|
||||
} else {
|
||||
return None;
|
||||
};
|
||||
Some(errors)
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_fifo(&self) {
|
||||
self.0.fifo_clr().write(|w| w.rxfifo().set_bit());
|
||||
@ -874,34 +848,15 @@ impl<Uart: Instance> Rx<Uart> {
|
||||
}
|
||||
|
||||
impl<Uart> embedded_io::ErrorType for Rx<Uart> {
|
||||
type Error = RxError;
|
||||
type Error = Infallible;
|
||||
}
|
||||
|
||||
impl<Uart> embedded_hal_nb::serial::ErrorType for Rx<Uart> {
|
||||
type Error = RxError;
|
||||
type Error = Infallible;
|
||||
}
|
||||
|
||||
impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for Rx<Uart> {
|
||||
fn read(&mut self) -> nb::Result<u8, Self::Error> {
|
||||
let uart = unsafe { &(*Uart::ptr()) };
|
||||
let status_reader = uart.rxstatus().read();
|
||||
let err = if status_reader.rxovr().bit_is_set() {
|
||||
Some(RxError::Overrun)
|
||||
} else if status_reader.rxfrm().bit_is_set() {
|
||||
Some(RxError::Framing)
|
||||
} else if status_reader.rxpar().bit_is_set() {
|
||||
Some(RxError::Parity)
|
||||
} else {
|
||||
None
|
||||
};
|
||||
if let Some(err) = err {
|
||||
// The status code is always related to the next bit for the framing
|
||||
// and parity status bits. We have to read the DATA register
|
||||
// so that the next status reflects the next DATA word
|
||||
// For overrun error, we read as well to clear the peripheral
|
||||
self.read_fifo_unchecked();
|
||||
return Err(err.into());
|
||||
}
|
||||
self.read_fifo().map(|val| (val & 0xff) as u8).map_err(|e| {
|
||||
if let nb::Error::Other(_) = e {
|
||||
unreachable!()
|
||||
@ -916,13 +871,23 @@ impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
|
||||
if buf.is_empty() {
|
||||
return Ok(0);
|
||||
}
|
||||
|
||||
let mut read = 0;
|
||||
loop {
|
||||
if self.0.rxstatus().read().rdavl().bit_is_set() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
for byte in buf.iter_mut() {
|
||||
let w = nb::block!(<Self as embedded_hal_nb::serial::Read<u8>>::read(self))?;
|
||||
*byte = w;
|
||||
match <Self as embedded_hal_nb::serial::Read<u8>>::read(self) {
|
||||
Ok(w) => {
|
||||
*byte = w;
|
||||
read += 1;
|
||||
}
|
||||
Err(nb::Error::WouldBlock) => break,
|
||||
}
|
||||
}
|
||||
|
||||
Ok(buf.len())
|
||||
Ok(read)
|
||||
}
|
||||
}
|
||||
|
||||
@ -1081,14 +1046,19 @@ impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
|
||||
if buf.is_empty() {
|
||||
return Ok(0);
|
||||
}
|
||||
|
||||
for byte in buf.iter() {
|
||||
nb::block!(<Self as embedded_hal_nb::serial::Write<u8>>::write(
|
||||
self, *byte
|
||||
))?;
|
||||
loop {
|
||||
if self.0.txstatus().read().wrrdy().bit_is_set() {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
Ok(buf.len())
|
||||
let mut written = 0;
|
||||
for byte in buf.iter() {
|
||||
match <Self as embedded_hal_nb::serial::Write<u8>>::write(self, *byte) {
|
||||
Ok(_) => written += 1,
|
||||
Err(nb::Error::WouldBlock) => return Ok(written),
|
||||
}
|
||||
}
|
||||
Ok(written)
|
||||
}
|
||||
|
||||
fn flush(&mut self) -> Result<(), Self::Error> {
|
||||
@ -1182,7 +1152,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
|
||||
/// This function will not disable the RX interrupts, so you don't need to call any other
|
||||
/// API after calling this function to continue emptying the FIFO. RX errors are handled
|
||||
/// as partial errors and are returned as part of the [IrqResult].
|
||||
pub fn irq_handler(&mut self, buf: &mut [u8; 16]) -> IrqResult {
|
||||
pub fn on_interrupt(&mut self, buf: &mut [u8; 16]) -> IrqResult {
|
||||
let mut result = IrqResult::default();
|
||||
|
||||
let irq_end = self.uart().irq_end().read();
|
||||
@ -1203,15 +1173,10 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
|
||||
|
||||
// Timeout, empty the FIFO completely.
|
||||
if irq_end.irq_rx_to().bit_is_set() {
|
||||
loop {
|
||||
// While there is data in the FIFO, write it into the reception buffer
|
||||
let read_result = self.0.read();
|
||||
if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
|
||||
buf[result.bytes_read] = byte;
|
||||
result.bytes_read += 1;
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
// While there is data in the FIFO, write it into the reception buffer
|
||||
while let Ok(byte) = self.0.read_fifo() {
|
||||
buf[result.bytes_read] = byte as u8;
|
||||
result.bytes_read += 1;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1239,7 +1204,7 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
|
||||
/// If passed buffer is equal to or larger than the specified maximum length, an
|
||||
/// [BufferTooShortError] will be returned. Other RX errors are treated as partial errors
|
||||
/// and returned inside the [IrqResultMaxSizeOrTimeout] structure.
|
||||
pub fn irq_handler_max_size_or_timeout_based(
|
||||
pub fn on_interrupt_max_size_or_timeout_based(
|
||||
&mut self,
|
||||
context: &mut IrqContextTimeoutOrMaxSize,
|
||||
buf: &mut [u8],
|
||||
@ -1288,12 +1253,13 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
|
||||
if context.rx_idx == context.max_len {
|
||||
break;
|
||||
}
|
||||
let read_result = self.0.read();
|
||||
if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
|
||||
buf[context.rx_idx] = byte;
|
||||
context.rx_idx += 1;
|
||||
} else {
|
||||
break;
|
||||
// While there is data in the FIFO, write it into the reception buffer
|
||||
match self.0.read() {
|
||||
Ok(byte) => {
|
||||
buf[result.bytes_read] = byte;
|
||||
result.bytes_read += 1;
|
||||
}
|
||||
Err(_) => break,
|
||||
}
|
||||
}
|
||||
self.irq_completion_handler_max_size_timeout(&mut result, context);
|
||||
@ -1312,29 +1278,6 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
|
||||
Ok(result)
|
||||
}
|
||||
|
||||
fn read_handler(
|
||||
&self,
|
||||
errors: &mut Option<UartErrors>,
|
||||
read_res: &nb::Result<u8, RxError>,
|
||||
) -> Option<u8> {
|
||||
match read_res {
|
||||
Ok(byte) => Some(*byte),
|
||||
Err(nb::Error::WouldBlock) => None,
|
||||
Err(nb::Error::Other(e)) => {
|
||||
// Ensure `errors` is Some(IrqUartError), initializing if it's None
|
||||
let err = errors.get_or_insert(UartErrors::default());
|
||||
|
||||
// Now we can safely modify fields inside `err`
|
||||
match e {
|
||||
RxError::Overrun => err.overflow = true,
|
||||
RxError::Framing => err.framing = true,
|
||||
RxError::Parity => err.parity = true,
|
||||
}
|
||||
None
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn check_for_errors(&self, errors: &mut Option<UartErrors>) {
|
||||
let rx_status = self.uart().rxstatus().read();
|
||||
|
||||
|
||||
@ -28,7 +28,7 @@ use va416xx::uart0 as uart_base;
|
||||
|
||||
use crate::enable_nvic_interrupt;
|
||||
|
||||
use super::{Bank, Instance, Rx, RxError, UartErrors};
|
||||
use super::{Bank, Instance, Rx, UartErrors};
|
||||
|
||||
static UART_RX_WAKERS: [AtomicWaker; 3] = [const { AtomicWaker::new() }; 3];
|
||||
static RX_READ_ACTIVE: [AtomicBool; 3] = [const { AtomicBool::new(false) }; 3];
|
||||
@ -48,7 +48,7 @@ impl RxFuture {
|
||||
}
|
||||
|
||||
impl Future for RxFuture {
|
||||
type Output = Result<(), RxError>;
|
||||
type Output = Result<(), Infallible>;
|
||||
|
||||
fn poll(
|
||||
self: core::pin::Pin<&mut Self>,
|
||||
|
||||
@ -8,6 +8,19 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
||||
|
||||
# [unreleased]
|
||||
|
||||
# [v0.1.2] 2025-03-07
|
||||
|
||||
- Bump allowed HAL version to v0.5
|
||||
|
||||
# [v0.1.1] 2025-02-18
|
||||
|
||||
- Bump allowed HAL version to v0.4
|
||||
|
||||
# [v0.1.0] 2024-10-01
|
||||
|
||||
- Initial release
|
||||
|
||||
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.2...HEAD
|
||||
[v0.1.2]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.1...vorago-peb1-v0.1.2
|
||||
[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/compare/vorago-peb1-v0.1.0...vorago-peb1-v0.1.1
|
||||
[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/va416xx-rs/src/tag/vorago-peb1-v0.1.0
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
[package]
|
||||
name = "vorago-peb1"
|
||||
version = "0.1.0"
|
||||
version = "0.1.2"
|
||||
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
||||
edition = "2021"
|
||||
description = "Board Support Crate for the Vorago PEB1 development board"
|
||||
@ -14,15 +14,9 @@ categories = ["embedded", "no-std", "hardware-support"]
|
||||
cortex-m = "0.7"
|
||||
cortex-m-rt = "0.7"
|
||||
embedded-hal = "1"
|
||||
lis2dh12 = { version = "0.7", features = ["out_f32"] }
|
||||
|
||||
[dependencies.va416xx-hal]
|
||||
path = "../va416xx-hal"
|
||||
features = ["va41630"]
|
||||
version = ">=0.3, <=0.4"
|
||||
|
||||
[dependencies.lis2dh12]
|
||||
version = "0.7"
|
||||
features = ["out_f32"]
|
||||
va416xx-hal = { version = ">=0.3, <=0.5", features = ["va41630"] }
|
||||
|
||||
[features]
|
||||
rt = ["va416xx-hal/rt"]
|
||||
|
||||
Reference in New Issue
Block a user