some form changes
Rust/vorago-reb1/pipeline/head There was a failure building this commit Details
Rust/vorago-reb1/pipeline/pr-main There was a failure building this commit Details

This commit is contained in:
Robin Müller 2021-12-12 14:42:35 +01:00
parent a912dd3971
commit a2a824cfcf
No known key found for this signature in database
GPG Key ID: 71B58F8A3CDFA9AC
2 changed files with 2 additions and 9 deletions

View File

@ -14,7 +14,6 @@ use va108xx_hal::{
prelude::*,
spi::{Spi, SpiBase, SpiConfig, TransferConfig},
timer::{default_ms_irq_handler, set_up_ms_timer, Delay},
utility::*,
};
use vorago_reb1::max11619::{
max11619_externally_clocked, max11619_internally_clocked, EocPin, AN2_CHANNEL,
@ -56,18 +55,13 @@ fn main() -> ! {
}
let pinsa = PinsA::new(&mut dp.SYSCONFIG, None, dp.PORTA);
let mut spi_cfg = SpiConfig::default();
spi_cfg.scrdv = 0x07;
let spi_cfg = SpiConfig::default();
let (sck, mosi, miso) = (
pinsa.pa20.into_funsel_2(),
pinsa.pa19.into_funsel_2(),
pinsa.pa18.into_funsel_2(),
);
port_mux(&mut dp.IOCONFIG, PortSel::PortB, 16, Funsel::Funsel1).ok();
// port_mux(&mut dp.IOCONFIG, PortSel::PortB, 17, Funsel::Funsel1).ok();
port_mux(&mut dp.IOCONFIG, PortSel::PortB, 18, Funsel::Funsel1).ok();
port_mux(&mut dp.IOCONFIG, PortSel::PortB, 19, Funsel::Funsel1).ok();
// Set the accelerometer chip select low in case the board slot is populated
let mut accel_cs = pinsa.pa16.into_push_pull_output();
accel_cs

View File

@ -1,9 +1,8 @@
use embedded_hal::{blocking::spi::Transfer, spi::FullDuplex};
use max116xx_10bit::{
Error, ExternallyClocked, InternallyClockedInternallyTimedSerialInterface, Max11619,
Max116xx10Bit, RefMode, WithoutWakeupDelay,
};
use embedded_hal::blocking::spi::Transfer;
use embedded_hal::spi::FullDuplex;
use va108xx_hal::gpio::{Floating, Input, Pin, PA14};
pub type Max11619ExternallyClocked<SPI> =