invert Pull enum

2026-05-18 20:25:28 +02:00
parent 682655c036
commit c1b2511508
2 changed files with 4 additions and 3 deletions
@@ -26,6 +26,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ### Fixed

+- `Pull::Up` and `Pull::High` were inverted.
 - Removed HW CS pin provider implementation for PA23, PA22 and PA21, which are multi HW CS pins.
 - Added missing `AnyPin` trait impl for Multi HW CS pins.
 - Expose inner `Input` pin for `InputPinAsync`.
@@ -55,4 +56,4 @@ Init commit.

 [unreleased]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.2.0...HEAD
 [v0.2.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/compare/v0.1.0...v0.2.0
-[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal/src/tag/v0.1.0
+[v0.1.0]: https://egit.irs.u ni-stuttgart.de/rust/vorago-shared-hal/src/tag/v0.1.0
@@ -39,8 +39,8 @@ pub enum FilterClockSelect {
 #[bitbybit::bitenum(u1, exhaustive = true)]
 #[cfg_attr(feature = "defmt", derive(defmt::Format))]
 pub enum Pull {
-    Up = 0,
-    Down = 1,
+    Down = 0,
+    Up = 1,
 }

 #[derive(Debug, Eq, PartialEq)]