changelog

2026-05-19 18:29:15 +02:00
parent b510d2f0b2
commit ed2891bbf2
1 changed files with 6 additions and 0 deletions
@@ -8,6 +8,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

 ## [unreleased]

+## Changed
+
+- Naming improvements for UART register module
+- Improved UART Async TX module. Only enable TX below threshold interrupts if the FIFO
+  actually needs to be refilled.
+
 ## [v0.3.0] 2026-05-18

 ### Added