improve repository structure

firmware/zedboard-fsbl/Cargo.toml

@@ -13,7 +13,7 @@ aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
-zynq7000-boot-image = { path = "../../zynq7000-boot-image" }
+zynq7000-boot-image = { path = "../../host/zynq7000-boot-image" }
 zedboard-bsp = { path = "../zedboard-bsp" }
 embedded-io = "0.7"
 embedded-hal = "1"

firmware/zedboard-qspi-flasher/Cargo.toml

@@ -8,7 +8,7 @@ aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
-zynq7000-boot-image = { path = "../../zynq7000-boot-image" }
+zynq7000-boot-image = { path = "../../host/zynq7000-boot-image" }
 zedboard-bsp = { path = "../zedboard-bsp" }
 embedded-io = "0.7"
 embedded-hal = "1"

firmware/zynq7000-hal/src/clocks/mod.rs

@@ -1,8 +1,4 @@
 //! # Clock module
-//!
-//! ## Examples
-//!
-//! - PLL initialization in [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::{prelude::*, u6};
 
 pub mod pll;

firmware/zynq7000-hal/src/clocks/pll.rs

@@ -1,3 +1,4 @@
+//! # PLL support module
 use core::sync::atomic::AtomicBool;
 
 use arbitrary_int::{u4, u7, u10};

firmware/zynq7000-hal/src/ddr/mod.rs

@@ -1,8 +1,4 @@
 //! # DDR module
-//!
-//! ## Examples
-//!
-//! - [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::u6;
 use zynq7000::ddrc::MmioRegisters;
 

firmware/zynq7000-hal/src/eth/mod.rs

@@ -1,8 +1,4 @@
 //! # Ethernet module
-//!
-//! ## Examples
-//!
-//! - [Zedboard Ethernet](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/ethernet.rs)
 use arbitrary_int::{u2, u3};
 pub use zynq7000::eth::MdcClockDivisor;
 use zynq7000::eth::{

firmware/zynq7000-hal/src/gic.rs

@@ -2,10 +2,6 @@
 //!
 //! The primary interface to configure and allow handling the interrupts are the
 //! [GicConfigurator] and the [GicInterruptHelper] structures.
-//!
-//! # Examples
-//!
-//! - [GTC ticks](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
 #![deny(missing_docs)]
 use arbitrary_int::prelude::*;
 
@@ -314,7 +310,7 @@ pub struct InvalidSgiInterruptId(pub usize);
 ///    to have a certain value. It also sets the priority mask to 0xff by calling
 ///    [Self::set_priority_mask] to prevent masking of the interrupts.
 /// 2. Perform the configuration of the interrupt targets and the interrupt sensitivities.
-///    The CPU targets are encoded with [TargetCpu] while the sensitivities are encoded by
+///    The CPU targets are encoded with [TargetCpus] while the sensitivities are encoded by
 ///    the [SpiSensitivity] enum. You can use the following (helper) API to configure the
 ///    interrupts:
 ///

firmware/zynq7000-hal/src/gpio/mod.rs

@@ -2,12 +2,6 @@
 //!
 //! This module contains a MIO and EMIO pin resource managements singleton as well as abstractions
 //! to use these pins as GPIOs.
-//!
-//! # Examples
-//!
-//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/main.rs)
-//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
-//!   which uses MIO pins for the UART.
 pub mod emio;
 pub mod ll;
 pub mod mio;

firmware/zynq7000-hal/src/gtc.rs

@@ -1,9 +1,4 @@
 //! # Global timer counter driver module
-//!
-//! ## Examples
-//!
-//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/gtc-ticks.rs)
-//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zynq7000-embassy/src/lib.rs)
 #![deny(missing_docs)]
 use zynq7000::gtc::MmioRegisters;
 

firmware/zynq7000-hal/src/lib.rs

@@ -10,8 +10,8 @@
 //!
 //! ## Examples
 //!
-//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples)
-//! of the project
+//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/firmware/examples)
+//! and [firmware folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/firmware) of the project
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_cfg))]
 

firmware/zynq7000-hal/src/log.rs

@@ -1,9 +1,4 @@
 //! # Simple logging providers
-//!
-//! ## Examples
-//!
-//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
-//!   which uses MIO pins for the UART.
 
 use core::sync::atomic::{AtomicBool, AtomicU8};
 

firmware/zynq7000-hal/src/priv_tim.rs

@@ -1,8 +1,4 @@
 //! # CPU private timer module
-//!
-//! ## Examples
-//!
-//! - Private timer as delay provider in [blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/blinky.rs)
 #![deny(missing_docs)]
 use core::{marker::PhantomData, sync::atomic::AtomicBool};
 

firmware/zynq7000-hal/src/qspi/mod.rs

@@ -1,8 +1,4 @@
 //! # QSPI module
-//!
-//! ## Examples
-//!
-//! - [Zedboard QSPI](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/qspi.rs)
 use core::ops::{Deref, DerefMut};
 
 use arbitrary_int::{prelude::*, u2, u3, u6};

firmware/zynq7000-hal/src/spi/mod.rs

@@ -1,8 +1,4 @@
 //! SPI module
-//!
-//! ## Examples
-//!
-//! - [L3GD20H SPI sensor](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs)
 use core::convert::Infallible;
 
 use crate::clocks::Clocks;