Merge pull request 'add various changelogs' (#15) from changelogs into main

Reviewed-on: #15

zynq/zedboard-bsp/CHANGELOG.md

@@ -0,0 +1,16 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+# [unreleased]
+
+# [v0.1.0]
+
+Initial release
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zedboard-bsp-v0.1.0...HEAD
+[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tags/zedboard-bsp-v0.1.0

zynq/zynq7000-embassy/CHANGELOG.md

@@ -0,0 +1,16 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+# [unreleased]
+
+# [v0.1.0] 2025-10-08
+
+Initial release
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/v0.1.0...HEAD
+[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tags/zynq7000-embassy-v0.1.0

zynq/zynq7000-hal/CHANGELOG.md

@@ -0,0 +1,16 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+# [unreleased]
+
+# [v0.1.0] 2025-10-09
+
+Initial release
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-hal-v0.1.0...HEAD
+[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tags/zynq7000-hal-v0.1.0

zynq/zynq7000-mmu/CHANGELOG.md

@@ -0,0 +1,16 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+# [unreleased]
+
+# [v0.1.0] 2025-10-09
+
+Initial release
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-mmu-v0.1.0...HEAD
+[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tags/zynq7000-mmu-v0.1.0

zynq/zynq7000-rt/CHANGELOG.md

@@ -0,0 +1,16 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+# [unreleased]
+
+# [v0.1.0] 2025-10-09
+
+Initial release
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.0...HEAD
+[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tags/zynq7000-rt-v0.1.0

zynq/zynq7000/CHANGELOG.md

@@ -0,0 +1,21 @@
+Change Log
+=======
+
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/)
+and this project adheres to [Semantic Versioning](http://semver.org/).
+
+# [unreleased]
+
+# [v0.1.1] 2025-10-09
+
+Documenation fix
+
+# [v0.1.0] 2025-10-08
+
+Initial release
+
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.1...HEAD
+[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.0...zynq7000-0.1.1
+[v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tags/zynq7000-v0.1.0

zynq/zynq7000/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "zynq7000"
-version = "0.1.0"
+version = "0.1.1"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2024"
 description = "Peripheral Access Crate (PAC) for the Zynq7000 family of SoCs"

zynq/zynq7000/README.md

@@ -2,7 +2,8 @@
 [![docs.rs](https://img.shields.io/docsrs/zynq7000)](https://docs.rs/zynq7000)
 [![ci](https://github.com/us-irs/zynq7000-rs/actions/workflows/ci.yml/badge.svg?branch=main)](https://github.com/us-irs/zynq7000-rs/actions/workflows/ci.yml)
 
-# PAC for
+# PAC for the AMD Zynq 7000 SoC family
+
 This repository contains the Peripheral Access Crate (PAC) for the AMD Zynq7000 SoC family.
 
 If you are interested in higher-level abstractions, it is recommended you visit