rust/zynq7000-rs
Archived
12
0 Fork 0
Code Issues Actions Packages Projects Releases 18 Wiki Activity

bugfix for PL programming routine
ci / Check build (push) Has been cancelled
Details
ci / Check formatting (push) Has been cancelled
Details
ci / Check Documentation Build (push) Has been cancelled
Details
ci / Clippy (push) Has been cancelled
Details
ci / Check build (pull_request) Has been cancelled
Details
ci / Check formatting (pull_request) Has been cancelled
Details
ci / Check Documentation Build (pull_request) Has been cancelled
Details
ci / Clippy (pull_request) Has been cancelled
Details

Browse Source
This commit is contained in:
muellerr committed 2026-02-07 01:35:27 +01:00
1 parent e3a05cc650
commit 3ba6c63554
1 file changed
+7 -3
Download Patch File Download Diff File Expand all files Collapse all files
firmware/zynq7000-hal/src/devcfg.rs
+7 -3
View File
@@ -53,10 +53,14 @@ pub fn configure_bitstream_non_secure(
val.set_pcap_rate_enable(false);
val
});
devcfg.write_dma_source_addr(bitstream.as_ptr() as u32);
// As specified in the TMR,
// Setting the two LSBs of the source and destination address to 2'b01 indicates to the DevC
// DMA module the last DMA command of an overall transfer
devcfg.write_dma_source_addr(bitstream.as_ptr() as u32 | 0b01);
devcfg.write_dma_dest_addr(0xFFFF_FFFF);
devcfg.write_dma_source_len(bitstream.len() as u32);
devcfg.write_dma_dest_len(bitstream.len() as u32);
devcfg.write_dma_source_len(bitstream.len() as u32 / 4);
devcfg.write_dma_dest_len(bitstream.len() as u32 / 4);
while !devcfg.read_interrupt_status().dma_done() {}
// TODO: Check for errors.