continue

zynq7000-hal/src/eth/rx_descr.rs

@@ -0,0 +1,85 @@
+//! RX buffer descriptor module.
+pub use super::Ownership;
+use arbitrary_int::{u2, u3, u13, u30};
+
+/// RX buffer descriptor.
+///
+/// The user should declare an array of this structure inside uncached memory.
+///
+/// These descriptors are shared between software and hardware and contain information
+/// related to frame reception.
+#[repr(C)]
+pub struct Descriptor {
+    /// The first word of the descriptor.
+    pub word0: Word0,
+    /// The second word of the descriptor.
+    pub word1: Word1,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug, PartialEq, Eq)]
+pub struct Word0 {
+    /// The full reception address with the last two bits cleared.
+    #[bits(2..=31, rw)]
+    addr_upper_30_bits: u30,
+    #[bit(1, rw)]
+    wrap: bool,
+    #[bit(0, rw)]
+    ownership: Ownership,
+}
+
+#[bitbybit::bitfield(u32)]
+#[derive(Debug, PartialEq, Eq)]
+pub struct Word1 {
+    #[bit(31, r)]
+    broadcast_detect: bool,
+    #[bit(30, r)]
+    multicast_hash: bool,
+    #[bit(29, r)]
+    unicast_hash: bool,
+    #[bit(27, r)]
+    specific_addr_match: bool,
+    /// Specifies which of the 4 specific address registers was matched.
+    #[bits(25..=26, r)]
+    specific_addr_match_info: u2,
+    #[bit(24, r)]
+    type_id_match_or_snap_info: bool,
+    #[bits(22..=23, r)]
+    type_id_match_info_or_chksum_status: u2,
+    #[bit(21, r)]
+    vlan_tag_detected: bool,
+    #[bit(20, r)]
+    priority_tag_detected: bool,
+    #[bits(17..=19, r)]
+    vlan_prio: u3,
+    #[bit(16, r)]
+    cfi_bit: bool,
+    #[bit(15, r)]
+    end_of_frame: bool,
+    #[bit(14, r)]
+    start_of_frame: bool,
+    /// Relevant when FCS errors are not ignored.
+    /// 0: Frame has good FCS, 1: Frame has bad FCS, but was copied to memory as the ignore FCS
+    /// functionality was enabled.
+    #[bit(13, r)]
+    fcs_status: bool,
+    #[bits(0..=12, r)]
+    rx_len: u13,
+}
+
+impl Descriptor {
+    #[inline]
+    pub fn set_ownership(&mut self, ownership: Ownership) {
+        self.word0.set_ownership(ownership);
+    }
+
+    #[inline]
+    pub fn set_wrap_bit(&mut self) {
+        self.word0.set_wrap(true);
+    }
+
+    #[inline]
+    pub fn write_rx_addr(&mut self, addr: u32) {
+        self.word0.set_addr_upper_30_bits(u30::new(addr >> 2));
+    }
+}