continue

zynq7000/src/eth.rs

@@ -263,6 +263,12 @@ pub struct TxStatus {
     read_when_used: bool,
 }
 
+impl TxStatus {
+    pub fn new_clear_all() -> Self {
+        Self::new_with_raw_value(0xFF)
+    }
+}
+
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
 pub struct RxStatus {
@@ -276,6 +282,12 @@ pub struct RxStatus {
     buf_not_available: bool,
 }
 
+impl RxStatus {
+    pub fn new_clear_all() -> Self {
+        Self::new_with_raw_value(0xF)
+    }
+}
+
 #[bitbybit::bitfield(u32)]
 #[derive(Debug)]
 pub struct InterruptStatus {
@@ -362,6 +374,12 @@ pub struct InterruptControl {
     mgmt_frame_sent: bool,
 }
 
+impl InterruptControl {
+    pub fn new_clear_all() -> Self {
+        Self::new_with_raw_value(0xFFFF_FFFF)
+    }
+}
+
 #[bitbybit::bitenum(u2, exhaustive = false)]
 pub enum PhyOperation {
     Read = 0b10,

zynq7000/src/slcr/reset.rs

@@ -35,6 +35,23 @@ pub struct GpioClockReset {
     gpio_cpu1x_rst: bool,
 }
 
+#[bitbybit::bitfield(u32, default = 0x0)]
+#[derive(Debug)]
+pub struct EthernetReset {
+    #[bit(5, rw)]
+    gem1_ref_rst: bool,
+    #[bit(4, rw)]
+    gem0_ref_rst: bool,
+    #[bit(3, rw)]
+    gem1_rx_rst: bool,
+    #[bit(2, rw)]
+    gem0_rx_rst: bool,
+    #[bit(1, rw)]
+    gem1_cpu1x_rst: bool,
+    #[bit(0, rw)]
+    gem0_cpu1x_rst: bool,
+}
+
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct ResetControl {
@@ -45,7 +62,7 @@ pub struct ResetControl {
     topsw: u32,
     dmac: u32,
     usb: u32,
-    gem: u32,
+    eth: EthernetReset,
     sdio: DualRefAndClockReset,
     spi: DualRefAndClockReset,
     can: DualClockReset,