continue
This commit is contained in:
parent
8c9e34f96a
commit
47b150369d
GPG Key ID:
A649FB78196E3849
@ -1,14 +1,27 @@
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use arbitrary_int::{u2, u3, u13, u30};
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use zynq7000::eth::{GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, MmioEthernet};
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use arbitrary_int::{Number, u2, u3, u6, u13, u30};
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use zynq7000::{
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eth::{
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GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, InterruptControl, MmioEthernet, NetworkControl, RxStatus,
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SpeedMode, TxStatus,
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},
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slcr::reset::EthernetReset,
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};
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#[cfg(not(feature = "7z010-7z007s-clg225"))]
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use crate::gpio::mio::{Mio28, Mio29, Mio30, Mio31, Mio32, Mio33};
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use crate::gpio::{
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use crate::gpio::mio::{
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Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27,
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};
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use crate::{
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enable_amba_peripheral_clock,
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gpio::{
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IoPeriphPin,
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mio::{
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Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27, Mio34,
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Mio35, Mio36, Mio37, Mio38, Mio39, Mio52, Mio53, MioPinMarker, MuxConf, Pin,
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Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39,
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Mio52, Mio53, MioPinMarker, MuxConf, Pin,
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},
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},
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slcr::Slcr,
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time::Hertz,
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};
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pub const MUX_CONF_PHY: MuxConf = MuxConf::new_with_l0();
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@ -172,22 +185,191 @@ impl RxData3 for Pin<Mio38> {
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const ETH_ID: EthernetId = EthernetId::Eth1;
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}
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pub struct EthernetLowLevel(zynq7000::eth::MmioEthernet<'static>);
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pub struct EthernetLowLevel {
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id: EthernetId,
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pub regs: zynq7000::eth::MmioEthernet<'static>,
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}
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#[derive(Debug, Clone, Copy)]
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pub struct ClkConfig {
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pub src_sel: zynq7000::slcr::clocks::SrcSelIo,
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pub use_emio_tx_clk: bool,
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pub divisor_0: u6,
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pub divisor_1: u6,
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/// Enable the clock.
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pub enable: bool,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum Speed {
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Mbps10,
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Mbps100,
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Mbps1000,
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}
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impl Speed {
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pub const fn rgmii_clk_rate(&self) -> Hertz {
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match self {
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Speed::Mbps10 => Hertz::from_raw(2_500_000),
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Speed::Mbps100 => Hertz::from_raw(25_000_000),
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Speed::Mbps1000 => Hertz::from_raw(125_000_000),
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}
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}
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}
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impl ClkConfig {
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pub const fn new(divisor_0: u6, divisor_1: u6) -> Self {
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Self {
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src_sel: zynq7000::slcr::clocks::SrcSelIo::IoPll,
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use_emio_tx_clk: false,
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divisor_0,
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divisor_1,
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enable: true,
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}
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}
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/// Calculate the best clock configuration (divisors) for the given reference clock
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/// and desired target speed when using a RGMII interface.
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///
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/// Usually, the reference clock will be the IO clock.
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///
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/// Returns a tuple where the first entry is the calcualted clock configuration
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/// and the second entry is the difference between calculated clock speed for the divisors
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/// and the target speed. Ideally, this difference should be 0.
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pub fn calculate_for_rgmii(ref_clk: Hertz, target_speed: Speed) -> (Self, u32) {
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let mut smallest_diff = u32::MAX;
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let target_speed = target_speed.rgmii_clk_rate();
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let mut best_div_0 = u6::new(0);
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let mut best_div_1 = u6::new(0);
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for div_0 in 0..=u6::MAX.as_usize() {
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for div_1 in 0..=u6::MAX.as_usize() {
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let clk_rate = ref_clk.raw() / div_0 as u32 / div_1 as u32;
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let diff = (target_speed.raw() as i64 - clk_rate as i64).unsigned_abs() as u32;
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if diff < smallest_diff {
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smallest_diff = diff;
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best_div_0 = u6::new(div_0 as u8);
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best_div_1 = u6::new(div_1 as u8);
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}
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// We found a perfect match. No need to continue.
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if diff == 0 {
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break;
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}
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}
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}
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(Self::new(best_div_0, best_div_1), smallest_diff)
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}
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}
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/// Ethernet low-level interface.
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impl EthernetLowLevel {
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/// Creates a new instance of the Ethernet low-level interface.
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pub fn new(eth: zynq7000::eth::MmioEthernet<'static>) -> Self {
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EthernetLowLevel(eth)
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#[inline]
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pub fn new(regs: zynq7000::eth::MmioEthernet<'static>) -> Option<Self> {
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regs.id()?;
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Some(EthernetLowLevel {
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id: regs.id().unwrap(),
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regs,
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})
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}
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/// Returns a reference to the underlying MMIO Ethernet interface.
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pub fn regs(&self) -> &zynq7000::eth::MmioEthernet<'static> {
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&self.0
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/// Create a low-level instance for the given [EthernetId].
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///
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/// # Safety
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///
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/// Circumvents ownership and safety guarantees of the HAL.
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#[inline]
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pub const unsafe fn steal(id: EthernetId) -> Self {
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Self {
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id,
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regs: unsafe {
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match id {
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EthernetId::Eth0 => zynq7000::eth::Ethernet::new_mmio_fixed_0(),
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EthernetId::Eth1 => zynq7000::eth::Ethernet::new_mmio_fixed_1(),
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}
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},
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}
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}
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/// Returns a mutable reference to the underlying MMIO Ethernet interface.
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pub fn regs_mut(&mut self) -> &mut zynq7000::eth::MmioEthernet<'static> {
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&mut self.0
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pub fn reset(&mut self, cycles: usize) {
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let assert_reset = match self.id {
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EthernetId::Eth0 => EthernetReset::builder()
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.with_gem1_ref_rst(false)
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.with_gem0_ref_rst(true)
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.with_gem1_rx_rst(false)
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.with_gem0_rx_rst(true)
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.with_gem1_cpu1x_rst(false)
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.with_gem0_cpu1x_rst(true)
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.build(),
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EthernetId::Eth1 => EthernetReset::builder()
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.with_gem1_ref_rst(true)
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.with_gem0_ref_rst(false)
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.with_gem1_rx_rst(true)
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.with_gem0_rx_rst(false)
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.with_gem1_cpu1x_rst(true)
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.with_gem0_cpu1x_rst(false)
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.build(),
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};
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unsafe {
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Slcr::with(|regs| {
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regs.reset_ctrl().write_eth(assert_reset);
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for _ in 0..cycles {
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cortex_ar::asm::nop();
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}
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regs.reset_ctrl().write_eth(EthernetReset::DEFAULT);
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});
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}
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}
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#[inline]
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pub fn enable_peripheral_clock(&mut self) {
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let periph_sel = match self.id {
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EthernetId::Eth0 => crate::PeripheralSelect::Gem0,
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EthernetId::Eth1 => crate::PeripheralSelect::Gem1,
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};
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enable_amba_peripheral_clock(periph_sel);
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}
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#[inline]
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pub fn configure_clock(&mut self, cfg: ClkConfig) {
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unsafe {
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Slcr::with(|regs| {
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regs.clk_ctrl().modify_gem_0_clk_ctrl(|mut val| {
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val.set_srcsel(cfg.src_sel);
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val.set_divisor_0(cfg.divisor_0);
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val.set_divisor_1(cfg.divisor_1);
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val.set_use_emio_tx_clk(cfg.use_emio_tx_clk);
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val.set_clk_act(cfg.enable);
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val
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});
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})
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}
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}
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#[inline]
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pub fn configure_mdc_clk_div() {
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// TODO:
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}
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/// Performs initialization according to TRM p.541.
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///
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/// These steps do not include any resets or clock configuration.
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pub fn initialize(&mut self) {
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let mut ctrl_val = NetworkControl::new_with_raw_value(0);
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self.regs.write_net_ctrl(ctrl_val);
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// Now clear statistics.
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ctrl_val.set_clear_statistics(true);
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self.regs.write_net_ctrl(ctrl_val);
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self.regs.write_tx_status(TxStatus::new_clear_all());
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self.regs.write_rx_status(RxStatus::new_clear_all());
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self.regs
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.write_interrupt_disable(InterruptControl::new_clear_all());
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self.regs.write_rx_buf_queue_base_addr(0);
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self.regs.write_tx_buf_queue_base_addr(0);
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}
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#[inline]
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pub const fn id(&self) -> EthernetId {
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self.id
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}
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}
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@ -213,7 +395,8 @@ impl Ethernet {
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MdClkPin: MdClk,
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MdIoPin: MdIo,
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>(
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ll: EthernetLowLevel,
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mut ll: EthernetLowLevel,
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clk_config: ClkConfig,
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tx_clk: TxClkPin,
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tx_ctrl: TxCtrlPin,
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tx_data: (TxData0Pin, TxData1Pin, TxData2Pin, TxData3Pin),
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@ -222,6 +405,7 @@ impl Ethernet {
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rx_data: (RxData0Pin, RxData1Pin, RxData2Pin, RxData3Pin),
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md_pins: Option<(MdClkPin, MdIoPin)>,
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) -> Self {
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Self::common_init(&mut ll);
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let tx_mio_config = zynq7000::slcr::mio::Config::builder()
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.with_disable_hstl_rcvr(true)
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.with_pullup(true)
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@ -337,12 +521,42 @@ impl Ethernet {
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});
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});
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}
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ll.configure_clock(clk_config);
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Ethernet { ll }
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}
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pub fn new(ll: EthernetLowLevel) -> Self {
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pub fn new(mut ll: EthernetLowLevel, clk_config: ClkConfig) -> Self {
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Self::common_init(&mut ll);
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ll.configure_clock(clk_config);
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Ethernet { ll }
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}
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fn common_init(ll: &mut EthernetLowLevel) {
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ll.enable_peripheral_clock();
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ll.reset(3);
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ll.initialize();
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ll.regs.modify_net_cfg(|mut net_cfg| {
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net_cfg.set_full_duplex(true);
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net_cfg.set_gigabit_enable(true);
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net_cfg.set_speed_mode(SpeedMode::High100Mbps);
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net_cfg
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});
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}
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#[inline]
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pub fn ll(&mut self) -> &mut EthernetLowLevel {
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&mut self.ll
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}
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#[inline]
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pub fn regs(&mut self) -> &MmioEthernet<'static> {
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&self.ll.regs
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}
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#[inline]
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pub fn regs_mut(&mut self) -> &mut MmioEthernet<'static> {
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&mut self.ll.regs
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}
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}
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/// RX buffer descriptor.
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///
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@ -263,6 +263,12 @@ pub struct TxStatus {
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read_when_used: bool,
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}
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impl TxStatus {
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pub fn new_clear_all() -> Self {
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Self::new_with_raw_value(0xFF)
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}
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct RxStatus {
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@ -276,6 +282,12 @@ pub struct RxStatus {
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buf_not_available: bool,
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}
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impl RxStatus {
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pub fn new_clear_all() -> Self {
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Self::new_with_raw_value(0xF)
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}
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}
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#[bitbybit::bitfield(u32)]
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#[derive(Debug)]
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pub struct InterruptStatus {
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@ -362,6 +374,12 @@ pub struct InterruptControl {
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mgmt_frame_sent: bool,
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}
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impl InterruptControl {
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pub fn new_clear_all() -> Self {
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Self::new_with_raw_value(0xFFFF_FFFF)
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}
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}
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#[bitbybit::bitenum(u2, exhaustive = false)]
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pub enum PhyOperation {
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Read = 0b10,
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@ -35,6 +35,23 @@ pub struct GpioClockReset {
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gpio_cpu1x_rst: bool,
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}
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct EthernetReset {
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#[bit(5, rw)]
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gem1_ref_rst: bool,
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#[bit(4, rw)]
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gem0_ref_rst: bool,
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#[bit(3, rw)]
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gem1_rx_rst: bool,
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#[bit(2, rw)]
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gem0_rx_rst: bool,
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#[bit(1, rw)]
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gem1_cpu1x_rst: bool,
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#[bit(0, rw)]
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gem0_cpu1x_rst: bool,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct ResetControl {
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@ -45,7 +62,7 @@ pub struct ResetControl {
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topsw: u32,
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dmac: u32,
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usb: u32,
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gem: u32,
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eth: EthernetReset,
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sdio: DualRefAndClockReset,
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spi: DualRefAndClockReset,
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can: DualClockReset,
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