update dependencies

examples/zedboard/Cargo.toml

@@ -40,7 +40,8 @@ embassy-executor = { git = "https://github.com/us-irs/embassy.git", branch = "co
 embassy-time = { version = "0.5", features = ["tick-hz-1_000_000", "generic-queue-16"] }
 embassy-net = { version = "0.7", features = ["dhcpv4", "packet-trace", "medium-ethernet", "icmp", "tcp", "udp"] }
 embassy-sync = { version = "0.7" }
-heapless = "0.9"
+# TODO: Bump as soon as new compatible smoltcp/embassy-net version is released.
+heapless = "0.8"
 axi-uartlite = { git = "https://egit.irs.uni-stuttgart.de/rust/axi-uartlite.git" }
 axi-uart16550 = { git = "https://egit.irs.uni-stuttgart.de/rust/axi-uart16550.git" }
 

zedboard-bsp/src/qspi_spansion.rs

@@ -1,6 +1,6 @@
 use core::cell::RefCell;
 
-use arbitrary_int::{Number, u24};
+use arbitrary_int::{prelude::*, u24};
 use zynq7000_hal::qspi::{
     FIFO_DEPTH, LinearQspiConfig, QspiIoMode, QspiIoTransferGuard, QspiLinearAddressing,
     QspiLinearReadGuard,

zynq-mmu/Cargo.toml

@@ -6,7 +6,7 @@ edition = "2024"
 
 [dependencies]
 thiserror = { version = "2", default-features = false }
-cortex-ar = { version = "0.2", git = "https://github.com/rust-embedded/cortex-ar.git", rev = "79dba7000d2090d13823bfb783d9d64be8b778d2" }
+cortex-ar = { version = "0.2", git = "https://github.com/rust-embedded/cortex-ar.git", branch = "bump-arbitrary-int" }
 
 [features]
 tools = []

zynq7000-hal/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "amd", "zynq7000", "xilinx", "bare-metal"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-cortex-ar = { version = "0.2", git = "https://github.com/rust-embedded/cortex-ar.git", rev = "79dba7000d2090d13823bfb783d9d64be8b778d2" }
+cortex-ar = { version = "0.2", git = "https://github.com/rust-embedded/cortex-ar.git", branch = "bump-arbitrary-int" }
 zynq7000 = { path = "../zynq7000" }
 zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
 

zynq7000-hal/src/clocks/mod.rs

@@ -1,5 +1,5 @@
 //! Clock module.
-use arbitrary_int::{Number, u6};
+use arbitrary_int::{prelude::*, u6};
 
 pub mod pll;
 

zynq7000-hal/src/ddr/ll.rs

@@ -1,5 +1,5 @@
 //! Low-level DDR configuration module.
-use arbitrary_int::{Number, u2, u3, u6};
+use arbitrary_int::{prelude::*, u2, u3, u6};
 use zynq7000::ddrc::{MmioDdrController, regs::*};
 use zynq7000::slcr::{clocks::DciClockControl, ddriob::DdriobConfig};
 

zynq7000-hal/src/eth/ll.rs

@@ -1,4 +1,4 @@
-use arbitrary_int::{Number, u6};
+use arbitrary_int::{prelude::*, u6};
 use zynq7000::{
     eth::{InterruptControl, NetworkControl, RxStatus, TxStatus},
     slcr::reset::EthernetReset,

zynq7000-hal/src/eth/rx_descr.rs

@@ -4,7 +4,7 @@ use core::{cell::UnsafeCell, mem::MaybeUninit, sync::atomic::AtomicBool};
 use crate::{cache::clean_and_invalidate_data_cache_range, eth::AlignedBuffer};
 
 pub use super::shared::Ownership;
-use arbitrary_int::{Number, u2, u3, u13, u30};
+use arbitrary_int::{prelude::*, u2, u3, u13, u30};
 use vcell::VolatileCell;
 
 static RX_DESCR_TAKEN: AtomicBool = AtomicBool::new(false);

zynq7000-hal/src/gic.rs

@@ -6,7 +6,7 @@
 //! # Examples
 //!
 //! - [GTC ticks](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
-use arbitrary_int::Number;
+use arbitrary_int::prelude::*;
 
 use cortex_ar::interrupt;
 use zynq7000::gic::{

zynq7000-hal/src/qspi/mod.rs

@@ -1,6 +1,6 @@
 use core::ops::{Deref, DerefMut};
 
-use arbitrary_int::{Number, u2, u3, u6};
+use arbitrary_int::{prelude::*, u2, u3, u6};
 pub use zynq7000::qspi::LinearQspiConfig;
 use zynq7000::{
     qspi::{

zynq7000-hal/src/spi/mod.rs

@@ -15,7 +15,7 @@ use crate::gpio::mio::{
 use crate::{enable_amba_peripheral_clock, spi_mode_const_to_cpol_cpha};
 
 use crate::{clocks::IoClocks, slcr::Slcr, time::Hertz};
-use arbitrary_int::{Number, u3, u4, u6};
+use arbitrary_int::{prelude::*, u3, u4, u6};
 use embedded_hal::delay::DelayNs;
 pub use embedded_hal::spi::Mode;
 use embedded_hal::spi::SpiBus as _;

zynq7000-hal/src/ttc.rs

@@ -4,7 +4,7 @@
 
 use core::convert::Infallible;
 
-use arbitrary_int::{Number, u3, u4};
+use arbitrary_int::{prelude::*, u3, u4};
 use zynq7000::ttc::{MmioTtc, TTC_0_BASE_ADDR, TTC_1_BASE_ADDR};
 
 #[cfg(not(feature = "7z010-7z007s-clg225"))]
@@ -188,23 +188,22 @@ pub enum TtcConstructionError {
 
 pub fn calc_prescaler_reg_and_interval_ticks(mut ref_clk: Hertz, freq: Hertz) -> (Option<u4>, u16) {
     // TODO: Can this be optimized?
-    let mut prescaler_reg: Option<u4> = None;
+    let mut prescaler: Option<u32> = None;
     let mut tick_val = ref_clk / freq;
     while tick_val > u16::MAX as u32 {
         ref_clk /= 2;
-        if let Some(prescaler_reg) = prescaler_reg {
-            // TODO: Better error handling for this case? Can this even happen?
-            if prescaler_reg.value() == u4::MAX.value() {
-                break;
-            } else {
-                prescaler_reg.checked_add(u4::new(1));
+        match prescaler {
+            Some(val) => {
+                if val == u4::MAX.as_u32() {
+                    break;
+                }
+                prescaler = Some(val + 1);
             }
-        } else {
-            prescaler_reg = Some(u4::new(0));
+            None => prescaler = Some(0),
         }
         tick_val = ref_clk / freq;
     }
-    (prescaler_reg, tick_val as u16)
+    (prescaler.map(|v| u4::new(v as u8)), tick_val as u16)
 }
 
 pub struct Pwm {

zynq7000-hal/src/uart/rx.rs

@@ -1,6 +1,6 @@
 use core::convert::Infallible;
 
-use arbitrary_int::Number;
+use arbitrary_int::prelude::*;
 use zynq7000::uart::{InterruptControl, InterruptStatus, MmioUart};
 
 use super::FIFO_DEPTH;

zynq7000-rt/Cargo.toml

@@ -12,7 +12,7 @@ categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
 cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
-cortex-ar = { version = "0.2", git = "https://github.com/rust-embedded/cortex-ar.git", rev = "79dba7000d2090d13823bfb783d9d64be8b778d2" }
+cortex-ar = { version = "0.2", git = "https://github.com/rust-embedded/cortex-ar.git", branch = "bump-arbitrary-int" }
 arbitrary-int = "2"
 zynq-mmu = { path = "../zynq-mmu", version = "0.1.0" }
 

zynq7000/src/slcr/clocks.rs

@@ -12,8 +12,7 @@ pub enum Bypass {
     BypassedRegardlessOfPinStrapping = 0b11,
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct PllControl {
     /// Feedback divisor for the PLL.
     ///
@@ -69,8 +68,7 @@ impl PllControl {
     }
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct PllConfig {
     #[bits(12..=21, rw)]
     lock_count: u10,
@@ -82,8 +80,7 @@ pub struct PllConfig {
     loop_resistor: u4,
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct PllStatus {
     #[bit(5, r)]
     io_pll_stable: bool,
@@ -99,8 +96,7 @@ pub struct PllStatus {
     arm_pll_lock: bool,
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct FpgaClockControl {
     // Reset value 0x1
     #[bits(20..=25, rw)]
@@ -132,7 +128,7 @@ pub enum SrcSelArm {
     IoPll = 0b11,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct ArmClockControl {
     #[bit(28, rw)]
     cpu_peri_clk_act: bool,
@@ -153,7 +149,7 @@ pub struct ArmClockControl {
     srcsel: SrcSelArm,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct DdrClockControl {
     /// Divisor for DDR 2x clock. Reset value: 0x6
     #[bits(26..=31, rw)]
@@ -169,7 +165,7 @@ pub struct DdrClockControl {
     ddr_3x_clk_act: bool,
 }
 
-#[bitbybit::bitfield(u32, default = 0x0)]
+#[bitbybit::bitfield(u32, default = 0x0, debug)]
 pub struct DciClockControl {
     /// Second cascade divider. Reset value: 0x1E
     #[bits(20..=25, rw)]
@@ -182,8 +178,7 @@ pub struct DciClockControl {
     clk_act: bool,
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct ClockRatioSelectReg {
     /// Reset value: 0x1 (6:2:1 clock)
     #[bit(0, rw)]
@@ -227,8 +222,7 @@ impl PartialEq for SrcSelIo {
     }
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct GigEthClockControl {
     #[bits(20..=25, rw)]
     divisor_1: u6,
@@ -249,8 +243,7 @@ pub enum SrcSelGigEthRclk {
     Emio = 1,
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct GigEthRclkControl {
     #[bit(4, rw)]
     srcsel: SrcSelGigEthRclk,
@@ -284,8 +277,7 @@ pub struct SingleCommonPeriphIoClockControl {
     clk_act: bool,
 }
 
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct DualCommonPeriphIoClockControl {
     #[bits(8..=13, rw)]
     divisor: u6,
@@ -310,7 +302,7 @@ pub enum SrcSelTpiu {
     EmioTraceClkAlt2 = 0b111,
 }
 
-#[bitbybit::bitfield(u32)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct TracePortClockControl {
     #[bits(8..=13, rw)]
     divisor: u6,
@@ -325,8 +317,7 @@ pub struct TracePortClockControl {
 /// AMBA peripheral clock control.
 ///
 /// These clocks must be enabled if you want to read from the peripheral register space.
-#[bitbybit::bitfield(u32)]
-#[derive(Debug)]
+#[bitbybit::bitfield(u32, debug)]
 pub struct AperClockControl {
     #[bit(24, rw)]
     smc_1x_clk_act: bool,

zynq7000/src/spi.rs

@@ -1,5 +1,5 @@
 //! SPI register module.
-use arbitrary_int::{Number, u4};
+use arbitrary_int::{prelude::*, u4};
 
 pub use crate::{SpiClockPhase, SpiClockPolarity};