rust/zynq7000-rs
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replaced cortex-ar and cortex-a-rt by aarch32-rt and aarch32-cpu
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This commit is contained in:
Robin Mueller
2025-10-28 00:05:27 +01:00
parent b394da69f3
commit a8339153c4
51 changed files with 131 additions and 212 deletions
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2
justfile
View File

@@ -19,7 +19,7 @@ clean target:
cd {{target}} && cargo clean
fmt target:
cd {{target}} && cargo +stable fmt --all -- --check
cd {{target}} && cargo +stable fmt
clippy target:
cd {{target}} && cargo clippy -- -D warnings

180
tools/Cargo.lock generated
View File

@@ -2,6 +2,19 @@
# It is not intended for manual editing.
version = 4
[[package]]
name = "aarch32-cpu"
version = "0.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "5db6700cf01549520abec199376115e1ceb6fde1d1de30064f0f230be8a0c305"
dependencies = [
"arbitrary-int 2.0.0",
"arm-targets",
"bitbybit",
"num_enum",
"thiserror",
]
[[package]]
name = "aho-corasick"
version = "1.1.3"
@@ -75,9 +88,9 @@ checksum = "c858caffa49edfc4ecc45a4bec37abd3e88041a2903816f10f990b7b41abc281"
[[package]]
name = "arm-targets"
version = "0.3.0"
version = "0.4.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "3371884971a96d71d8bd4e781188a7d327d7e5e455d07ef4c352922c66695e9e"
checksum = "8d29a37f252452446b67d5e50dee82a6ce12781218b915244bb6507c10b72812"
[[package]]
name = "bitbybit"
@@ -101,9 +114,9 @@ dependencies = [
[[package]]
name = "clap"
version = "4.5.48"
version = "4.5.50"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e2134bb3ea021b78629caa971416385309e0131b351b25e01dc16fb54e1b5fae"
checksum = "0c2cfd7bf8a6017ddaa4e32ffe7403d547790db06bd171c1c53926faab501623"
dependencies = [
"clap_builder",
"clap_derive",
@@ -111,9 +124,9 @@ dependencies = [
[[package]]
name = "clap_builder"
version = "4.5.48"
version = "4.5.50"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "c2ba64afa3c0a6df7fa517765e31314e983f51dda798ffba27b988194fb65dc9"
checksum = "0a4c05b9e80c5ccd3a7ef080ad7b6ba7d6fc00a985b8b157197075677c82c7a0"
dependencies = [
"anstream",
"anstyle",
@@ -123,9 +136,9 @@ dependencies = [
[[package]]
name = "clap_derive"
version = "4.5.47"
version = "4.5.49"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "bbfd7eae0b0f1a6e63d4b13c9c478de77c2eb546fba158ad50b4203dc24b9f9c"
checksum = "2a0b5487afeab2deb2ff4e03a807ad1a03ac532ff5a2cee5d86884440c7f7671"
dependencies = [
"heck",
"proc-macro2",
@@ -135,9 +148,9 @@ dependencies = [
[[package]]
name = "clap_lex"
version = "0.7.5"
version = "0.7.6"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b94f61472cee1439c0b966b47e3aca9ae07e45d070759512cd390ea2bebc6675"
checksum = "a1d728cc89cf3aee9ff92b05e62b19ee65a02b5702cff7d5a377e32c6ae29d8d"
[[package]]
name = "colorchoice"
@@ -147,27 +160,13 @@ checksum = "b05b61dc5112cbb17e4b6cd61790d9845d13888356391624cbe7e41efeac1e75"
[[package]]
name = "colored"
version = "2.2.0"
version = "3.0.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "117725a109d387c937a1533ce01b450cbde6b88abceea8473c4d7a85853cda3c"
checksum = "fde0e0ec90c9dfb3b4b1a0891a7dcd0e2bffde2f7efed5fe7c9bb00e5bfb915e"
dependencies = [
"lazy_static",
"windows-sys 0.59.0",
]
[[package]]
name = "cortex-ar"
version = "0.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b4ea2a354642e242870bc43b57a517359b0be6e96d302b2811cd0644c979c54e"
dependencies = [
"arbitrary-int 2.0.0",
"arm-targets",
"bitbybit",
"num_enum",
"thiserror",
]
[[package]]
name = "critical-section"
version = "1.2.0"
@@ -176,9 +175,9 @@ checksum = "790eea4361631c5e7d22598ecd5723ff611904e3344ce8720784c93e3d83d40b"
[[package]]
name = "deranged"
version = "0.5.4"
version = "0.5.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a41953f86f8a05768a6cda24def994fd2f424b04ec5c719cf89989779f199071"
checksum = "ececcb659e7ba858fb4f10388c250a7252eb0a27373f1a72b8748afdd248e587"
dependencies = [
"powerfmt",
]
@@ -213,9 +212,9 @@ checksum = "2304e00983f87ffb38b55b444b5e3b60a884b5d30c0fca7d82fe33449bbe55ea"
[[package]]
name = "is_terminal_polyfill"
version = "1.70.1"
version = "1.70.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "7943c866cc5cd64cbc25b2e01621d07fa8eb2a1a23160ee81ce38704e97b8ecf"
checksum = "a6cb138bb79a146c1bd460005623e142ef0181e3d0219cb493e02f7d08a35695"
[[package]]
name = "itoa"
@@ -223,17 +222,11 @@ version = "1.0.15"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "4a5f13b858c8d314ee3e8f639011f7ccefe71f97f96e50151fb991f267928e2c"
[[package]]
name = "lazy_static"
version = "1.5.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "bbd2bcb4c963f2ddae06a2efc7e9f3591312473c50c6685e1f298068316e66fe"
[[package]]
name = "libc"
version = "0.2.176"
version = "0.2.177"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "58f929b4d672ea937a23a1ab494143d968337a5f47e56d0815df1e0890ddf174"
checksum = "2874a2af47a2325c2001a6e6fad9b16a53b802102b528163885171cf92b15976"
[[package]]
name = "log"
@@ -263,9 +256,9 @@ checksum = "51d515d32fb182ee37cda2ccdcb92950d6a3c2893aa280e540671c2cd0f3b1d9"
[[package]]
name = "num_enum"
version = "0.7.4"
version = "0.7.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a973b4e44ce6cad84ce69d797acf9a044532e4184c4f267913d1b546a0727b7a"
checksum = "b1207a7e20ad57b847bbddc6776b968420d38292bbfe2089accff5e19e82454c"
dependencies = [
"num_enum_derive",
"rustversion",
@@ -273,9 +266,9 @@ dependencies = [
[[package]]
name = "num_enum_derive"
version = "0.7.4"
version = "0.7.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "77e878c846a8abae00dd069496dbe8751b16ac1c3d6bd2a7283a938e8228f90d"
checksum = "ff32365de1b6743cb203b710788263c44a03de03802daf96092f2da4fe6ba4d7"
dependencies = [
"proc-macro2",
"quote",
@@ -303,9 +296,9 @@ dependencies = [
[[package]]
name = "once_cell_polyfill"
version = "1.70.1"
version = "1.70.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a4895175b425cb1f87721b59f0f286c2092bd4af812243672510e1ac53e2e0ad"
checksum = "384b8ab6d37215f3c5301a95a4accb5d64aa607f1fcb26a11b5303878451b4fe"
[[package]]
name = "portable-atomic"
@@ -343,9 +336,9 @@ dependencies = [
[[package]]
name = "proc-macro2"
version = "1.0.101"
version = "1.0.103"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "89ae43fd86e4158d6db51ad8e2b80f313af9cc74f5c0e03ccb87de09998732de"
checksum = "5ee95bc4ef87b8d5ba32e8b7714ccc834865276eab0aed5c9958d00ec45f49e8"
dependencies = [
"unicode-ident",
]
@@ -361,9 +354,9 @@ dependencies = [
[[package]]
name = "regex"
version = "1.11.3"
version = "1.12.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "8b5288124840bee7b386bc413c487869b360b2b4ec421ea56425128692f2a82c"
checksum = "843bc0191f75f3e22651ae5f1e72939ab2f72a4bc30fa80a066bd66edefc24d4"
dependencies = [
"aho-corasick",
"memchr",
@@ -373,9 +366,9 @@ dependencies = [
[[package]]
name = "regex-automata"
version = "0.4.11"
version = "0.4.13"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "833eb9ce86d40ef33cb1306d8accf7bc8ec2bfea4355cbdebb3df68b40925cad"
checksum = "5276caf25ac86c8d810222b3dbb938e512c55c6831a10f3e6ed1c93b84041f1c"
dependencies = [
"aho-corasick",
"memchr",
@@ -384,9 +377,9 @@ dependencies = [
[[package]]
name = "regex-syntax"
version = "0.8.6"
version = "0.8.8"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "caf4aa5b0f434c91fe5c7f1ecb6a5ece2130b02ad2a590589dda5146df959001"
checksum = "7a2d987857b319362043e95f5353c0535c1f58eec5336fdfcf626430af7def58"
[[package]]
name = "rustversion"
@@ -425,14 +418,14 @@ dependencies = [
[[package]]
name = "simple_logger"
version = "5.0.0"
version = "5.1.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e8c5dfa5e08767553704aa0ffd9d9794d527103c736aba9854773851fd7497eb"
checksum = "291bee647ce7310b0ea721bfd7e0525517b4468eb7c7e15eb8bd774343179702"
dependencies = [
"colored",
"log",
"time",
"windows-sys 0.48.0",
"windows-sys 0.61.2",
]
[[package]]
@@ -449,9 +442,9 @@ checksum = "7da8b5736845d9f2fcb837ea5d9e2628564b3b043a70948a3f0b778838c5fb4f"
[[package]]
name = "syn"
version = "2.0.106"
version = "2.0.108"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ede7c438028d4436d71104916910f5bb611972c5cfd7f89b8300a8186e6fada6"
checksum = "da58917d35242480a05c2897064da0a80589a2a0476c9a3f2fdc83b53502e917"
dependencies = [
"proc-macro2",
"quote",
@@ -513,9 +506,9 @@ dependencies = [
[[package]]
name = "unicode-ident"
version = "1.0.19"
version = "1.0.20"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "f63a545481291138910575129486daeaf8ac54aee4387fe7906919f7830c7d9d"
checksum = "462eeb75aeb73aea900253ce739c8e18a67423fadf006037cd3ff27e82748a06"
[[package]]
name = "utf8parse"
@@ -529,15 +522,6 @@ version = "0.2.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "f0805222e57f7521d6a62e36fa9163bc891acd422f971defe97d64e70d0a4fe5"
[[package]]
name = "windows-sys"
version = "0.48.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "677d2418bec65e3338edb076e806bc1ec15693c5d0104683f2efe857f61056a9"
dependencies = [
"windows-targets 0.48.5",
]
[[package]]
name = "windows-sys"
version = "0.59.0"
@@ -557,18 +541,12 @@ dependencies = [
]
[[package]]
name = "windows-targets"
version = "0.48.5"
name = "windows-sys"
version = "0.61.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "9a2fa6e2155d7247be68c096456083145c183cbbbc2764150dda45a87197940c"
checksum = "ae137229bcbd6cdf0f7b80a31df61766145077ddf49416a728b02cb3921ff3fc"
dependencies = [
"windows_aarch64_gnullvm 0.48.5",
"windows_aarch64_msvc 0.48.5",
"windows_i686_gnu 0.48.5",
"windows_i686_msvc 0.48.5",
"windows_x86_64_gnu 0.48.5",
"windows_x86_64_gnullvm 0.48.5",
"windows_x86_64_msvc 0.48.5",
"windows-link",
]
[[package]]
@@ -604,12 +582,6 @@ dependencies = [
"windows_x86_64_msvc 0.53.1",
]
[[package]]
name = "windows_aarch64_gnullvm"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2b38e32f0abccf9987a4e3079dfb67dcd799fb61361e53e2882c3cbaf0d905d8"
[[package]]
name = "windows_aarch64_gnullvm"
version = "0.52.6"
@@ -622,12 +594,6 @@ version = "0.53.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a9d8416fa8b42f5c947f8482c43e7d89e73a173cead56d044f6a56104a6d1b53"
[[package]]
name = "windows_aarch64_msvc"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "dc35310971f3b2dbbf3f0690a219f40e2d9afcf64f9ab7cc1be722937c26b4bc"
[[package]]
name = "windows_aarch64_msvc"
version = "0.52.6"
@@ -640,12 +606,6 @@ version = "0.53.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "b9d782e804c2f632e395708e99a94275910eb9100b2114651e04744e9b125006"
[[package]]
name = "windows_i686_gnu"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "a75915e7def60c94dcef72200b9a8e58e5091744960da64ec734a6c6e9b3743e"
[[package]]
name = "windows_i686_gnu"
version = "0.52.6"
@@ -670,12 +630,6 @@ version = "0.53.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "fa7359d10048f68ab8b09fa71c3daccfb0e9b559aed648a8f95469c27057180c"
[[package]]
name = "windows_i686_msvc"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "8f55c233f70c4b27f66c523580f78f1004e8b5a8b659e05a4eb49d4166cca406"
[[package]]
name = "windows_i686_msvc"
version = "0.52.6"
@@ -688,12 +642,6 @@ version = "0.53.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "1e7ac75179f18232fe9c285163565a57ef8d3c89254a30685b57d83a38d326c2"
[[package]]
name = "windows_x86_64_gnu"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "53d40abd2583d23e4718fddf1ebec84dbff8381c07cae67ff7768bbf19c6718e"
[[package]]
name = "windows_x86_64_gnu"
version = "0.52.6"
@@ -706,12 +654,6 @@ version = "0.53.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "9c3842cdd74a865a8066ab39c8a7a473c0778a3f29370b5fd6b4b9aa7df4a499"
[[package]]
name = "windows_x86_64_gnullvm"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0b7b52767868a23d5bab768e390dc5f5c55825b6d30b86c844ff2dc7414044cc"
[[package]]
name = "windows_x86_64_gnullvm"
version = "0.52.6"
@@ -724,12 +666,6 @@ version = "0.53.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0ffa179e2d07eee8ad8f57493436566c7cc30ac536a3379fdf008f47f6bb7ae1"
[[package]]
name = "windows_x86_64_msvc"
version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "ed94fce61571a4006852b7389a063ab983c02eb1bb37b47f8272ce92d06d9538"
[[package]]
name = "windows_x86_64_msvc"
version = "0.52.6"
@@ -768,8 +704,8 @@ dependencies = [
name = "zynq7000-mmu"
version = "0.1.1"
dependencies = [
"aarch32-cpu",
"arm-targets",
"cortex-ar",
"thiserror",
]
@@ -791,8 +727,8 @@ dependencies = [
name = "zynq7000-rt"
version = "0.1.1"
dependencies = [
"aarch32-cpu",
"arbitrary-int 2.0.0",
"arm-targets",
"cortex-ar",
"zynq7000-mmu",
]

4
zynq/examples/embassy/Cargo.toml
View File

@@ -11,7 +11,7 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-ar = { version = "0.3", features = ["critical-section-single-core"] }
aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
zynq7000-rt = { path = "../../zynq7000-rt" }
zynq7000 = { path = "../../zynq7000" }
zynq7000-hal = { path = "../../zynq7000-hal" }
@@ -25,7 +25,7 @@ embedded-hal = "1"
fugit = "0.3"
log = "0.4"
embassy-executor = { git = "https://github.com/embassy-rs/embassy.git", features = [
embassy-executor = { version = "0.9", features = [
"arch-cortex-ar",
"executor-thread",
]}

1
zynq/examples/embassy/memory.x
View File

@@ -7,6 +7,7 @@ MEMORY
UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
}
REGION_ALIAS("VECTORS", CODE);
REGION_ALIAS("DATA", CODE);
SECTIONS

2
zynq/examples/embassy/src/bin/dht22-open-drain-pins.rs
View File

@@ -2,8 +2,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Delay, Duration, Ticker};
use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};

2
zynq/examples/embassy/src/bin/embassy-hello.rs
View File

@@ -1,8 +1,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

5
zynq/examples/embassy/src/bin/logger-non-blocking.rs
View File

@@ -2,8 +2,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;
@@ -70,6 +70,7 @@ async fn main(spawner: Spawner) -> ! {
uart.write_all(b"-- Zynq 7000 Logging example --\n\r")
.unwrap();
uart.flush().unwrap();
let (tx, _rx) = uart.split();
let mut logger = TxAsync::new(tx);
@@ -79,7 +80,7 @@ async fn main(spawner: Spawner) -> ! {
info!("Boot mode: {:?}", boot_mode);
let led = Output::new_for_mio(mio_pins.mio7, PinState::Low);
spawner.spawn(led_task(led).unwrap());
spawner.spawn(led_task(led)).unwrap();
let mut log_buf: [u8; 2048] = [0; 2048];
let frame_queue = zynq7000_hal::log::rb::get_frame_queue();
loop {

5
zynq/examples/embassy/src/bin/pwm.rs
View File

@@ -7,8 +7,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::{digital::StatefulOutputPin, pwm::SetDutyCycle};
@@ -80,8 +80,7 @@ async fn main(_spawner: Spawner) -> ! {
(mio_pins.mio48, mio_pins.mio49),
)
.unwrap();
uart.write_all(b"-- Zynq 7000 Embassy Hello World --\n\r")
.unwrap();
uart.write_all(b"-- Zynq 7000 PWM example--\n\r").unwrap();
// Safety: We are not multi-threaded yet.
unsafe {
zynq7000_hal::log::uart_blocking::init_unsafe_single_core(

2
zynq/examples/embassy/src/main.rs
View File

@@ -1,8 +1,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

2
zynq/examples/simple/Cargo.toml
View File

@@ -9,7 +9,7 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
license = "MIT OR Apache-2.0"
[dependencies]
cortex-ar = "0.3"
aarch32-cpu = { version = "0.1" }
zynq7000-rt = { path = "../../zynq7000-rt" }
zynq7000 = { path = "../../zynq7000" }
zynq7000-hal = { path = "../../zynq7000-hal" }

1
zynq/examples/simple/memory.x
View File

@@ -7,6 +7,7 @@ MEMORY
UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
}
REGION_ALIAS("VECTORS", CODE);
REGION_ALIAS("DATA", CODE);
SECTIONS

2
zynq/examples/simple/src/bin/blinky.rs
View File

@@ -2,8 +2,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embedded_hal::{delay::DelayNs, digital::StatefulOutputPin};
use zynq7000::Peripherals;
use zynq7000_hal::{

2
zynq/examples/simple/src/bin/gtc-ticks.rs
View File

@@ -2,8 +2,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::{panic::PanicInfo, sync::atomic::AtomicU64};
use cortex_ar::asm::nop;
use embedded_hal::digital::StatefulOutputPin;
use embedded_io::Write;
use log::{error, info};

2
zynq/examples/simple/src/bin/logger.rs
View File

@@ -2,8 +2,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::{panic::PanicInfo, sync::atomic::AtomicU64};
use cortex_ar::asm::nop;
use embedded_hal::digital::StatefulOutputPin;
use embedded_io::Write;
use log::{error, info};

4
zynq/examples/simple/src/main.rs
View File

@@ -2,8 +2,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use zynq7000_rt as _;
/// Entry point (not called like a normal main function)
@@ -18,7 +18,7 @@ pub extern "C" fn boot_core(cpu_id: u32) -> ! {
#[unsafe(export_name = "main")]
pub fn main() -> ! {
loop {
cortex_ar::asm::nop();
nop();
}
}

2
zynq/examples/zedboard/Cargo.toml
View File

@@ -11,7 +11,7 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-ar = "0.3"
aarch32-cpu = { version = "0.1" }
zynq7000-rt = { path = "../../zynq7000-rt" }
zynq7000 = { path = "../../zynq7000" }
zynq7000-hal = { path = "../../zynq7000-hal" }

1
zynq/examples/zedboard/memory.x
View File

@@ -7,6 +7,7 @@ MEMORY
UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
}
REGION_ALIAS("VECTORS", CODE);
REGION_ALIAS("DATA", CODE);
SECTIONS

2
zynq/examples/zedboard/src/bin/ethernet.rs
View File

@@ -24,8 +24,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::{net::Ipv4Addr, panic::PanicInfo};
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_net::{Ipv4Cidr, StaticConfigV4, tcp::TcpSocket, udp::UdpSocket};
use embassy_time::{Duration, Timer};

2
zynq/examples/zedboard/src/bin/l3gd20h-i2c-mio.rs
View File

@@ -8,8 +8,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Delay, Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

2
zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs
View File

@@ -9,8 +9,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Delay, Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

2
zynq/examples/zedboard/src/bin/qspi.rs
View File

@@ -1,8 +1,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

2
zynq/examples/zedboard/src/bin/uart-blocking.rs
View File

@@ -1,10 +1,10 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use axi_uart16550::AxiUart16550;
use axi_uartlite::AxiUartlite;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

2
zynq/examples/zedboard/src/bin/uart-non-blocking.rs
View File

@@ -25,11 +25,11 @@
#![no_main]
extern crate alloc;
use aarch32_cpu::asm::nop;
use alloc::format;
use axi_uart16550::AxiUart16550;
use axi_uartlite::AxiUartlite;
use core::{cell::RefCell, panic::PanicInfo};
use cortex_ar::asm::nop;
use critical_section::Mutex;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};

2
zynq/examples/zedboard/src/main.rs
View File

@@ -1,8 +1,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embassy_executor::Spawner;
use embassy_time::{Duration, Ticker};
use embedded_hal::digital::StatefulOutputPin;

2
zynq/zedboard-fsbl/Cargo.toml
View File

@@ -9,7 +9,7 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
license = "MIT OR Apache-2.0"
[dependencies]
cortex-ar = { version = "0.3", features = ["critical-section-single-core"] }
aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
zynq7000-rt = { path = "../zynq7000-rt" }
zynq7000 = { path = "../zynq7000" }
zynq7000-hal = { path = "../zynq7000-hal" }

1
zynq/zedboard-fsbl/memory.x
View File

@@ -9,6 +9,7 @@ MEMORY
UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
}
REGION_ALIAS("VECTORS", CODE);
REGION_ALIAS("DATA", CODE);
SECTIONS

12
zynq/zedboard-fsbl/src/main.rs
View File

@@ -10,7 +10,7 @@
use arbitrary_int::u6;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use aarch32_cpu::asm::nop;
use embedded_io::Write as _;
use log::{error, info};
use zedboard_bsp::qspi_spansion::{self, QspiSpansionS25Fl256SLinearMode};
@@ -178,7 +178,7 @@ pub fn main() -> ! {
qspi_boot(spansion_lqspi, priv_tim);
}
loop {
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
}
@@ -321,10 +321,10 @@ fn qspi_boot(mut qspi: QspiSpansionS25Fl256SLinearMode, _priv_tim: priv_tim::Cpu
// Some clean up and preparation for jumping to the user application.
zynq7000_hal::cache::clean_and_invalidate_data_cache();
cortex_ar::register::TlbIAll::write();
cortex_ar::register::BpIAll::write();
cortex_ar::asm::dsb();
cortex_ar::asm::isb();
aarch32_cpu::register::TlbIAll::write();
aarch32_cpu::register::BpIAll::write();
aarch32_cpu::asm::dsb();
aarch32_cpu::asm::isb();
let jump_func: extern "C" fn() -> ! = unsafe { core::mem::transmute(jump_addr) };
jump_func();

2
zynq/zedboard-qspi-flasher/Cargo.toml
View File

@@ -4,7 +4,7 @@ version = "0.1.0"
edition = "2024"
[dependencies]
cortex-ar = { version = "0.3" }
aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
zynq7000-rt = { path = "../zynq7000-rt" }
zynq7000 = { path = "../zynq7000" }
zynq7000-hal = { path = "../zynq7000-hal" }

1
zynq/zedboard-qspi-flasher/memory.x
View File

@@ -7,6 +7,7 @@ MEMORY
UNCACHED(rx): ORIGIN = 0x4000000, LENGTH = 1M
}
REGION_ALIAS("VECTORS", CODE)
REGION_ALIAS("DATA", CODE);
SECTIONS

2
zynq/zedboard-qspi-flasher/src/main.rs
View File

@@ -3,8 +3,8 @@
#![no_std]
#![no_main]
use aarch32_cpu::asm::nop;
use core::panic::PanicInfo;
use cortex_ar::asm::nop;
use embedded_hal::{delay::DelayNs as _, digital::StatefulOutputPin as _};
use embedded_io::Write as _;
use log::{error, info};

2
zynq/zynq7000-hal/Cargo.toml
View File

@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "amd", "zynq7000", "bare-metal"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-ar = { version = "0.3" }
aarch32-cpu = { version = "0.1" }
zynq7000 = { path = "../zynq7000", version = "0.1" }
zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }

6
zynq/zynq7000-hal/src/cache.rs
View File

@@ -4,7 +4,7 @@
//! L2 cache in the correct order. This module provides commonly required operations.
use core::sync::atomic::compiler_fence;
use cortex_ar::{
use aarch32_cpu::{
asm::dsb,
cache::{
clean_and_invalidate_data_cache_line_to_poc, clean_data_cache_line_to_poc,
@@ -28,7 +28,7 @@ pub fn clean_and_invalidate_l2c_line(l2c: &mut MmioRegisters<'static>, addr: u32
pub fn clean_and_invalidate_data_cache() {
dsb();
cortex_ar::cache::clean_l1_data_cache::<2, 5, 8>();
aarch32_cpu::cache::clean_l1_data_cache::<2, 5, 8>();
dsb();
// Clean all ways in L2 cache.
@@ -37,7 +37,7 @@ pub fn clean_and_invalidate_data_cache() {
while l2c.read_cache_sync().busy() {}
compiler_fence(core::sync::atomic::Ordering::SeqCst);
cortex_ar::cache::clean_and_invalidate_l1_data_cache::<2, 5, 8>();
aarch32_cpu::cache::clean_and_invalidate_l1_data_cache::<2, 5, 8>();
dsb();
}

4
zynq/zynq7000-hal/src/clocks/pll.rs
View File

@@ -346,9 +346,7 @@ unsafe fn configure_pll_unchecked(
while ((slcr.clk_ctrl().read_pll_status().raw_value() >> pll_type.bit_offset_pll_locked())
& 0b1)
!= 1
{
cortex_ar::asm::nop();
}
{}
pll_ctrl = unsafe { core::ptr::read_volatile(pll_ctrl_reg) };
pll_ctrl.set_bypass_force(false);

5
zynq/zynq7000-hal/src/ddr/ll.rs
View File

@@ -163,10 +163,7 @@ pub unsafe fn calibrate_iob_impedance(
val
});
if poll_for_done {
while !slcr.ddriob().read_dci_status().done() {
// Wait for the DDR IOB impedance calibration to complete.
cortex_ar::asm::nop();
}
while !slcr.ddriob().read_dci_status().done() {}
}
});
}

4
zynq/zynq7000-hal/src/ddr/mod.rs
View File

@@ -89,7 +89,7 @@ pub fn configure_ddr_for_ddr3(
let ddriob_shared = slcr.regs().ddriob_shared();
// Wait for DDR IOB impedance calibration to complete first.
while !ddriob_shared.read_dci_status().done() {
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
log::debug!("DDR IOB impedance calib done");
@@ -103,7 +103,7 @@ pub fn configure_ddr_for_ddr3(
!= zynq7000::ddrc::regs::OperatingMode::NormalOperation
{
// Wait for the soft reset to complete.
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
}

2
zynq/zynq7000-hal/src/eth/ll.rs
View File

@@ -226,7 +226,7 @@ impl EthernetLowLevel {
Slcr::with(|regs| {
regs.reset_ctrl().write_eth(assert_reset);
for _ in 0..cycles {
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
regs.reset_ctrl().write_eth(EthernetReset::DEFAULT);
});

2
zynq/zynq7000-hal/src/gic.rs
View File

@@ -8,7 +8,7 @@
//! - [GTC ticks](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
use arbitrary_int::prelude::*;
use cortex_ar::interrupt;
use aarch32_cpu::interrupt;
use zynq7000::gic::{
DistributorControlRegister, GicCpuInterfaceRegisters, GicDistributorRegisters,
InterfaceControl, InterruptSignalRegister, MmioGicCpuInterfaceRegisters,

2
zynq/zynq7000-hal/src/gpio/mod.rs
View File

@@ -49,7 +49,7 @@ pub fn reset() {
regs.reset_ctrl()
.write_gpio(GpioClockReset::builder().with_gpio_cpu1x_rst(true).build());
// Keep it in reset for one cycle.. not sure if this is necessary.
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
regs.reset_ctrl()
.write_gpio(GpioClockReset::builder().with_gpio_cpu1x_rst(false).build());
});

2
zynq/zynq7000-hal/src/i2c.rs
View File

@@ -658,7 +658,7 @@ pub fn reset(id: I2cId) {
// Keep it in reset for some cycles.. The TMR just mentions some small delay,
// no idea what is meant with that.
for _ in 0..3 {
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
regs.reset_ctrl().write_i2c(DualClockReset::DEFAULT);
});

6
zynq/zynq7000-hal/src/log.rs
View File

@@ -20,7 +20,7 @@ pub mod uart_blocking {
use core::cell::{Cell, RefCell, UnsafeCell};
use embedded_io::Write as _;
use cortex_ar::register::Cpsr;
use aarch32_cpu::register::Cpsr;
use critical_section::Mutex;
use log::{LevelFilter, Log, set_logger, set_max_level};
@@ -130,8 +130,8 @@ pub mod uart_blocking {
fn log(&self, record: &log::Record) {
if self.skip_in_isr.get() {
match Cpsr::read().mode().unwrap() {
cortex_ar::register::cpsr::ProcessorMode::Fiq
| cortex_ar::register::cpsr::ProcessorMode::Irq => {
aarch32_cpu::register::cpsr::ProcessorMode::Fiq
| aarch32_cpu::register::cpsr::ProcessorMode::Irq => {
return;
}
_ => {}

2
zynq/zynq7000-hal/src/priv_tim.rs
View File

@@ -27,7 +27,7 @@ impl CpuPrivateTimer {
///
/// This function can only be called once for each given core.
pub fn take(clocks: &ArmClocks) -> Option<Self> {
let mpidr = cortex_ar::register::mpidr::Mpidr::read();
let mpidr = aarch32_cpu::register::mpidr::Mpidr::read();
let core = mpidr.0 & 0xff;
if core != 0 && core != 1 {
return None;

2
zynq/zynq7000-hal/src/qspi/mod.rs
View File

@@ -678,7 +678,7 @@ pub fn reset() {
);
// Keep it in reset for some cycles.
for _ in 0..3 {
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
regs.reset_ctrl().write_lqspi(QspiResetControl::DEFAULT);
});

2
zynq/zynq7000-hal/src/spi/mod.rs
View File

@@ -1119,7 +1119,7 @@ pub fn reset(id: SpiId) {
// Keep it in reset for some cycles.. The TMR just mentions some small delay,
// no idea what is meant with that.
for _ in 0..3 {
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
}
regs.reset_ctrl().write_spi(DualRefAndClockReset::DEFAULT);
});

2
zynq/zynq7000-hal/src/uart/mod.rs
View File

@@ -645,7 +645,7 @@ pub fn reset(id: UartId) {
Slcr::with(|regs| {
regs.reset_ctrl().write_uart(assert_reset);
// Keep it in reset for one cycle.. not sure if this is necessary.
cortex_ar::asm::nop();
aarch32_cpu::asm::nop();
regs.reset_ctrl().write_uart(DualRefAndClockReset::DEFAULT);
});
}

4
zynq/zynq7000-mmu/Cargo.toml
View File

@@ -11,10 +11,10 @@ categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
thiserror = { version = "2", default-features = false }
cortex-ar = { version = "0.3" }
aarch32-cpu = { version = "0.1" }
[build-dependencies]
arm-targets = { version = "0.3" }
arm-targets = { version = "0.4" }
[features]
tools = []

6
zynq/zynq7000-mmu/src/lib.rs
View File

@@ -5,15 +5,15 @@
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
use core::cell::UnsafeCell;
use cortex_ar::mmu::L1Section;
use aarch32_cpu::mmu::L1Section;
#[cfg(all(not(feature = "tools"), arm_profile = "a"))]
use cortex_ar::{
use aarch32_cpu::{
asm::{dsb, isb},
cache::clean_and_invalidate_l1_data_cache,
mmu::SectionAttributes,
register::{BpIAll, TlbIAll},
};
use core::cell::UnsafeCell;
pub const NUM_L1_PAGE_TABLE_ENTRIES: usize = 4096;

8
zynq/zynq7000-rt/Cargo.toml
View File

@@ -11,17 +11,17 @@ keywords = ["no-std", "rt", "cortex-a", "amd", "zynq7000"]
categories = ["embedded", "no-std", "hardware-support"]
[dependencies]
cortex-a-rt = { version = "0.1", optional = true, features = ["vfp-dp"] }
cortex-ar = { version = "0.3" }
aarch32-rt = { version = "0.1", optional = true, features = ["fpu-d32"] }
aarch32-cpu = { version = "0.1" }
arbitrary-int = "2"
zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }
[build-dependencies]
arm-targets = { version = "0.3" }
arm-targets = { version = "0.4" }
[features]
default = ["rt"]
rt = ["dep:cortex-a-rt"]
rt = ["dep:aarch32-rt"]
[package.metadata.docs.rs]
targets = ["armv7a-none-eabihf"]

2
zynq/zynq7000-rt/src/lib.rs
View File

@@ -10,7 +10,7 @@
#![no_std]
#![cfg_attr(docsrs, feature(doc_cfg))]
#[cfg(all(feature = "rt", arm_profile = "a"))]
pub use cortex_a_rt::*;
pub use aarch32_rt::*;
#[cfg(feature = "rt")]
use zynq7000_mmu::L1TableWrapper;

4
zynq/zynq7000-rt/src/mmu.rs
View File

@@ -84,10 +84,10 @@ pub mod segments {
}
pub mod section_attrs {
use arbitrary_int::u4;
use cortex_ar::mmu::{
use aarch32_cpu::mmu::{
AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
};
use arbitrary_int::u4;
pub const DEFAULT_DOMAIN: u4 = u4::new(0b0000);
// DDR is in different domain, but all domains are set as manager domains during run-time

2
zynq/zynq7000-rt/src/mmu_table.rs
View File

@@ -1,6 +1,6 @@
//! This file was auto-generated by table-gen.rs
use crate::mmu::section_attrs;
use cortex_ar::mmu::L1Section;
use aarch32_cpu::mmu::L1Section;
use zynq7000_mmu::L1Table;
/// MMU Level 1 Page table.

21
zynq/zynq7000-rt/src/rt.rs
View File

@@ -5,8 +5,8 @@
//! but does NOT provide the L2 cache initialization.
//!
//! The boot routine includes stack, MMU and .bss/.data section initialization.
use cortex_a_rt as _;
use cortex_ar::register::{Cpsr, cpsr::ProcessorMode};
use aarch32_cpu::register::{Cpsr, cpsr::ProcessorMode};
use aarch32_rt as _;
// Start-up code for Armv7-A
//
@@ -16,17 +16,6 @@ core::arch::global_asm!(
.set PSS_L2CC_BASE_ADDR, 0xF8F02000
.set PSS_SLCR_BASE_ADDR, 0xF8000000
.set RESERVED, 0x0fffff00
.set LRemap, 0xFE00000F /* set the base address of the peripheral block as not shared */
.set L2CCWay, (PSS_L2CC_BASE_ADDR + 0x077C) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_INVLD_WAY_OFFSET)*/
.set L2CCSync, (PSS_L2CC_BASE_ADDR + 0x0730) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CACHE_SYNC_OFFSET)*/
.set L2CCCrtl, (PSS_L2CC_BASE_ADDR + 0x0100) /*(PSS_L2CC_BASE_ADDR + PSS_L2CC_CNTRL_OFFSET)*/
.set L2CCAuxCrtl, (PSS_L2CC_BASE_ADDR + 0x0104) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_AUX_CNTRL_OFFSET)*/
.set L2CCTAGLatReg, (PSS_L2CC_BASE_ADDR + 0x0108) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_TAG_RAM_CNTRL_OFFSET)*/
.set L2CCDataLatReg, (PSS_L2CC_BASE_ADDR + 0x010C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_DATA_RAM_CNTRL_OFFSET)*/
.set L2CCIntClear, (PSS_L2CC_BASE_ADDR + 0x0220) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_IAR_OFFSET)*/
.set L2CCIntRaw, (PSS_L2CC_BASE_ADDR + 0x021C) /*(PSS_L2CC_BASE_ADDR + XPSS_L2CC_ISR_OFFSET)*/
.set SLCRlockReg, (PSS_SLCR_BASE_ADDR + 0x04) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_LOCK_OFFSET)*/
.set SLCRUnlockReg, (PSS_SLCR_BASE_ADDR + 0x08) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_UNLOCK_OFFSET)*/
.set SLCRL2cRamReg, (PSS_SLCR_BASE_ADDR + 0xA1C) /*(PSS_SLCR_BASE_ADDR + XPSS_SLCR_L2C_RAM_OFFSET)*/
@@ -36,12 +25,6 @@ core::arch::global_asm!(
.set CRValMmuCac, 0b01000000000101 /* Enable IDC, and MMU */
.set CRValHiVectorAddr, 0b10000000000000 /* Set the Vector address to high, 0xFFFF0000 */
.set L2CCAuxControl, 0x72360000 /* Enable all prefetching, Cache replacement policy, Parity enable,
Event monitor bus enable and Way Size (64 KB) */
.set L2CCControl, 0x01 /* Enable L2CC */
.set L2CCTAGLatency, 0x0111 /* latency for TAG RAM */
.set L2CCDataLatency, 0x0121 /* latency for DATA RAM */
.set SLCRlockKey, 0x767B /* SLCR lock key */
.set SLCRUnlockKey, 0xDF0D /* SLCR unlock key */
.set SLCRL2cRamConfig, 0x00020202 /* SLCR L2C ram configuration */