continue with descriptors

zynq7000-hal/src/eth/mod.rs

@@ -1,6 +1,6 @@
 use arbitrary_int::u3;
 pub use zynq7000::eth::MdcClkDiv;
-use zynq7000::eth::{GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, MmioEthernet, SpeedMode};
+use zynq7000::eth::{MmioEthernet, SpeedMode, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR};
 
 pub use ll::{ClkConfig, EthernetLowLevel};
 
@@ -14,11 +14,11 @@ use crate::gpio::mio::{
     Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27,
 };
 use crate::gpio::{
-    IoPeriphPin,
     mio::{
         Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio52,
         Mio53, MioPinMarker, MuxConf, Pin,
     },
+    IoPeriphPin,
 };
 
 pub const MUX_CONF_PHY: MuxConf = MuxConf::new_with_l0();
@@ -390,9 +390,11 @@ impl Ethernet {
     }
 }
 
-#[bitbybit::bitenum(u1, exhaustive = true)]
-#[derive(Debug, PartialEq, Eq)]
-pub(crate) enum Ownership {
-    Hardware = 0,
-    Software = 1,
+mod shared {
+    #[bitbybit::bitenum(u1, exhaustive = true)]
+    #[derive(Debug, PartialEq, Eq)]
+    pub enum Ownership {
+        Hardware = 0,
+        Software = 1,
+    }
 }

zynq7000-hal/src/eth/rx_descr.rs

@@ -1,5 +1,5 @@
 //! RX buffer descriptor module.
-pub use super::Ownership;
+pub use super::shared::Ownership;
 use arbitrary_int::{u2, u3, u13, u30};
 
 /// RX buffer descriptor.

zynq7000-hal/src/eth/tx_descr.rs

@@ -1,6 +1,6 @@
 use arbitrary_int::u14;
 
-pub use super::Ownership;
+pub use super::shared::Ownership;
 
 /// RX buffer descriptor.
 ///