continue with descriptors
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42335ab8c1
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@ -1,6 +1,6 @@
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use arbitrary_int::u3;
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pub use zynq7000::eth::MdcClkDiv;
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use zynq7000::eth::{GEM_0_BASE_ADDR, GEM_1_BASE_ADDR, MmioEthernet, SpeedMode};
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use zynq7000::eth::{MmioEthernet, SpeedMode, GEM_0_BASE_ADDR, GEM_1_BASE_ADDR};
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pub use ll::{ClkConfig, EthernetLowLevel};
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@ -14,11 +14,11 @@ use crate::gpio::mio::{
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Mio16, Mio17, Mio18, Mio19, Mio20, Mio21, Mio22, Mio23, Mio24, Mio25, Mio26, Mio27,
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};
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use crate::gpio::{
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IoPeriphPin,
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mio::{
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Mio28, Mio29, Mio30, Mio31, Mio32, Mio33, Mio34, Mio35, Mio36, Mio37, Mio38, Mio39, Mio52,
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Mio53, MioPinMarker, MuxConf, Pin,
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},
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IoPeriphPin,
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};
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pub const MUX_CONF_PHY: MuxConf = MuxConf::new_with_l0();
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@ -390,9 +390,11 @@ impl Ethernet {
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}
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}
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub(crate) enum Ownership {
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Hardware = 0,
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Software = 1,
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mod shared {
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#[bitbybit::bitenum(u1, exhaustive = true)]
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#[derive(Debug, PartialEq, Eq)]
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pub enum Ownership {
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Hardware = 0,
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Software = 1,
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}
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}
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@ -1,5 +1,5 @@
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//! RX buffer descriptor module.
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pub use super::Ownership;
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pub use super::shared::Ownership;
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use arbitrary_int::{u2, u3, u13, u30};
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/// RX buffer descriptor.
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@ -1,6 +1,6 @@
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use arbitrary_int::u14;
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pub use super::Ownership;
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pub use super::shared::Ownership;
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/// RX buffer descriptor.
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///
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