bump aarch32 deps

firmware/examples/defmt/Cargo.toml

@@ -9,7 +9,7 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
 license = "MIT OR Apache-2.0"
 
 [dependencies]
-aarch32-cpu = { version = "0.2" }
+aarch32-cpu = { version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal", features = ["defmt"] }
@@ -17,5 +17,5 @@ defmt = "1"
 defmt-rtt = "1"
 embedded-io = "0.7"
 embedded-hal = "1"
-fugit = "0.3"
+fugit = "0.4"
 log = "0.4"

firmware/examples/defmt/memory.x

@@ -27,3 +27,10 @@ SECTIONS
     _ebss_uncached = .;
   } > UNCACHED
 }
+
+
+PROVIDE(_und_stack_size = 2K);
+PROVIDE(_svc_stack_size = 2K);
+PROVIDE(_abt_stack_size = 2K);
+PROVIDE(_hyp_stack_size = 1K);
+PROVIDE(_sys_stack_size = 32K);

firmware/examples/embassy/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-aarch32-cpu = { version = "0.2", features = ["critical-section-single-core"] }
+aarch32-cpu = { version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
@@ -24,7 +24,7 @@ critical-section = "1"
 heapless = "0.9"
 embedded-io = "0.7"
 embedded-hal = "1"
-fugit = "0.3"
+fugit = "0.4"
 log = "0.4"
 
 embassy-executor = { version = "0.10", features = [

firmware/examples/simple/Cargo.toml

@@ -9,11 +9,11 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
 license = "MIT OR Apache-2.0"
 
 [dependencies]
-aarch32-cpu = { version = "0.2" }
+aarch32-cpu = { version = "0.3" }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
 embedded-io = "0.7"
 embedded-hal = "1"
-fugit = "0.3"
+fugit = "0.4"
 log = "0.4"

firmware/examples/simple/memory.x

@@ -23,3 +23,9 @@ SECTIONS
     _ebss_uncached = .;
   } > UNCACHED
 }
+
+PROVIDE(_und_stack_size = 2K);
+PROVIDE(_svc_stack_size = 2K);
+PROVIDE(_abt_stack_size = 2K);
+PROVIDE(_hyp_stack_size = 1K);
+PROVIDE(_sys_stack_size = 32K);

firmware/examples/zedboard/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-aarch32-cpu = { version = "0.2", features = ["critical-section-single-core"] }
+aarch32-cpu = { version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../../zynq7000-rt" }
 zynq7000 = { path = "../../zynq7000" }
 zynq7000-hal = { path = "../../zynq7000-hal" }
@@ -30,7 +30,8 @@ embedded-hal = "1"
 embedded-hal-bus = "0.3"
 embedded-hal-async = "1"
 dummy-pin = "1"
-fugit = "0.3"
+fugit = "0.4"
+fugit-03 = { version = "0.3", package = "fugit" }
 embedded-graphics = "0.8"
 log = "0.4"
 ssd1306 = { version = "0.10" }

firmware/examples/zedboard/memory.x

@@ -23,3 +23,10 @@ SECTIONS
     _ebss_uncached = .;
   } > UNCACHED
 }
+
+PROVIDE(_und_stack_size = 2K);
+PROVIDE(_svc_stack_size = 2K);
+PROVIDE(_abt_stack_size = 2K);
+PROVIDE(_hyp_stack_size = 1K);
+PROVIDE(_irq_stack_size = 2K);
+PROVIDE(_sys_stack_size = 32K);

firmware/examples/zedboard/src/bin/l3gd20h-spi-mio.rs

@@ -64,8 +64,8 @@ async fn main(spawner: Spawner) -> ! {
     spi::configure_spi_ref_clock(&mut clocks, target_spi_ref_clock);
 
     assert!(
-        clocks.io_clocks().spi_clk().raw()
-            > (clocks.arm_clocks().cpu_1x_clk().raw() as f32 * 1.2) as u32,
+        clocks.io_clocks().spi_clk().to_raw()
+            > (clocks.arm_clocks().cpu_1x_clk().to_raw() as f32 * 1.2) as u32,
         "SPI reference clock must be larger than CPU 1x clock"
     );
 
@@ -129,12 +129,12 @@ async fn main(spawner: Spawner) -> ! {
     )
     .unwrap();
     let sclk = Hertz::from_raw(
-        clocks.io_clocks().spi_clk().raw() / zynq7000::spi::BaudDivSel::By64.div_value() as u32,
+        clocks.io_clocks().spi_clk().to_raw() / zynq7000::spi::BaudDivSel::By64.div_value() as u32,
     );
     let mod_id = spi.regs().read_mod_id();
     assert_eq!(mod_id, spi::MODULE_ID);
     assert!(sclk <= Hertz::from_raw(10_000_000));
-    let min_delay = (sclk.raw() * 5) / 1_000_000_000;
+    let min_delay = (sclk.to_raw() * 5) / 1_000_000_000;
     spi.inner().configure_delays(
         DelayControl::builder()
             .with_inter_word_cs_deassert(0)

firmware/examples/zedboard/src/bin/oled.rs

@@ -52,8 +52,8 @@ async fn main(spawner: Spawner) -> ! {
     spi::configure_spi_ref_clock(&mut clocks, target_spi_ref_clock);
 
     assert!(
-        clocks.io_clocks().spi_clk().raw()
-            > (clocks.arm_clocks().cpu_1x_clk().raw() as f32 * 1.2) as u32,
+        clocks.io_clocks().spi_clk().to_raw()
+            > (clocks.arm_clocks().cpu_1x_clk().to_raw() as f32 * 1.2) as u32,
         "SPI reference clock must be larger than CPU 1x clock"
     );
 

firmware/examples/zedboard/src/bin/uart-blocking.rs

@@ -9,7 +9,6 @@ use embassy_executor::Spawner;
 use embassy_time::{Duration, Ticker};
 use embedded_hal::digital::StatefulOutputPin;
 use embedded_io::Write;
-use fugit::RateExtU32;
 use log::{error, info};
 use zedboard::PS_CLOCK_FREQUENCY;
 use zynq7000_hal::{
@@ -147,7 +146,8 @@ async fn main(_spawner: Spawner) -> ! {
 
     // TODO: Can we determine/read the clock frequency to the FPGAs as well?
     let (clk_config, error) =
-        axi_uart16550::ClockConfig::new_autocalc_with_error(100.MHz(), 115200).unwrap();
+        axi_uart16550::ClockConfig::new_autocalc_with_error(fugit_03::HertzU32::MHz(100), 115200)
+            .unwrap();
     assert!(error < 0.02);
     let mut uart_16550 = unsafe {
         AxiUart16550::new(

firmware/examples/zedboard/src/bin/uart-non-blocking.rs

@@ -240,8 +240,11 @@ async fn main(spawner: Spawner) -> ! {
     // used for both TX and RX, so the API is only exposed for this structure.
     uartlite.enable_interrupt();
 
-    let (clk_config, error) =
-        axi_uart16550::ClockConfig::new_autocalc_with_error(clocks.pl_clocks()[0], 115200).unwrap();
+    let (clk_config, error) = axi_uart16550::ClockConfig::new_autocalc_with_error(
+        fugit_03::HertzU32::from_raw(clocks.pl_clocks()[0].to_raw()),
+        115200,
+    )
+    .unwrap();
     assert!(error < 0.02);
     let _uart_16550 = unsafe {
         AxiUart16550::new(

firmware/gdb.gdb

@@ -5,4 +5,4 @@ break main
 
 load
 
-continue
+# continue

firmware/zedboard-fsbl/Cargo.toml

@@ -9,7 +9,7 @@ repository = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
 license = "MIT OR Apache-2.0"
 
 [dependencies]
-aarch32-cpu = { version = "0.2", features = ["critical-section-single-core"] }
+aarch32-cpu = { version = "0.3", features = ["critical-section-single-core"] }
 zynq7000-rt = { path = "../zynq7000-rt" }
 zynq7000 = { path = "../zynq7000" }
 zynq7000-hal = { path = "../zynq7000-hal" }
@@ -17,7 +17,7 @@ zynq7000-boot-image = { path = "../../host/zynq7000-boot-image" }
 zedboard-bsp = { path = "../zedboard-bsp" }
 embedded-io = "0.7"
 embedded-hal = "1"
-fugit = "0.3"
+fugit = "0.4"
 log = "0.4"
 arbitrary-int = "2"
 

firmware/zedboard-fsbl/memory.x

@@ -25,3 +25,9 @@ SECTIONS
     _ebss_uncached = .;
   } > UNCACHED
 }
+
+PROVIDE(_und_stack_size = 2K);
+PROVIDE(_svc_stack_size = 2K);
+PROVIDE(_abt_stack_size = 2K);
+PROVIDE(_hyp_stack_size = 2K);
+PROVIDE(_sys_stack_size = 32K);

firmware/zedboard-fsbl/src/main.rs

@@ -44,7 +44,7 @@ const IO_CLK: Hertz = Hertz::from_raw(1_000_000_000);
 const DDR_FREQUENCY: Hertz = Hertz::from_raw(533_333_333);
 
 /// 1067 MHz.
-const DDR_CLK: Hertz = Hertz::from_raw(2 * DDR_FREQUENCY.raw());
+const DDR_CLK: Hertz = Hertz::from_raw(2 * DDR_FREQUENCY.to_raw());
 
 const PERFORM_DDR_MEMTEST: bool = false;
 

firmware/zynq7000-embassy/src/lib.rs

@@ -68,7 +68,7 @@ impl GtcTimerDriver {
     pub unsafe fn init(&'static self, arm_clock: &ArmClocks, mut gtc: GlobalTimerCounter) {
         CPU_3X2X_CLK.set(arm_clock.cpu_3x2x_clk()).unwrap();
         SCALE
-            .set(arm_clock.cpu_3x2x_clk().raw() as u64 / TICK_HZ)
+            .set(arm_clock.cpu_3x2x_clk().to_raw() as u64 / TICK_HZ)
             .unwrap();
         gtc.set_cpu_3x2x_clock(arm_clock.cpu_3x2x_clk());
         gtc.set_prescaler(0);

firmware/zynq7000-hal/Cargo.toml

@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "amd", "zynq7000", "bare-metal"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-aarch32-cpu = { version = "0.2" }
+aarch32-cpu = { version = "0.3" }
 zynq7000 = { path = "../zynq7000", version = "0.2" }
 zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }
 static_assertions = "1.1"
@@ -29,7 +29,7 @@ static_cell = "2"
 delegate = "0.13"
 pastey = "0.2.1"
 nb = "1"
-fugit = "0.3"
+fugit = "0.4"
 critical-section = "1"
 libm = "0.2"
 log = "0.4"

firmware/zynq7000-hal/src/clocks/pll.rs

@@ -38,7 +38,7 @@ impl PllConfig {
         ps_clk: Hertz,
         target_clk: Hertz,
     ) -> Result<Self, PllConfigCtorError> {
-        if ps_clk.raw() == 0 {
+        if ps_clk.to_raw() == 0 {
             return Err(PllConfigCtorError::InvalidInput);
         }
         let mul = target_clk / ps_clk;

firmware/zynq7000-hal/src/ddr/ll.rs

@@ -28,7 +28,7 @@ pub fn calculate_dci_divisors(ddr_clks: &DdrClocks) -> DciClkConfig {
 
 /// Calculate the required DCI divisors for the given DDR clock frequency.
 pub fn calculate_dci_divisors_with_ddr_clk(ddr_clk: Hertz) -> DciClkConfig {
-    let target_div = ddr_clk.raw().div_ceil(DCI_MAX_FREQ.raw());
+    let target_div = ddr_clk.to_raw().div_ceil(DCI_MAX_FREQ.to_raw());
     let mut config = DciClkConfig {
         div0: u6::new(u6::MAX.value()),
         div1: u6::new(u6::MAX.value()),

firmware/zynq7000-hal/src/eth/ll.rs

@@ -69,8 +69,8 @@ impl ClockDivisors {
         let mut best_div_1 = u6::new(0);
         for div_1 in 1..=u6::MAX.as_usize() {
             for div_0 in 1..=u6::MAX.as_usize() {
-                let clk_rate = ref_clk.raw() / div_0 as u32 / div_1 as u32;
-                let diff = (target_speed.raw() as i64 - clk_rate as i64).unsigned_abs() as u32;
+                let clk_rate = ref_clk.to_raw() / div_0 as u32 / div_1 as u32;
+                let diff = (target_speed.to_raw() as i64 - clk_rate as i64).unsigned_abs() as u32;
                 if diff < smallest_diff {
                     smallest_diff = diff;
                     best_div_0 = u6::new(div_0 as u8);

firmware/zynq7000-hal/src/eth/mod.rs

@@ -179,7 +179,10 @@ impl Eth1RxData3Pin for Pin<Mio38> {}
 /// Calculate the CPU 1x clock divisor required to achieve a clock speed which is below
 /// 2.5 MHz, as specified by the 802.3 standard.
 pub fn calculate_mdc_clk_div(arm_clks: &ArmClocks) -> Option<MdcClockDivisor> {
-    let div = arm_clks.cpu_1x_clk().raw().div_ceil(MAX_MDC_SPEED.raw());
+    let div = arm_clks
+        .cpu_1x_clk()
+        .to_raw()
+        .div_ceil(MAX_MDC_SPEED.to_raw());
     match div {
         0..8 => Some(MdcClockDivisor::Div8),
         8..16 => Some(MdcClockDivisor::Div16),

firmware/zynq7000-hal/src/gtc.rs

@@ -18,8 +18,8 @@ unsafe impl Send for GlobalTimerCounter {}
 
 /// Convert a frequency to GTC ticks given a clock frequency.
 pub const fn frequency_to_ticks(clock: Hertz, frequency: Hertz) -> u32 {
-    if frequency.raw() != 0 {
-        clock.raw().div_ceil(frequency.raw())
+    if frequency.to_raw() != 0 {
+        clock.to_raw().div_ceil(frequency.to_raw())
     } else {
         0
     }
@@ -171,7 +171,7 @@ impl embedded_hal::delay::DelayNs for GlobalTimerCounter {
             return;
         }
         let end_of_delay = self.read_timer()
-            + (((ns as u64) * self.cpu_3x2x_clock.unwrap().raw() as u64) / 1_000_000_000);
+            + (((ns as u64) * self.cpu_3x2x_clock.unwrap().to_raw() as u64) / 1_000_000_000);
         while self.read_timer() < end_of_delay {}
     }
 }

firmware/zynq7000-hal/src/i2c.rs

@@ -266,7 +266,8 @@ pub fn calculate_divisors(
     for divisor_a in 1..=4 {
         for divisor_b in 1..=64 {
             let i2c_clock = cpu_1x_clk / (22 * divisor_a * divisor_b);
-            let deviation = (target_speed.raw() as i32 - i2c_clock.raw() as i32).unsigned_abs();
+            let deviation =
+                (target_speed.to_raw() as i32 - i2c_clock.to_raw() as i32).unsigned_abs();
             if deviation < smallest_deviation {
                 smallest_deviation = deviation;
                 best_div_a = divisor_a;
@@ -678,8 +679,8 @@ mod tests {
         assert_eq!(clk_cfg.div_a(), 0);
         assert_eq!(clk_cfg.div_b(), 55);
         let speed = calculate_i2c_speed(111.MHz(), clk_cfg);
-        assert!(speed.raw() < 100_000);
-        assert!(speed.raw() > 85_000);
+        assert!(speed.to_raw() < 100_000);
+        assert!(speed.to_raw() > 85_000);
     }
 
     #[test]
@@ -688,8 +689,8 @@ mod tests {
         assert_eq!(clk_cfg.div_a(), 0);
         assert_eq!(clk_cfg.div_b(), 12);
         let speed = calculate_i2c_speed(111.MHz(), clk_cfg);
-        assert!(speed.raw() < 400_000);
-        assert!(speed.raw() > 360_000);
+        assert!(speed.to_raw() < 400_000);
+        assert!(speed.to_raw() > 360_000);
     }
 
     #[test]
@@ -698,8 +699,8 @@ mod tests {
         assert_eq!(clk_cfg.div_a(), 1);
         assert_eq!(clk_cfg.div_b(), 33);
         let speed = calculate_i2c_speed(133.MHz(), clk_cfg);
-        assert!(speed.raw() < 100_000);
-        assert!(speed.raw() > 85_000);
+        assert!(speed.to_raw() < 100_000);
+        assert!(speed.to_raw() > 85_000);
     }
 
     #[test]
@@ -708,7 +709,7 @@ mod tests {
         assert_eq!(clk_cfg.div_a(), 0);
         assert_eq!(clk_cfg.div_b(), 15);
         let speed = calculate_i2c_speed(133.MHz(), clk_cfg);
-        assert!(speed.raw() < 400_000);
-        assert!(speed.raw() > 360_000);
+        assert!(speed.to_raw() < 400_000);
+        assert!(speed.to_raw() > 360_000);
     }
 }

firmware/zynq7000-hal/src/priv_tim.rs

@@ -76,7 +76,7 @@ impl embedded_hal::delay::DelayNs for CpuPrivateTimer {
     fn delay_ns(&mut self, ns: u32) {
         // Even for a value of 1000 MHz for CPU 3x2x and u32::MAX for nanoseconds, this will
         // never overflow.
-        let ticks = (ns as u64 * self.cpu_3x2x_clock.raw() as u64) / 1_000_000_000;
+        let ticks = (ns as u64 * self.cpu_3x2x_clock.to_raw() as u64) / 1_000_000_000;
 
         // Split the total delay into manageable chunks (u32::MAX ticks max).
         let mut remaining = ticks;

firmware/zynq7000-hal/src/qspi/mod.rs

@@ -212,7 +212,7 @@ impl ClockConfig {
             SrcSelIo::ArmPll => clocks.arm_clocks().ref_clk(),
             SrcSelIo::DdrPll => clocks.ddr_clocks().ref_clk(),
         };
-        let ref_clk_div = ref_clk.raw().div_ceil(target_ref_clock.raw());
+        let ref_clk_div = ref_clk.to_raw().div_ceil(target_ref_clock.to_raw());
         if ref_clk_div > u6::MAX.as_u32() {
             return Err(ClockCalculationError::RefDivOutOfRange);
         }
@@ -239,24 +239,24 @@ impl ClockConfig {
                 clocks
                     .io_clocks()
                     .ref_clk()
-                    .raw()
-                    .div_ceil(target_qspi_ref_clock.raw()),
+                    .to_raw()
+                    .div_ceil(target_qspi_ref_clock.to_raw()),
                 clocks.io_clocks().ref_clk(),
             ),
             SrcSelIo::ArmPll => (
                 clocks
                     .arm_clocks()
                     .ref_clk()
-                    .raw()
-                    .div_ceil(target_qspi_ref_clock.raw()),
+                    .to_raw()
+                    .div_ceil(target_qspi_ref_clock.to_raw()),
                 clocks.arm_clocks().ref_clk(),
             ),
             SrcSelIo::DdrPll => (
                 clocks
                     .ddr_clocks()
                     .ref_clk()
-                    .raw()
-                    .div_ceil(target_qspi_ref_clock.raw()),
+                    .to_raw()
+                    .div_ceil(target_qspi_ref_clock.to_raw()),
                 clocks.ddr_clocks().ref_clk(),
             ),
         };
@@ -268,8 +268,8 @@ impl ClockConfig {
             return Err(ClockCalculationError::RefClockSmallerThanCpu1xClock);
         }
         let qspi_baud_rate_div = qspi_ref_clk
-            .raw()
-            .div_ceil(target_qspi_interface_clock.raw());
+            .to_raw()
+            .div_ceil(target_qspi_interface_clock.to_raw());
         let baud_rate_div = match qspi_baud_rate_div {
             0..=2 => BaudRateDivisor::_2,
             3..=4 => BaudRateDivisor::_4,

firmware/zynq7000-hal/src/sd/mod.rs

@@ -308,8 +308,10 @@ impl SdioDivisors {
             129.. => SdClockDivisor::Div256,
         };
         Self {
-            divisor_init_phase: divisor_select_from_value(ref_clk.raw().div_ceil(INIT_CLOCK_HZ)),
-            divisor_normal: divisor_select_from_value(ref_clk.raw().div_ceil(target_speed.raw())),
+            divisor_init_phase: divisor_select_from_value(ref_clk.to_raw().div_ceil(INIT_CLOCK_HZ)),
+            divisor_normal: divisor_select_from_value(
+                ref_clk.to_raw().div_ceil(target_speed.to_raw()),
+            ),
         }
     }
 
@@ -354,7 +356,7 @@ impl SdClockConfig {
         target_sd_speed: Hertz,
     ) -> Option<Self> {
         let ref_clk = io_clocks.ref_clk();
-        let io_ref_clock_divisor = ref_clk.raw().div_ceil(target_ref_clock.raw());
+        let io_ref_clock_divisor = ref_clk.to_raw().div_ceil(target_ref_clock.to_raw());
         if io_ref_clock_divisor > u6::MAX.as_u32() {
             return None;
         }

firmware/zynq7000-hal/src/spi/mod.rs

@@ -389,7 +389,7 @@ impl Config {
         init_mode: Mode,
         ss_config: SlaveSelectConfig,
     ) -> Self {
-        let divisor_raw = io_clock.spi_clk().raw().div_ceil(target_clock.raw());
+        let divisor_raw = io_clock.spi_clk().to_raw().div_ceil(target_clock.to_raw());
         let baud_div_sel = match divisor_raw {
             0..=4 => BaudDivSel::By4,
             5..=8 => BaudDivSel::By8,
@@ -1181,24 +1181,14 @@ pub fn reset(id: SpiId) {
 pub fn calculate_largest_allowed_spi_ref_clk_divisor(clks: &Clocks) -> Option<u6> {
     let slcr = unsafe { Slcr::steal() };
     let spi_clk_ctrl = slcr.regs().clk_ctrl_shared().read_spi_clk_ctrl();
-    let div = match spi_clk_ctrl.srcsel() {
+    let ref_clock = match spi_clk_ctrl.srcsel() {
         zynq7000::slcr::clocks::SrcSelIo::IoPll | zynq7000::slcr::clocks::SrcSelIo::IoPllAlt => {
-            clks.io_clocks()
-                .ref_clk()
-                .raw()
-                .div_ceil(clks.arm_clocks().cpu_1x_clk().raw())
+            clks.io_clocks().ref_clk().to_raw()
         }
-        zynq7000::slcr::clocks::SrcSelIo::ArmPll => clks
-            .arm_clocks()
-            .ref_clk()
-            .raw()
-            .div_ceil(clks.arm_clocks().cpu_1x_clk().raw()),
-        zynq7000::slcr::clocks::SrcSelIo::DdrPll => clks
-            .ddr_clocks()
-            .ref_clk()
-            .raw()
-            .div_ceil(clks.arm_clocks().cpu_1x_clk().raw()),
+        zynq7000::slcr::clocks::SrcSelIo::ArmPll => clks.arm_clocks().ref_clk().to_raw(),
+        zynq7000::slcr::clocks::SrcSelIo::DdrPll => clks.ddr_clocks().ref_clk().to_raw(),
     };
+    let div = ref_clock.div_ceil(clks.arm_clocks().cpu_1x_clk().to_raw());
     if div > u6::MAX.value() as u32 {
         return None;
     }
@@ -1216,12 +1206,12 @@ pub fn configure_spi_ref_clock(clks: &mut Clocks, target_clock: Hertz) {
     let spi_clk_ctrl = slcr.regs().clk_ctrl_shared().read_spi_clk_ctrl();
     let ref_clk = match spi_clk_ctrl.srcsel() {
         zynq7000::slcr::clocks::SrcSelIo::IoPll | zynq7000::slcr::clocks::SrcSelIo::IoPllAlt => {
-            clks.io_clocks().ref_clk().raw()
+            clks.io_clocks().ref_clk().to_raw()
         }
-        zynq7000::slcr::clocks::SrcSelIo::ArmPll => clks.arm_clocks().ref_clk().raw(),
-        zynq7000::slcr::clocks::SrcSelIo::DdrPll => clks.ddr_clocks().ref_clk().raw(),
+        zynq7000::slcr::clocks::SrcSelIo::ArmPll => clks.arm_clocks().ref_clk().to_raw(),
+        zynq7000::slcr::clocks::SrcSelIo::DdrPll => clks.ddr_clocks().ref_clk().to_raw(),
     };
-    let div = ref_clk.div_ceil(target_clock.raw());
+    let div = ref_clk.div_ceil(target_clock.to_raw());
     if div > u6::MAX.value() as u32 {
         configure_spi_ref_clock_with_divisor(clks, u6::new(div as u8));
     }

firmware/zynq7000-hal/src/ttc.rs

@@ -275,7 +275,7 @@ impl Pwm {
         ref_clk: Hertz,
         freq: Hertz,
     ) -> Result<Self, FrequencyIsZeroError> {
-        if freq.raw() == 0 {
+        if freq.to_raw() == 0 {
             return Err(FrequencyIsZeroError);
         }
         let (prescaler_reg, tick_val) = calc_prescaler_reg_and_interval_ticks(ref_clk, freq);
@@ -289,7 +289,7 @@ impl Pwm {
     ///
     /// This resets the duty cycle to 0%.
     pub fn set_frequency(&mut self, freq: Hertz) -> Result<(), FrequencyIsZeroError> {
-        if freq.raw() == 0 {
+        if freq.to_raw() == 0 {
             return Err(FrequencyIsZeroError);
         }
         let id = self.channel.id() as usize;

firmware/zynq7000-hal/src/uart/mod.rs

@@ -254,8 +254,8 @@ pub fn calculate_viable_configs(
     }
     let mut current_clk_config = ClockConfig::default();
     for bdiv in 4..u8::MAX {
-        let cd =
-            round(uart_clk.raw() as f64 / ((bdiv as u32 + 1) as f64 * target_baud as f64)) as u64;
+        let cd = round(uart_clk.to_raw() as f64 / ((bdiv as u32 + 1) as f64 * target_baud as f64))
+            as u64;
         if cd > u16::MAX as u64 {
             continue;
         }
@@ -290,8 +290,8 @@ pub fn calculate_raw_baud_cfg_smallest_error(
     let mut best_clk_config = ClockConfig::default();
     let mut smallest_error: f64 = 100.0;
     for bdiv in 4..u8::MAX {
-        let cd =
-            round(uart_clk.raw() as f64 / ((bdiv as u32 + 1) as f64 * target_baud as f64)) as u64;
+        let cd = round(uart_clk.to_raw() as f64 / ((bdiv as u32 + 1) as f64 * target_baud as f64))
+            as u64;
         if cd > u16::MAX as u64 {
             continue;
         }
@@ -369,7 +369,7 @@ impl ClockConfig {
     /// Actual baudrate.
     #[inline]
     pub fn actual_baud(&self, sel_clk: Hertz) -> f64 {
-        sel_clk.raw() as f64 / (self.cd as f64 * (self.bdiv + 1) as f64)
+        sel_clk.to_raw() as f64 / (self.cd as f64 * (self.bdiv + 1) as f64)
     }
 }
 

firmware/zynq7000-mmu/Cargo.toml

@@ -11,7 +11,7 @@ categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
 thiserror = { version = "2", default-features = false }
-aarch32-cpu = { version = "0.2" }
+aarch32-cpu = { version = "0.3" }
 
 [build-dependencies]
 arm-targets = { version = "0.4" }

firmware/zynq7000-mmu/src/lib.rs

@@ -6,7 +6,6 @@
 #![cfg_attr(docsrs, feature(doc_cfg))]
 
 use aarch32_cpu::mmu::L1Section;
-#[cfg(all(not(feature = "tools"), arm_profile = "a"))]
 use aarch32_cpu::{
     asm::{dsb, isb},
     cache::clean_and_invalidate_l1_data_cache,
@@ -39,7 +38,6 @@ impl L1TableRaw {
         self.0.as_mut_ptr() as *mut _
     }
 
-    #[cfg(all(not(feature = "tools"), arm_profile = "a"))]
     pub fn update(
         &mut self,
         addr: u32,
@@ -92,7 +90,6 @@ impl<'a> L1TableWrapper<'a> {
 }
 
 impl L1TableWrapper<'_> {
-    #[cfg(all(not(feature = "tools"), arm_profile = "a"))]
     pub fn update(
         &mut self,
         addr: u32,

firmware/zynq7000-rt/Cargo.toml

@@ -11,8 +11,8 @@ keywords = ["no-std", "rt", "cortex-a", "amd", "zynq7000"]
 categories = ["embedded", "no-std", "hardware-support"]
 
 [dependencies]
-aarch32-rt = { version = "0.2", optional = true, features = ["fpu-d32"] }
-aarch32-cpu = { version = "0.2" }
+aarch32-rt = { version = "0.3", optional = true, features = ["fpu-d32"] }
+aarch32-cpu = { version = "0.3" }
 arbitrary-int = "2"
 zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }
 

firmware/zynq7000-rt/src/mmu.rs

@@ -85,7 +85,7 @@ pub mod segments {
 
 pub mod section_attrs {
     use aarch32_cpu::mmu::{
-        AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
+        AccessPermissions, CachePolicy, MemoryRegionAttributes, SectionAttributes,
     };
     use arbitrary_int::u4;
 
@@ -103,8 +103,8 @@ pub mod section_attrs {
         domain: DDR_DOMAIN,
         execute_never: false,
         memory_attrs: MemoryRegionAttributes::CacheableMemory {
-            inner: CacheableMemoryAttribute::WriteBackWriteAlloc,
-            outer: CacheableMemoryAttribute::WriteBackWriteAlloc,
+            inner: CachePolicy::WriteBackWriteAlloc,
+            outer: CachePolicy::WriteBackWriteAlloc,
         }
         .as_raw(),
     };
@@ -157,8 +157,8 @@ pub mod section_attrs {
         domain: DEFAULT_DOMAIN,
         execute_never: false,
         memory_attrs: MemoryRegionAttributes::CacheableMemory {
-            inner: CacheableMemoryAttribute::WriteThroughNoWriteAlloc,
-            outer: CacheableMemoryAttribute::NonCacheable,
+            inner: CachePolicy::WriteThroughNoWriteAlloc,
+            outer: CachePolicy::NonCacheable,
         }
         .as_raw(),
     };

firmware/zynq7000-rt/src/rt.rs

@@ -94,6 +94,8 @@ initialize:
     bic     r0, r0, #0x1      /* clear bit 0 */
     mcr     p15, 0, r0, c1, c0, 0   /* write value back */
 
+    /* We must set the core number for this function */
+    mov     r0,#0
     bl      _stack_setup_preallocated
 
     // set scu enable bit in scu

host/Cargo.lock

@@ -2,19 +2,6 @@
 # It is not intended for manual editing.
 version = 4
 
-[[package]]
-name = "aarch32-cpu"
-version = "0.2.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1417bbf608824a44cb2fa2ad74b5ec28c0ae4c83df62a4bd2b532bf04c241ade"
-dependencies = [
- "arbitrary-int 2.0.0",
- "arm-targets",
- "bitbybit 1.4.0",
- "num_enum",
- "thiserror",
-]
-
 [[package]]
 name = "aho-corasick"
 version = "1.1.3"
@@ -86,12 +73,6 @@ version = "2.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c858caffa49edfc4ecc45a4bec37abd3e88041a2903816f10f990b7b41abc281"
 
-[[package]]
-name = "arm-targets"
-version = "0.4.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8d29a37f252452446b67d5e50dee82a6ce12781218b915244bb6507c10b72812"
-
 [[package]]
 name = "bitbybit"
 version = "1.4.0"
@@ -254,10 +235,6 @@ checksum = "f52b00d39961fc5b2736ea853c9cc86238e165017a493d1d5c8eac6bdc4cc273"
 [[package]]
 name = "mmu-table-gen"
 version = "0.1.0"
-dependencies = [
- "zynq7000-mmu",
- "zynq7000-rt",
-]
 
 [[package]]
 name = "num-conv"
@@ -265,27 +242,6 @@ version = "0.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "51d515d32fb182ee37cda2ccdcb92950d6a3c2893aa280e540671c2cd0f3b1d9"
 
-[[package]]
-name = "num_enum"
-version = "0.7.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b1207a7e20ad57b847bbddc6776b968420d38292bbfe2089accff5e19e82454c"
-dependencies = [
- "num_enum_derive",
- "rustversion",
-]
-
-[[package]]
-name = "num_enum_derive"
-version = "0.7.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ff32365de1b6743cb203b710788263c44a03de03802daf96092f2da4fe6ba4d7"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
-
 [[package]]
 name = "num_threads"
 version = "0.1.7"
@@ -711,15 +667,6 @@ dependencies = [
  "thiserror",
 ]
 
-[[package]]
-name = "zynq7000-mmu"
-version = "0.1.2"
-dependencies = [
- "aarch32-cpu",
- "arm-targets",
- "thiserror",
-]
-
 [[package]]
 name = "zynq7000-ps7init-extract"
 version = "0.1.0"
@@ -733,13 +680,3 @@ dependencies = [
  "syn",
  "zynq7000",
 ]
-
-[[package]]
-name = "zynq7000-rt"
-version = "0.2.0"
-dependencies = [
- "aarch32-cpu",
- "arbitrary-int 2.0.0",
- "arm-targets",
- "zynq7000-mmu",
-]

host/mmu-table-gen/Cargo.toml

@@ -4,5 +4,3 @@ version = "0.1.0"
 edition = "2024"
 
 [dependencies]
-zynq7000-rt = { path = "../../firmware/zynq7000-rt", default-features = false }
-zynq7000-mmu = { path = "../../firmware/zynq7000-mmu", features = ["tools"] }

host/mmu-table-gen/src/main.rs

@@ -1,8 +1,71 @@
 use std::fs::File;
 use std::io::Write;
 use std::process::Command;
-use zynq7000_rt::mmu::ONE_MB;
-pub use zynq7000_rt::mmu::segments::*;
+//use zynq7000_rt::mmu::ONE_MB;
+//pub use zynq7000_rt::mmu::segments::*;
+
+pub const MAX_DDR_SIZE: usize = 0x4000_0000;
+pub const ONE_MB: usize = 0x10_0000;
+
+pub mod offsets {
+    pub const OFFSET_DDR: usize = 0;
+    pub const OFFSET_DDR_ALL_ACCESSIBLE: usize = 0x10_0000;
+
+    pub const OFFSET_FPGA_SLAVE_0: usize = 0x4000_0000;
+    pub const OFFSET_FPGA_SLAVE_1_START: usize = 0x8000_0000;
+    pub const OFFSET_FPGA_SLAVE_1_END: usize = 0xC000_0000;
+
+    pub const OFFSET_IO_PERIPHERALS_START: usize = 0xE000_0000;
+    pub const OFFSET_IO_PERIPHERALS_END: usize = 0xE030_0000;
+
+    pub const OFFSET_NAND_MEMORY: usize = 0xE100_0000;
+    pub const OFFSET_NOR_MEMORY: usize = 0xE200_0000;
+    pub const OFFSET_SRAM_MEMORY: usize = 0xE400_0000;
+    pub const OFFSET_SMC_MEMORIES_END: usize = 0xE600_0000;
+
+    /// 0xf8000c00 to 0xf8000fff, 0xf8010000 to 0xf88fffff and
+    /// 0xf8f03000 to 0xf8ffffff are reserved  but due to granual size of
+    /// 1MB, it is not possible to define separate regions for them.
+    pub const OFFSET_AMBA_APB_START: usize = 0xF800_0000;
+    pub const OFFSET_AMBA_APB_END: usize = 0xF900_0000;
+
+    pub const OFFSET_QSPI_XIP_START: usize = 0xFC00_0000;
+    pub const OFFSET_QSPI_XIP_END: usize = 0xFE00_0000;
+
+    /// 0xfff00000 to 0xfffb0000 is reserved but due to granual size of
+    /// 1MB, it is not possible to define separate region for it
+    pub const OFFSET_OCM_MAPPED_HIGH_START: usize = 0xFFF0_0000;
+    pub const OFFSET_OCM_MAPPED_HIGH_END: u64 = 0x1_0000_0000;
+}
+
+pub mod segments {
+    pub use super::offsets::*;
+    use super::{MAX_DDR_SIZE, ONE_MB};
+
+    /// First 1 MB of DDR has special treatment, access is dependant on SCU/OCM state.
+    /// Refer to Zynq TRM UG585 p.106 for more details.
+    pub const DDR_FULL_ACCESSIBLE: usize = (MAX_DDR_SIZE - ONE_MB) / ONE_MB;
+    pub const FPGA_SLAVE: usize = (OFFSET_FPGA_SLAVE_1_START - OFFSET_FPGA_SLAVE_0) / ONE_MB;
+    pub const UNASSIGNED_0: usize =
+        (OFFSET_IO_PERIPHERALS_START - OFFSET_FPGA_SLAVE_1_END) / ONE_MB;
+    pub const IO_PERIPHS: usize =
+        (OFFSET_IO_PERIPHERALS_END - OFFSET_IO_PERIPHERALS_START) / ONE_MB;
+    pub const UNASSIGNED_1: usize = (OFFSET_NAND_MEMORY - OFFSET_IO_PERIPHERALS_END) / ONE_MB;
+    pub const NAND: usize = (OFFSET_NOR_MEMORY - OFFSET_NAND_MEMORY) / ONE_MB;
+    pub const NOR: usize = (OFFSET_SRAM_MEMORY - OFFSET_NOR_MEMORY) / ONE_MB;
+    pub const SRAM: usize = (OFFSET_SMC_MEMORIES_END - OFFSET_SRAM_MEMORY) / ONE_MB;
+    pub const SEGMENTS_UNASSIGNED_2: usize =
+        (OFFSET_AMBA_APB_START - OFFSET_SMC_MEMORIES_END) / ONE_MB;
+    pub const AMBA_APB: usize = (OFFSET_AMBA_APB_END - OFFSET_AMBA_APB_START) / ONE_MB;
+    pub const UNASSIGNED_3: usize = (OFFSET_QSPI_XIP_START - OFFSET_AMBA_APB_END) / ONE_MB;
+    pub const QSPI_XIP: usize = (OFFSET_QSPI_XIP_END - OFFSET_QSPI_XIP_START) / ONE_MB;
+    pub const UNASSIGNED_4: usize = (OFFSET_OCM_MAPPED_HIGH_START - OFFSET_QSPI_XIP_END) / ONE_MB;
+    pub const OCM_MAPPED_HIGH: usize = ((OFFSET_OCM_MAPPED_HIGH_END
+        - OFFSET_OCM_MAPPED_HIGH_START as u64)
+        / ONE_MB as u64) as usize;
+}
+
+use segments::*;
 
 macro_rules! write_l1_section {
     ($writer:expr, $offset:expr, $attr:expr) => {