IT WORKS

zynq7000/build.rs

@@ -1,4 +1,3 @@
-
 fn main() {
     println!("cargo:rerun-if-changed=build.rs");
 }

zynq7000/src/lib.rs

@@ -1,2 +1,119 @@
 //! Rust peripheral acess crate to the AMD Zynq 7000 SoCs
 #![no_std]
+
+#[derive(derive_mmio::Mmio)]
+#[repr(C)]
+pub struct Gpio {
+    /// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
+    xgpiops_data_lsw_offset: u32,
+    /// Maskable output data (GPIO bank 0, MIO, upper 16 bits)
+    xgpiops_data_msw_offset: u32,
+    /// Maskable output data (GPIO bank 1, MIO, lower 16 bits)
+    mask_data_1_lsw: u32,
+    /// Maskable output data (GPIO bank 1, MIO, upper 16 bits)
+    mask_data_1_msw: u32,
+    /// Maskable output data (GPIO bank 2, EMIO, lower 16 bits)
+    mask_data_2_lsw: u32,
+    /// Maskable output data (GPIO bank 2, EMIO, upper 16 bits)
+    mask_data_2_msw: u32,
+    /// Maskable output data (GPIO bank 3, EMIO, lower 16 bits)
+    mask_data_3_lsw: u32,
+    /// Maskable output data (GPIO bank 3, EMIO, upper 16 bits)
+    mask_data_3_msw: u32,
+    _reserved_0: [u32; 8],
+    /// Output data (GPIO bank 0, MIO)
+    xgpiops_data_offset: u32,
+    /// Output data (GPIO bank 1, MIO)
+    data_1: u32,
+    /// Output data (GPIO bank 2, EMIO)
+    data_2: u32,
+    /// Output data (GPIO bank 3, EMIO)
+    data_3: u32,
+
+    _reserved_1: [u32; 4],
+
+    /// Input data (GPIO bank 0, MIO)
+    data_0_ro: u32,
+    /// Input data (GPIO bank 1, MIO)
+    data_1_ro: u32,
+    /// Input data (GPIO bank 2, EMIO)
+    data_2_ro: u32,
+    /// Input data (GPIO bank 3, EMIO)
+    data_3_ro: u32,
+
+    _reserved_2: [u32; 101],
+
+    /// Direction mode (GPIO bank 0, MIO)
+    xgpiops_dirm_offset: u32,
+    /// Output enable (GPIO bank 0, MIO)
+    xgpiops_outen_offset: u32,
+    /// Interrupt mask status (GPIO bank 0, MIO)
+    xgpiops_intmask_offset: u32,
+    /// Interrupt enable/unmask (GPIO bank 0, MIO)
+    xgpiops_inten_offset: u32,
+    /// Interrupt disable/mask (GPIO bank 0, MIO)
+    xgpiops_intdis_offset: u32,
+    /// Interrupt status (GPIO bank 0, MIO)
+    xgpiops_intsts_offset: u32,
+    /// Interrupt type (GPIO bank 0, MIO)
+    xgpiops_inttype_offset: u32,
+    /// Interrupt polarity (GPIO bank 0, MIO)
+    xgpiops_intpol_offset: u32,
+    /// Interrupt any edge sensitivity (GPIO bank 0, MIO)
+    xgpiops_intany_offset: u32,
+
+    _reserved_3: [u32; 8],
+
+    /// Direction mode (GPIO bank 1, MIO)
+    dirm_1: u32,
+    /// Output enable (GPIO bank 1, MIO)
+    outen_1: u32,
+    /// Interrupt mask status (GPIO bank 1, MIO)
+    int_mask_1: u32,
+    /// Interrupt enable/unmask (GPIO bank 1, MIO)
+    int_en_1: u32,
+    /// Interrupt disable/mask (GPIO bank 1, MIO)
+    int_dis_1: u32,
+    /// Interrupt status (GPIO bank 1, MIO)
+    int_sts_1: u32,
+    /// Interrupt type (GPIO bank 1, MIO)
+    int_type_1: u32,
+    /// Interrupt polarity (GPIO bank 1, MIO)
+    int_pol_1: u32,
+    /// Interrupt any edge sensitivity (GPIO bank 1, MIO)
+    int_any_1: u32,
+
+    _reserved_4: [u32; 8],
+
+    /// Direction mode (GPIO bank 2, MIO)
+    dirm_2: u32,
+    /// Output enable (GPIO bank 2, MIO)
+    outen_2: u32,
+    /// Interrupt mask status (GPIO bank 2, MIO)
+    int_mask_2: u32,
+    /// Interrupt enable/unmask (GPIO bank 2, MIO)
+    int_en_2: u32,
+    /// Interrupt disable/mask (GPIO bank 2, MIO)
+    int_dis_2: u32,
+    /// Interrupt status (GPIO bank 2, MIO)
+    int_sts_2: u32,
+    /// Interrupt type (GPIO bank 2, MIO)
+    int_type_2: u32,
+    /// Interrupt polarity (GPIO bank 2, MIO)
+    int_pol_2: u32,
+    /// Interrupt any edge sensitivity (GPIO bank 2, MIO)
+    int_any_2: u32,
+}
+
+impl Gpio {
+    /// Create a new XGPIOPS GPIO MMIO instance.
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub unsafe fn new_mmio_fixed() -> MmioGpio {
+        unsafe { Self::new_mmio_at(0xE000A000) }
+    }
+}