start derive_mmio experiments
This commit is contained in:
65
Cargo.lock
generated
65
Cargo.lock
generated
@ -29,12 +29,12 @@ name = "cortex-a-rt"
|
||||
version = "0.1.0"
|
||||
dependencies = [
|
||||
"arm-targets",
|
||||
"cortex-r-a",
|
||||
"cortex-ar",
|
||||
"semihosting",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "cortex-r-a"
|
||||
name = "cortex-ar"
|
||||
version = "0.1.0"
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||||
dependencies = [
|
||||
"arbitrary-int",
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||||
@ -42,6 +42,50 @@ dependencies = [
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"bitbybit",
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]
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[[package]]
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name = "derive-mmio"
|
||||
version = "0.2.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "290d102578147eb74f297190842998dff79a70c1c242886e6c01f0b2194f8afc"
|
||||
dependencies = [
|
||||
"derive-mmio-macro",
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||||
]
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||||
|
||||
[[package]]
|
||||
name = "derive-mmio-macro"
|
||||
version = "0.2.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "7a42cb29e2388869429bcd293f8fd37218e98cce4bb8381b10993de0ddab4928"
|
||||
dependencies = [
|
||||
"proc-macro-error2",
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
"rustversion",
|
||||
"syn",
|
||||
]
|
||||
|
||||
[[package]]
|
||||
name = "proc-macro-error-attr2"
|
||||
version = "2.0.0"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "96de42df36bb9bba5542fe9f1a054b8cc87e172759a1868aa05c1f3acc89dfc5"
|
||||
dependencies = [
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
]
|
||||
|
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[[package]]
|
||||
name = "proc-macro-error2"
|
||||
version = "2.0.1"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
||||
checksum = "11ec05c52be0a07b08061f7dd003e7d7092e0472bc731b4af7bb1ef876109802"
|
||||
dependencies = [
|
||||
"proc-macro-error-attr2",
|
||||
"proc-macro2",
|
||||
"quote",
|
||||
"syn",
|
||||
]
|
||||
|
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[[package]]
|
||||
name = "proc-macro2"
|
||||
version = "1.0.93"
|
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@ -60,6 +104,12 @@ dependencies = [
|
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"proc-macro2",
|
||||
]
|
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|
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[[package]]
|
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name = "rustversion"
|
||||
version = "1.0.19"
|
||||
source = "registry+https://github.com/rust-lang/crates.io-index"
|
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checksum = "f7c45b9784283f1b2e7fb61b42047c2fd678ef0960d4f6f1eba131594cc369d4"
|
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|
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[[package]]
|
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name = "semihosting"
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||||
version = "0.1.19"
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@ -87,14 +137,21 @@ checksum = "00e2473a93778eb0bad35909dff6a10d28e63f792f16ed15e404fca9d5eeedbe"
|
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name = "zynq-examples"
|
||||
version = "0.1.0"
|
||||
dependencies = [
|
||||
"cortex-r-a",
|
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"cortex-ar",
|
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"zynq7000-rt",
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]
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|
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[[package]]
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name = "zynq7000"
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version = "0.1.0"
|
||||
dependencies = [
|
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"derive-mmio",
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]
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|
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[[package]]
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name = "zynq7000-rt"
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||||
version = "0.1.0"
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dependencies = [
|
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"cortex-a-rt",
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"cortex-r-a",
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"cortex-ar",
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]
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@ -1,7 +1,7 @@
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[workspace]
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resolver = "3"
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members = [
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# "zynq7000",
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"zynq7000",
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"zynq7000-rt",
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"zynq-examples"
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]
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@ -11,5 +11,5 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
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categories = ["embedded", "no-std", "hardware-support"]
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|
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[dependencies]
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cortex-r-a = { path = "../../cortex-r-a/cortex-r-a" }
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cortex-ar = { path = "../../cortex-ar/cortex-ar" }
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zynq7000-rt = { path = "../zynq7000-rt" }
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|
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@ -11,8 +11,8 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
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categories = ["embedded", "no-std", "hardware-support"]
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|
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[dependencies]
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cortex-a-rt = { path = "../../cortex-r-a/cortex-a-rt", optional = true, features = ["vfp-dp"] }
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cortex-r-a = { path = "../../cortex-r-a/cortex-r-a" }
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cortex-a-rt = { path = "../../cortex-ar/cortex-a-rt", optional = true, features = ["vfp-dp"] }
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cortex-ar = { path = "../../cortex-ar/cortex-ar" }
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[features]
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default = ["rt"]
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2
zynq7000-rt/regen-table.sh
Executable file
2
zynq7000-rt/regen-table.sh
Executable file
@ -0,0 +1,2 @@
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#!/bin/bash
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cargo +stable run --target $(rustc -vV | grep host | cut -d ' ' -f2) --bin table-gen --no-default-features --features tools
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@ -38,10 +38,10 @@ fn main() {
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let mut buf_writer = std::io::BufWriter::new(file);
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writeln!(
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buf_writer,
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"//! This file is auto-generated by table-gen.rs. Do not edit it!"
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"//! This file was auto-generated by table-gen.rs"
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)
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.unwrap();
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writeln!(buf_writer, "use cortex_r_a::mmu::L1Section;").unwrap();
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writeln!(buf_writer, "use cortex_ar::mmu::L1Section;").unwrap();
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writeln!(buf_writer, "use crate::mmu::{{section_attrs, L1Table}};").unwrap();
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writeln!(buf_writer, "").unwrap();
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@ -63,12 +63,12 @@ fn main() {
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"// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
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)
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.unwrap();
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writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_ddr).unwrap();
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writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
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offset += ONE_MB;
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writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
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for _ in 0..DDR_FULL_ACCESSIBLE {
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writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_ddr).unwrap();
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writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
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offset += ONE_MB;
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}
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@ -76,7 +76,7 @@ fn main() {
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for _ in 0..FPGA_SLAVE {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_fpga_slaves
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)
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.unwrap();
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@ -87,7 +87,7 @@ fn main() {
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for _ in 0..FPGA_SLAVE {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_fpga_slaves
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)
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.unwrap();
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@ -102,7 +102,7 @@ fn main() {
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||||
for _ in 0..UNASSIGNED_0 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
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)
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.unwrap();
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@ -117,7 +117,7 @@ fn main() {
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for _ in 0..IO_PERIPHS {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_shared_dev
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)
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.unwrap();
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@ -132,7 +132,7 @@ fn main() {
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for _ in 0..UNASSIGNED_1 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
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)
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.unwrap();
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@ -143,7 +143,7 @@ fn main() {
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for _ in 0..NAND {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_shared_dev
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)
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.unwrap();
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@ -154,7 +154,7 @@ fn main() {
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for _ in 0..NOR {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_shared_dev
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)
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.unwrap();
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@ -175,7 +175,7 @@ fn main() {
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for _ in 0..SEGMENTS_UNASSIGNED_2 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
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)
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.unwrap();
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@ -190,7 +190,7 @@ fn main() {
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for _ in 0..AMBA_APB {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_shared_dev
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)
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.unwrap();
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@ -205,7 +205,7 @@ fn main() {
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for _ in 0..UNASSIGNED_3 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
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)
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.unwrap();
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@ -214,7 +214,7 @@ fn main() {
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writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
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for _ in 0..QSPI_XIP {
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writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_qspi).unwrap();
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writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_qspi).unwrap();
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offset += ONE_MB;
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}
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@ -226,7 +226,7 @@ fn main() {
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for _ in 0..UNASSIGNED_4 {
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writeln!(
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buf_writer,
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"L1Section::new({}, {}).0,",
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"L1Section::new({}, {}).raw_value(),",
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offset, attr_unassigned
|
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)
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.unwrap();
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||||
@ -238,7 +238,7 @@ fn main() {
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for _ in 0..OCM_MAPPED_HIGH {
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writeln!(
|
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buf_writer,
|
||||
"L1Section::new({}, {}).0,",
|
||||
"L1Section::new({}, {}).raw_value(),",
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offset, attr_ocm_high
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)
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.unwrap();
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||||
|
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@ -84,7 +84,7 @@ pub mod segments {
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}
|
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|
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pub mod section_attrs {
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||||
use cortex_r_a::mmu::{
|
||||
use cortex_ar::mmu::{
|
||||
AccessPermissions, CacheableMemoryAttribute, MemoryRegionAttributes, SectionAttributes,
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -11,10 +11,10 @@ keywords = ["no-std", "arm", "cortex-a", "amd", "zynq7000"]
|
||||
categories = ["embedded", "no-std", "hardware-support"]
|
||||
|
||||
[dependencies]
|
||||
# cortex-ra
|
||||
vcell = "0.1.3"
|
||||
defmt = { version = "0.3", optional = true }
|
||||
critical-section = { version = "1", optional = true }
|
||||
derive-mmio = "0.2"
|
||||
# cortex-r
|
||||
# defmt = { version = "0.3", optional = true }
|
||||
# critical-section = { version = "1", optional = true }
|
||||
|
||||
[features]
|
||||
# Adds Debug implementation
|
||||
|
||||
@ -1,17 +1,4 @@
|
||||
#![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"]
|
||||
use std::env;
|
||||
use std::fs::File;
|
||||
use std::io::Write;
|
||||
use std::path::PathBuf;
|
||||
|
||||
fn main() {
|
||||
if env::var_os("CARGO_FEATURE_RT").is_some() {
|
||||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
|
||||
File::create(out.join("device.x"))
|
||||
.unwrap()
|
||||
.write_all(include_bytes!("device.x"))
|
||||
.unwrap();
|
||||
println!("cargo:rustc-link-search={}", out.display());
|
||||
println!("cargo:rerun-if-changed=device.x");
|
||||
}
|
||||
println!("cargo:rerun-if-changed=build.rs");
|
||||
}
|
||||
|
||||
@ -1,730 +0,0 @@
|
||||
use core::marker;
|
||||
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"]
|
||||
pub trait RawReg:
|
||||
Copy
|
||||
+ Default
|
||||
+ From<bool>
|
||||
+ core::ops::BitOr<Output = Self>
|
||||
+ core::ops::BitAnd<Output = Self>
|
||||
+ core::ops::BitOrAssign
|
||||
+ core::ops::BitAndAssign
|
||||
+ core::ops::Not<Output = Self>
|
||||
+ core::ops::Shl<u8, Output = Self>
|
||||
{
|
||||
#[doc = " Mask for bits of width `WI`"]
|
||||
fn mask<const WI: u8>() -> Self;
|
||||
#[doc = " Mask for bits of width 1"]
|
||||
fn one() -> Self;
|
||||
}
|
||||
macro_rules! raw_reg {
|
||||
($ U : ty , $ size : literal , $ mask : ident) => {
|
||||
impl RawReg for $U {
|
||||
#[inline(always)]
|
||||
fn mask<const WI: u8>() -> Self {
|
||||
$mask::<WI>()
|
||||
}
|
||||
#[inline(always)]
|
||||
fn one() -> Self {
|
||||
1
|
||||
}
|
||||
}
|
||||
const fn $mask<const WI: u8>() -> $U {
|
||||
<$U>::MAX >> ($size - WI)
|
||||
}
|
||||
impl FieldSpec for $U {
|
||||
type Ux = $U;
|
||||
}
|
||||
};
|
||||
}
|
||||
raw_reg!(u8, 8, mask_u8);
|
||||
raw_reg!(u16, 16, mask_u16);
|
||||
raw_reg!(u32, 32, mask_u32);
|
||||
raw_reg!(u64, 64, mask_u64);
|
||||
#[doc = " Raw register type"]
|
||||
pub trait RegisterSpec {
|
||||
#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."]
|
||||
type Ux: RawReg;
|
||||
}
|
||||
#[doc = " Raw field type"]
|
||||
pub trait FieldSpec: Sized {
|
||||
#[doc = " Raw field type (`u8`, `u16`, `u32`, ...)."]
|
||||
type Ux: Copy + core::fmt::Debug + PartialEq + From<Self>;
|
||||
}
|
||||
#[doc = " Marker for fields with fixed values"]
|
||||
pub trait IsEnum: FieldSpec {}
|
||||
#[doc = " Trait implemented by readable registers to enable the `read` method."]
|
||||
#[doc = ""]
|
||||
#[doc = " Registers marked with `Writable` can be also be `modify`'ed."]
|
||||
pub trait Readable: RegisterSpec {}
|
||||
#[doc = " Trait implemented by writeable registers."]
|
||||
#[doc = ""]
|
||||
#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."]
|
||||
#[doc = ""]
|
||||
#[doc = " Registers marked with `Readable` can be also be `modify`'ed."]
|
||||
pub trait Writable: RegisterSpec {
|
||||
#[doc = " Is it safe to write any bits to register"]
|
||||
type Safety;
|
||||
#[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"]
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
|
||||
#[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"]
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux;
|
||||
}
|
||||
#[doc = " Reset value of the register."]
|
||||
#[doc = ""]
|
||||
#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"]
|
||||
#[doc = " register by using the `reset` method."]
|
||||
pub trait Resettable: RegisterSpec {
|
||||
#[doc = " Reset value of the register."]
|
||||
const RESET_VALUE: Self::Ux;
|
||||
#[doc = " Reset value of the register."]
|
||||
#[inline(always)]
|
||||
fn reset_value() -> Self::Ux {
|
||||
Self::RESET_VALUE
|
||||
}
|
||||
}
|
||||
#[doc(hidden)]
|
||||
pub mod raw;
|
||||
#[doc = " Register reader."]
|
||||
#[doc = ""]
|
||||
#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"]
|
||||
#[doc = " method."]
|
||||
pub type R<REG> = raw::R<REG>;
|
||||
impl<REG: RegisterSpec> R<REG> {
|
||||
#[doc = " Reads raw bits from register."]
|
||||
#[inline(always)]
|
||||
pub const fn bits(&self) -> REG::Ux {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl<REG: RegisterSpec, FI> PartialEq<FI> for R<REG>
|
||||
where
|
||||
REG::Ux: PartialEq,
|
||||
FI: Copy,
|
||||
REG::Ux: From<FI>,
|
||||
{
|
||||
#[inline(always)]
|
||||
fn eq(&self, other: &FI) -> bool {
|
||||
self.bits.eq(®::Ux::from(*other))
|
||||
}
|
||||
}
|
||||
#[doc = " Register writer."]
|
||||
#[doc = ""]
|
||||
#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."]
|
||||
pub type W<REG> = raw::W<REG>;
|
||||
impl<REG: Writable> W<REG> {
|
||||
#[doc = " Writes raw bits to the register."]
|
||||
#[doc = ""]
|
||||
#[doc = " # Safety"]
|
||||
#[doc = ""]
|
||||
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
}
|
||||
impl<REG> W<REG>
|
||||
where
|
||||
REG: Writable<Safety = Safe>,
|
||||
{
|
||||
#[doc = " Writes raw bits to the register."]
|
||||
#[inline(always)]
|
||||
pub fn set(&mut self, bits: REG::Ux) -> &mut Self {
|
||||
self.bits = bits;
|
||||
self
|
||||
}
|
||||
}
|
||||
#[doc = " Field reader."]
|
||||
#[doc = ""]
|
||||
#[doc = " Result of the `read` methods of fields."]
|
||||
pub type FieldReader<FI = u8> = raw::FieldReader<FI>;
|
||||
#[doc = " Bit-wise field reader"]
|
||||
pub type BitReader<FI = bool> = raw::BitReader<FI>;
|
||||
impl<FI: FieldSpec> FieldReader<FI> {
|
||||
#[doc = " Reads raw bits from field."]
|
||||
#[inline(always)]
|
||||
pub const fn bits(&self) -> FI::Ux {
|
||||
self.bits
|
||||
}
|
||||
}
|
||||
impl<FI: FieldSpec> core::fmt::Debug for FieldReader<FI> {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||
core::fmt::Debug::fmt(&self.bits, f)
|
||||
}
|
||||
}
|
||||
impl<FI> PartialEq<FI> for FieldReader<FI>
|
||||
where
|
||||
FI: FieldSpec + Copy,
|
||||
{
|
||||
#[inline(always)]
|
||||
fn eq(&self, other: &FI) -> bool {
|
||||
self.bits.eq(&FI::Ux::from(*other))
|
||||
}
|
||||
}
|
||||
impl<FI> PartialEq<FI> for BitReader<FI>
|
||||
where
|
||||
FI: Copy,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[inline(always)]
|
||||
fn eq(&self, other: &FI) -> bool {
|
||||
self.bits.eq(&bool::from(*other))
|
||||
}
|
||||
}
|
||||
impl<FI> BitReader<FI> {
|
||||
#[doc = " Value of the field as raw bits."]
|
||||
#[inline(always)]
|
||||
pub const fn bit(&self) -> bool {
|
||||
self.bits
|
||||
}
|
||||
#[doc = " Returns `true` if the bit is clear (0)."]
|
||||
#[inline(always)]
|
||||
pub const fn bit_is_clear(&self) -> bool {
|
||||
!self.bit()
|
||||
}
|
||||
#[doc = " Returns `true` if the bit is set (1)."]
|
||||
#[inline(always)]
|
||||
pub const fn bit_is_set(&self) -> bool {
|
||||
self.bit()
|
||||
}
|
||||
}
|
||||
impl<FI> core::fmt::Debug for BitReader<FI> {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||
core::fmt::Debug::fmt(&self.bits, f)
|
||||
}
|
||||
}
|
||||
#[doc = " Marker for register/field writers which can take any value of specified width"]
|
||||
pub struct Safe;
|
||||
#[doc = " You should check that value is allowed to pass to register/field writer marked with this"]
|
||||
pub struct Unsafe;
|
||||
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
|
||||
pub struct Range<const MIN: u64, const MAX: u64>;
|
||||
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
|
||||
pub struct RangeFrom<const MIN: u64>;
|
||||
#[doc = " Marker for field writers are safe to write in specified inclusive range"]
|
||||
pub struct RangeTo<const MAX: u64>;
|
||||
#[doc = " Write field Proxy"]
|
||||
pub type FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe> =
|
||||
raw::FieldWriter<'a, REG, WI, FI, Safety>;
|
||||
impl<REG, const WI: u8, FI, Safety> FieldWriter<'_, REG, WI, FI, Safety>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
{
|
||||
#[doc = " Field width"]
|
||||
pub const WIDTH: u8 = WI;
|
||||
#[doc = " Field width"]
|
||||
#[inline(always)]
|
||||
pub const fn width(&self) -> u8 {
|
||||
WI
|
||||
}
|
||||
#[doc = " Field offset"]
|
||||
#[inline(always)]
|
||||
pub const fn offset(&self) -> u8 {
|
||||
self.o
|
||||
}
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
REG::Ux: From<FI::Ux>,
|
||||
{
|
||||
#[doc = " Writes raw bits to the field"]
|
||||
#[doc = ""]
|
||||
#[doc = " # Safety"]
|
||||
#[doc = ""]
|
||||
#[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"]
|
||||
#[inline(always)]
|
||||
pub unsafe fn bits(self, value: FI::Ux) -> &'a mut W<REG> {
|
||||
self.w.bits &= !(REG::Ux::mask::<WI>() << self.o);
|
||||
self.w.bits |= (REG::Ux::from(value) & REG::Ux::mask::<WI>()) << self.o;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI> FieldWriter<'a, REG, WI, FI, Safe>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
REG::Ux: From<FI::Ux>,
|
||||
{
|
||||
#[doc = " Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
|
||||
unsafe { self.bits(value) }
|
||||
}
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI, const MIN: u64, const MAX: u64>
|
||||
FieldWriter<'a, REG, WI, FI, Range<MIN, MAX>>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
REG::Ux: From<FI::Ux>,
|
||||
u64: From<FI::Ux>,
|
||||
{
|
||||
#[doc = " Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
|
||||
{
|
||||
let value = u64::from(value);
|
||||
assert!(value >= MIN && value <= MAX);
|
||||
}
|
||||
unsafe { self.bits(value) }
|
||||
}
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI, const MIN: u64> FieldWriter<'a, REG, WI, FI, RangeFrom<MIN>>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
REG::Ux: From<FI::Ux>,
|
||||
u64: From<FI::Ux>,
|
||||
{
|
||||
#[doc = " Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
|
||||
{
|
||||
let value = u64::from(value);
|
||||
assert!(value >= MIN);
|
||||
}
|
||||
unsafe { self.bits(value) }
|
||||
}
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI, const MAX: u64> FieldWriter<'a, REG, WI, FI, RangeTo<MAX>>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
REG::Ux: From<FI::Ux>,
|
||||
u64: From<FI::Ux>,
|
||||
{
|
||||
#[doc = " Writes raw bits to the field"]
|
||||
#[inline(always)]
|
||||
pub fn set(self, value: FI::Ux) -> &'a mut W<REG> {
|
||||
{
|
||||
let value = u64::from(value);
|
||||
assert!(value <= MAX);
|
||||
}
|
||||
unsafe { self.bits(value) }
|
||||
}
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: IsEnum,
|
||||
REG::Ux: From<FI::Ux>,
|
||||
{
|
||||
#[doc = " Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
|
||||
unsafe { self.bits(FI::Ux::from(variant)) }
|
||||
}
|
||||
}
|
||||
macro_rules! bit_proxy {
|
||||
($ writer : ident , $ mwv : ident) => {
|
||||
#[doc(hidden)]
|
||||
pub struct $mwv;
|
||||
#[doc = " Bit-wise write field proxy"]
|
||||
pub type $writer<'a, REG, FI = bool> = raw::BitWriter<'a, REG, FI, $mwv>;
|
||||
impl<'a, REG, FI> $writer<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = " Field width"]
|
||||
pub const WIDTH: u8 = 1;
|
||||
#[doc = " Field width"]
|
||||
#[inline(always)]
|
||||
pub const fn width(&self) -> u8 {
|
||||
Self::WIDTH
|
||||
}
|
||||
#[doc = " Field offset"]
|
||||
#[inline(always)]
|
||||
pub const fn offset(&self) -> u8 {
|
||||
self.o
|
||||
}
|
||||
#[doc = " Writes bit to the field"]
|
||||
#[inline(always)]
|
||||
pub fn bit(self, value: bool) -> &'a mut W<REG> {
|
||||
self.w.bits &= !(REG::Ux::one() << self.o);
|
||||
self.w.bits |= (REG::Ux::from(value) & REG::Ux::one()) << self.o;
|
||||
self.w
|
||||
}
|
||||
#[doc = " Writes `variant` to the field"]
|
||||
#[inline(always)]
|
||||
pub fn variant(self, variant: FI) -> &'a mut W<REG> {
|
||||
self.bit(bool::from(variant))
|
||||
}
|
||||
}
|
||||
};
|
||||
}
|
||||
bit_proxy!(BitWriter, BitM);
|
||||
bit_proxy!(BitWriter1S, Bit1S);
|
||||
bit_proxy!(BitWriter0C, Bit0C);
|
||||
bit_proxy!(BitWriter1C, Bit1C);
|
||||
bit_proxy!(BitWriter0S, Bit0S);
|
||||
bit_proxy!(BitWriter1T, Bit1T);
|
||||
bit_proxy!(BitWriter0T, Bit0T);
|
||||
impl<'a, REG, FI> BitWriter<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = " Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W<REG> {
|
||||
self.w.bits |= REG::Ux::one() << self.o;
|
||||
self.w
|
||||
}
|
||||
#[doc = " Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W<REG> {
|
||||
self.w.bits &= !(REG::Ux::one() << self.o);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, FI> BitWriter1S<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = " Sets the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit(self) -> &'a mut W<REG> {
|
||||
self.w.bits |= REG::Ux::one() << self.o;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, FI> BitWriter0C<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = " Clears the field bit"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit(self) -> &'a mut W<REG> {
|
||||
self.w.bits &= !(REG::Ux::one() << self.o);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, FI> BitWriter1C<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = "Clears the field bit by passing one"]
|
||||
#[inline(always)]
|
||||
pub fn clear_bit_by_one(self) -> &'a mut W<REG> {
|
||||
self.w.bits |= REG::Ux::one() << self.o;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, FI> BitWriter0S<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = "Sets the field bit by passing zero"]
|
||||
#[inline(always)]
|
||||
pub fn set_bit_by_zero(self) -> &'a mut W<REG> {
|
||||
self.w.bits &= !(REG::Ux::one() << self.o);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, FI> BitWriter1T<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = "Toggle the field bit by passing one"]
|
||||
#[inline(always)]
|
||||
pub fn toggle_bit(self) -> &'a mut W<REG> {
|
||||
self.w.bits |= REG::Ux::one() << self.o;
|
||||
self.w
|
||||
}
|
||||
}
|
||||
impl<'a, REG, FI> BitWriter0T<'a, REG, FI>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = "Toggle the field bit by passing zero"]
|
||||
#[inline(always)]
|
||||
pub fn toggle_bit(self) -> &'a mut W<REG> {
|
||||
self.w.bits &= !(REG::Ux::one() << self.o);
|
||||
self.w
|
||||
}
|
||||
}
|
||||
#[doc = " This structure provides volatile access to registers."]
|
||||
#[repr(transparent)]
|
||||
pub struct Reg<REG: RegisterSpec> {
|
||||
register: vcell::VolatileCell<REG::Ux>,
|
||||
_marker: marker::PhantomData<REG>,
|
||||
}
|
||||
unsafe impl<REG: RegisterSpec> Send for Reg<REG> where REG::Ux: Send {}
|
||||
impl<REG: RegisterSpec> Reg<REG> {
|
||||
#[doc = " Returns the underlying memory address of register."]
|
||||
#[doc = ""]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " let reg_ptr = periph.reg.as_ptr();"]
|
||||
#[doc = " ```"]
|
||||
#[inline(always)]
|
||||
pub fn as_ptr(&self) -> *mut REG::Ux {
|
||||
self.register.as_ptr()
|
||||
}
|
||||
}
|
||||
impl<REG: Readable> Reg<REG> {
|
||||
#[doc = " Reads the contents of a `Readable` register."]
|
||||
#[doc = ""]
|
||||
#[doc = " You can read the raw contents of a register by using `bits`:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " let bits = periph.reg.read().bits();"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or get the content of a particular field of a register:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " let reader = periph.reg.read();"]
|
||||
#[doc = " let bits = reader.field1().bits();"]
|
||||
#[doc = " let flag = reader.field2().bit_is_set();"]
|
||||
#[doc = " ```"]
|
||||
#[inline(always)]
|
||||
pub fn read(&self) -> R<REG> {
|
||||
R {
|
||||
bits: self.register.get(),
|
||||
_reg: marker::PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
impl<REG: Resettable + Writable> Reg<REG> {
|
||||
#[doc = " Writes the reset value to `Writable` register."]
|
||||
#[doc = ""]
|
||||
#[doc = " Resets the register to its initial state."]
|
||||
#[inline(always)]
|
||||
pub fn reset(&self) {
|
||||
self.register.set(REG::RESET_VALUE)
|
||||
}
|
||||
#[doc = " Writes bits to a `Writable` register."]
|
||||
#[doc = ""]
|
||||
#[doc = " You can write raw bits into a register:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or write only the fields you need:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.write(|w| w"]
|
||||
#[doc = " .field1().bits(newfield1bits)"]
|
||||
#[doc = " .field2().set_bit()"]
|
||||
#[doc = " .field3().variant(VARIANT)"]
|
||||
#[doc = " );"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or an alternative way of saying the same:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.write(|w| {"]
|
||||
#[doc = " w.field1().bits(newfield1bits);"]
|
||||
#[doc = " w.field2().set_bit();"]
|
||||
#[doc = " w.field3().variant(VARIANT)"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " In the latter case, other fields will be set to their reset value."]
|
||||
#[inline(always)]
|
||||
pub fn write<F>(&self, f: F) -> REG::Ux
|
||||
where
|
||||
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
|
||||
{
|
||||
let value = f(&mut W {
|
||||
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
|
||||
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
|
||||
_reg: marker::PhantomData,
|
||||
})
|
||||
.bits;
|
||||
self.register.set(value);
|
||||
value
|
||||
}
|
||||
#[doc = " Writes bits to a `Writable` register and produce a value."]
|
||||
#[doc = ""]
|
||||
#[doc = " You can write raw bits into a register:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.write_and(|w| unsafe { w.bits(rawbits); });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or write only the fields you need:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.write_and(|w| {"]
|
||||
#[doc = " w.field1().bits(newfield1bits)"]
|
||||
#[doc = " .field2().set_bit()"]
|
||||
#[doc = " .field3().variant(VARIANT);"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or an alternative way of saying the same:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.write_and(|w| {"]
|
||||
#[doc = " w.field1().bits(newfield1bits);"]
|
||||
#[doc = " w.field2().set_bit();"]
|
||||
#[doc = " w.field3().variant(VARIANT);"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " In the latter case, other fields will be set to their reset value."]
|
||||
#[doc = ""]
|
||||
#[doc = " Values can be returned from the closure:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " let state = periph.reg.write_and(|w| State::set(w.field1()));"]
|
||||
#[doc = " ```"]
|
||||
#[inline(always)]
|
||||
pub fn from_write<F, T>(&self, f: F) -> T
|
||||
where
|
||||
F: FnOnce(&mut W<REG>) -> T,
|
||||
{
|
||||
let mut writer = W {
|
||||
bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP
|
||||
| REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
|
||||
_reg: marker::PhantomData,
|
||||
};
|
||||
let result = f(&mut writer);
|
||||
self.register.set(writer.bits);
|
||||
result
|
||||
}
|
||||
}
|
||||
impl<REG: Writable> Reg<REG> {
|
||||
#[doc = " Writes 0 to a `Writable` register."]
|
||||
#[doc = ""]
|
||||
#[doc = " Similar to `write`, but unused bits will contain 0."]
|
||||
#[doc = ""]
|
||||
#[doc = " # Safety"]
|
||||
#[doc = ""]
|
||||
#[doc = " Unsafe to use with registers which don't allow to write 0."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn write_with_zero<F>(&self, f: F) -> REG::Ux
|
||||
where
|
||||
F: FnOnce(&mut W<REG>) -> &mut W<REG>,
|
||||
{
|
||||
let value = f(&mut W {
|
||||
bits: REG::Ux::default(),
|
||||
_reg: marker::PhantomData,
|
||||
})
|
||||
.bits;
|
||||
self.register.set(value);
|
||||
value
|
||||
}
|
||||
#[doc = " Writes 0 to a `Writable` register and produces a value."]
|
||||
#[doc = ""]
|
||||
#[doc = " Similar to `write`, but unused bits will contain 0."]
|
||||
#[doc = ""]
|
||||
#[doc = " # Safety"]
|
||||
#[doc = ""]
|
||||
#[doc = " Unsafe to use with registers which don't allow to write 0."]
|
||||
#[inline(always)]
|
||||
pub unsafe fn from_write_with_zero<F, T>(&self, f: F) -> T
|
||||
where
|
||||
F: FnOnce(&mut W<REG>) -> T,
|
||||
{
|
||||
let mut writer = W {
|
||||
bits: REG::Ux::default(),
|
||||
_reg: marker::PhantomData,
|
||||
};
|
||||
let result = f(&mut writer);
|
||||
self.register.set(writer.bits);
|
||||
result
|
||||
}
|
||||
}
|
||||
impl<REG: Readable + Writable> Reg<REG> {
|
||||
#[doc = " Modifies the contents of the register by reading and then writing it."]
|
||||
#[doc = ""]
|
||||
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.modify(|r, w| unsafe { w.bits("]
|
||||
#[doc = " r.bits() | 3"]
|
||||
#[doc = " ) });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.modify(|_, w| w"]
|
||||
#[doc = " .field1().bits(newfield1bits)"]
|
||||
#[doc = " .field2().set_bit()"]
|
||||
#[doc = " .field3().variant(VARIANT)"]
|
||||
#[doc = " );"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or an alternative way of saying the same:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.modify(|_, w| {"]
|
||||
#[doc = " w.field1().bits(newfield1bits);"]
|
||||
#[doc = " w.field2().set_bit();"]
|
||||
#[doc = " w.field3().variant(VARIANT)"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " Other fields will have the value they had before the call to `modify`."]
|
||||
#[inline(always)]
|
||||
pub fn modify<F>(&self, f: F) -> REG::Ux
|
||||
where
|
||||
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> &'w mut W<REG>,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let value = f(
|
||||
&R {
|
||||
bits,
|
||||
_reg: marker::PhantomData,
|
||||
},
|
||||
&mut W {
|
||||
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
|
||||
_reg: marker::PhantomData,
|
||||
},
|
||||
)
|
||||
.bits;
|
||||
self.register.set(value);
|
||||
value
|
||||
}
|
||||
#[doc = " Modifies the contents of the register by reading and then writing it"]
|
||||
#[doc = " and produces a value."]
|
||||
#[doc = ""]
|
||||
#[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " let bits = periph.reg.modify(|r, w| {"]
|
||||
#[doc = " let new_bits = r.bits() | 3;"]
|
||||
#[doc = " unsafe {"]
|
||||
#[doc = " w.bits(new_bits);"]
|
||||
#[doc = " }"]
|
||||
#[doc = ""]
|
||||
#[doc = " new_bits"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.modify(|_, w| {"]
|
||||
#[doc = " w.field1().bits(newfield1bits)"]
|
||||
#[doc = " .field2().set_bit()"]
|
||||
#[doc = " .field3().variant(VARIANT);"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " or an alternative way of saying the same:"]
|
||||
#[doc = " ```ignore"]
|
||||
#[doc = " periph.reg.modify(|_, w| {"]
|
||||
#[doc = " w.field1().bits(newfield1bits);"]
|
||||
#[doc = " w.field2().set_bit();"]
|
||||
#[doc = " w.field3().variant(VARIANT);"]
|
||||
#[doc = " });"]
|
||||
#[doc = " ```"]
|
||||
#[doc = " Other fields will have the value they had before the call to `modify`."]
|
||||
#[inline(always)]
|
||||
pub fn from_modify<F, T>(&self, f: F) -> T
|
||||
where
|
||||
for<'w> F: FnOnce(&R<REG>, &'w mut W<REG>) -> T,
|
||||
{
|
||||
let bits = self.register.get();
|
||||
let mut writer = W {
|
||||
bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP | REG::ZERO_TO_MODIFY_FIELDS_BITMAP,
|
||||
_reg: marker::PhantomData,
|
||||
};
|
||||
let result = f(
|
||||
&R {
|
||||
bits,
|
||||
_reg: marker::PhantomData,
|
||||
},
|
||||
&mut writer,
|
||||
);
|
||||
self.register.set(writer.bits);
|
||||
result
|
||||
}
|
||||
}
|
||||
impl<REG: Readable> core::fmt::Debug for crate::generic::Reg<REG>
|
||||
where
|
||||
R<REG>: core::fmt::Debug,
|
||||
{
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||
core::fmt::Debug::fmt(&self.read(), f)
|
||||
}
|
||||
}
|
||||
@ -1,95 +0,0 @@
|
||||
use super::{BitM, FieldSpec, RegisterSpec, Unsafe, Writable, marker};
|
||||
pub struct R<REG: RegisterSpec> {
|
||||
pub(crate) bits: REG::Ux,
|
||||
pub(super) _reg: marker::PhantomData<REG>,
|
||||
}
|
||||
pub struct W<REG: RegisterSpec> {
|
||||
#[doc = "Writable bits"]
|
||||
pub(crate) bits: REG::Ux,
|
||||
pub(super) _reg: marker::PhantomData<REG>,
|
||||
}
|
||||
pub struct FieldReader<FI = u8>
|
||||
where
|
||||
FI: FieldSpec,
|
||||
{
|
||||
pub(crate) bits: FI::Ux,
|
||||
_reg: marker::PhantomData<FI>,
|
||||
}
|
||||
impl<FI: FieldSpec> FieldReader<FI> {
|
||||
#[doc = " Creates a new instance of the reader."]
|
||||
#[allow(unused)]
|
||||
#[inline(always)]
|
||||
pub(crate) const fn new(bits: FI::Ux) -> Self {
|
||||
Self {
|
||||
bits,
|
||||
_reg: marker::PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
pub struct BitReader<FI = bool> {
|
||||
pub(crate) bits: bool,
|
||||
_reg: marker::PhantomData<FI>,
|
||||
}
|
||||
impl<FI> BitReader<FI> {
|
||||
#[doc = " Creates a new instance of the reader."]
|
||||
#[allow(unused)]
|
||||
#[inline(always)]
|
||||
pub(crate) const fn new(bits: bool) -> Self {
|
||||
Self {
|
||||
bits,
|
||||
_reg: marker::PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[must_use = "after creating `FieldWriter` you need to call field value setting method"]
|
||||
pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
{
|
||||
pub(crate) w: &'a mut W<REG>,
|
||||
pub(crate) o: u8,
|
||||
_field: marker::PhantomData<(FI, Safety)>,
|
||||
}
|
||||
impl<'a, REG, const WI: u8, FI, Safety> FieldWriter<'a, REG, WI, FI, Safety>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
FI: FieldSpec,
|
||||
{
|
||||
#[doc = " Creates a new instance of the writer"]
|
||||
#[allow(unused)]
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
|
||||
Self {
|
||||
w,
|
||||
o,
|
||||
_field: marker::PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
#[must_use = "after creating `BitWriter` you need to call bit setting method"]
|
||||
pub struct BitWriter<'a, REG, FI = bool, M = BitM>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
pub(crate) w: &'a mut W<REG>,
|
||||
pub(crate) o: u8,
|
||||
_field: marker::PhantomData<(FI, M)>,
|
||||
}
|
||||
impl<'a, REG, FI, M> BitWriter<'a, REG, FI, M>
|
||||
where
|
||||
REG: Writable + RegisterSpec,
|
||||
bool: From<FI>,
|
||||
{
|
||||
#[doc = " Creates a new instance of the writer"]
|
||||
#[allow(unused)]
|
||||
#[inline(always)]
|
||||
pub(crate) fn new(w: &'a mut W<REG>, o: u8) -> Self {
|
||||
Self {
|
||||
w,
|
||||
o,
|
||||
_field: marker::PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,237 +1,2 @@
|
||||
#![doc = "Peripheral access API for ARM_EXAMPLE microcontrollers (generated using svd2rust v0.35.0 (e10f920 2025-02-12))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
|
||||
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.35.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
|
||||
#![allow(non_camel_case_types)]
|
||||
#![allow(non_snake_case)]
|
||||
//! Rust peripheral acess crate to the AMD Zynq 7000 SoCs
|
||||
#![no_std]
|
||||
use core::marker::PhantomData;
|
||||
use core::ops::Deref;
|
||||
#[doc = r"Number available in the NVIC for configuring priority"]
|
||||
pub const NVIC_PRIO_BITS: u8 = 3;
|
||||
#[cfg(feature = "rt")]
|
||||
pub use self::Interrupt as interrupt;
|
||||
#[cfg(feature = "rt")]
|
||||
pub use cortex_m_rt::interrupt;
|
||||
#[allow(unused_imports)]
|
||||
use generic::*;
|
||||
#[doc = r"Common register and bit access and modify traits"]
|
||||
pub mod generic;
|
||||
#[cfg(feature = "rt")]
|
||||
extern "C" {
|
||||
fn TIMER0();
|
||||
fn TIMER1();
|
||||
fn TIMER2();
|
||||
}
|
||||
#[doc(hidden)]
|
||||
#[repr(C)]
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[cfg(feature = "rt")]
|
||||
#[doc(hidden)]
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 7] = [
|
||||
Vector { _handler: TIMER0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIMER1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIMER2 },
|
||||
];
|
||||
#[doc = r"Enumeration of all the interrupts."]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[repr(u16)]
|
||||
pub enum Interrupt {
|
||||
#[doc = "0 - Timer 0 interrupt"]
|
||||
TIMER0 = 0,
|
||||
#[doc = "4 - Timer 1 interrupt"]
|
||||
TIMER1 = 4,
|
||||
#[doc = "6 - Timer 2 interrupt"]
|
||||
TIMER2 = 6,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
#[doc = "32 Timer / Counter, counting up or down from different sources"]
|
||||
pub struct Timer0 {
|
||||
_marker: PhantomData<*const ()>,
|
||||
}
|
||||
unsafe impl Send for Timer0 {}
|
||||
impl Timer0 {
|
||||
#[doc = r"Pointer to the register block"]
|
||||
pub const PTR: *const timer0::RegisterBlock = 0x4001_0000 as *const _;
|
||||
#[doc = r"Return the pointer to the register block"]
|
||||
#[inline(always)]
|
||||
pub const fn ptr() -> *const timer0::RegisterBlock {
|
||||
Self::PTR
|
||||
}
|
||||
#[doc = r" Steal an instance of this peripheral"]
|
||||
#[doc = r""]
|
||||
#[doc = r" # Safety"]
|
||||
#[doc = r""]
|
||||
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
|
||||
#[doc = r" that may race with any existing instances, for example by only"]
|
||||
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
|
||||
#[doc = r" original peripheral and using critical sections to coordinate"]
|
||||
#[doc = r" access between multiple new instances."]
|
||||
#[doc = r""]
|
||||
#[doc = r" Additionally, other software such as HALs may rely on only one"]
|
||||
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
|
||||
#[doc = r" no stolen instances are passed to such software."]
|
||||
pub unsafe fn steal() -> Self {
|
||||
Self {
|
||||
_marker: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
impl Deref for Timer0 {
|
||||
type Target = timer0::RegisterBlock;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*Self::PTR }
|
||||
}
|
||||
}
|
||||
impl core::fmt::Debug for Timer0 {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("Timer0").finish()
|
||||
}
|
||||
}
|
||||
#[doc = "32 Timer / Counter, counting up or down from different sources"]
|
||||
pub mod timer0;
|
||||
#[doc = "32 Timer / Counter, counting up or down from different sources"]
|
||||
pub struct Timer1 {
|
||||
_marker: PhantomData<*const ()>,
|
||||
}
|
||||
unsafe impl Send for Timer1 {}
|
||||
impl Timer1 {
|
||||
#[doc = r"Pointer to the register block"]
|
||||
pub const PTR: *const timer0::RegisterBlock = 0x4001_0100 as *const _;
|
||||
#[doc = r"Return the pointer to the register block"]
|
||||
#[inline(always)]
|
||||
pub const fn ptr() -> *const timer0::RegisterBlock {
|
||||
Self::PTR
|
||||
}
|
||||
#[doc = r" Steal an instance of this peripheral"]
|
||||
#[doc = r""]
|
||||
#[doc = r" # Safety"]
|
||||
#[doc = r""]
|
||||
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
|
||||
#[doc = r" that may race with any existing instances, for example by only"]
|
||||
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
|
||||
#[doc = r" original peripheral and using critical sections to coordinate"]
|
||||
#[doc = r" access between multiple new instances."]
|
||||
#[doc = r""]
|
||||
#[doc = r" Additionally, other software such as HALs may rely on only one"]
|
||||
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
|
||||
#[doc = r" no stolen instances are passed to such software."]
|
||||
pub unsafe fn steal() -> Self {
|
||||
Self {
|
||||
_marker: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
impl Deref for Timer1 {
|
||||
type Target = timer0::RegisterBlock;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*Self::PTR }
|
||||
}
|
||||
}
|
||||
impl core::fmt::Debug for Timer1 {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("Timer1").finish()
|
||||
}
|
||||
}
|
||||
#[doc = "32 Timer / Counter, counting up or down from different sources"]
|
||||
pub use self::timer0 as timer1;
|
||||
#[doc = "32 Timer / Counter, counting up or down from different sources"]
|
||||
pub struct Timer2 {
|
||||
_marker: PhantomData<*const ()>,
|
||||
}
|
||||
unsafe impl Send for Timer2 {}
|
||||
impl Timer2 {
|
||||
#[doc = r"Pointer to the register block"]
|
||||
pub const PTR: *const timer0::RegisterBlock = 0x4001_0200 as *const _;
|
||||
#[doc = r"Return the pointer to the register block"]
|
||||
#[inline(always)]
|
||||
pub const fn ptr() -> *const timer0::RegisterBlock {
|
||||
Self::PTR
|
||||
}
|
||||
#[doc = r" Steal an instance of this peripheral"]
|
||||
#[doc = r""]
|
||||
#[doc = r" # Safety"]
|
||||
#[doc = r""]
|
||||
#[doc = r" Ensure that the new instance of the peripheral cannot be used in a way"]
|
||||
#[doc = r" that may race with any existing instances, for example by only"]
|
||||
#[doc = r" accessing read-only or write-only registers, or by consuming the"]
|
||||
#[doc = r" original peripheral and using critical sections to coordinate"]
|
||||
#[doc = r" access between multiple new instances."]
|
||||
#[doc = r""]
|
||||
#[doc = r" Additionally, other software such as HALs may rely on only one"]
|
||||
#[doc = r" peripheral instance existing to ensure memory safety; ensure"]
|
||||
#[doc = r" no stolen instances are passed to such software."]
|
||||
pub unsafe fn steal() -> Self {
|
||||
Self {
|
||||
_marker: PhantomData,
|
||||
}
|
||||
}
|
||||
}
|
||||
impl Deref for Timer2 {
|
||||
type Target = timer0::RegisterBlock;
|
||||
#[inline(always)]
|
||||
fn deref(&self) -> &Self::Target {
|
||||
unsafe { &*Self::PTR }
|
||||
}
|
||||
}
|
||||
impl core::fmt::Debug for Timer2 {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
f.debug_struct("Timer2").finish()
|
||||
}
|
||||
}
|
||||
#[doc = "32 Timer / Counter, counting up or down from different sources"]
|
||||
pub use self::timer0 as timer2;
|
||||
#[no_mangle]
|
||||
static mut DEVICE_PERIPHERALS: bool = false;
|
||||
#[doc = r" All the peripherals."]
|
||||
#[allow(non_snake_case)]
|
||||
pub struct Peripherals {
|
||||
#[doc = "TIMER0"]
|
||||
pub timer0: Timer0,
|
||||
#[doc = "TIMER1"]
|
||||
pub timer1: Timer1,
|
||||
#[doc = "TIMER2"]
|
||||
pub timer2: Timer2,
|
||||
}
|
||||
impl Peripherals {
|
||||
#[doc = r" Returns all the peripherals *once*."]
|
||||
#[cfg(feature = "critical-section")]
|
||||
#[inline]
|
||||
pub fn take() -> Option<Self> {
|
||||
critical_section::with(|_| {
|
||||
if unsafe { DEVICE_PERIPHERALS } {
|
||||
return None;
|
||||
}
|
||||
Some(unsafe { Peripherals::steal() })
|
||||
})
|
||||
}
|
||||
#[doc = r" Unchecked version of `Peripherals::take`."]
|
||||
#[doc = r""]
|
||||
#[doc = r" # Safety"]
|
||||
#[doc = r""]
|
||||
#[doc = r" Each of the returned peripherals must be used at most once."]
|
||||
#[inline]
|
||||
pub unsafe fn steal() -> Self {
|
||||
DEVICE_PERIPHERALS = true;
|
||||
Peripherals {
|
||||
timer0: Timer0::steal(),
|
||||
timer1: Timer1::steal(),
|
||||
timer2: Timer2::steal(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,110 +0,0 @@
|
||||
#[repr(C)]
|
||||
#[doc = "Register block"]
|
||||
pub struct RegisterBlock {
|
||||
cr: Cr,
|
||||
sr: Sr,
|
||||
_reserved2: [u8; 0x0a],
|
||||
int: Int,
|
||||
_reserved3: [u8; 0x0e],
|
||||
count: Count,
|
||||
match_: Match,
|
||||
_reserved_5_prescale: [u8; 0x04],
|
||||
_reserved6: [u8; 0x24],
|
||||
reload: [Reload; 4],
|
||||
}
|
||||
impl RegisterBlock {
|
||||
#[doc = "0x00 - Control Register"]
|
||||
#[inline(always)]
|
||||
pub const fn cr(&self) -> &Cr {
|
||||
&self.cr
|
||||
}
|
||||
#[doc = "0x04 - Status Register"]
|
||||
#[inline(always)]
|
||||
pub const fn sr(&self) -> &Sr {
|
||||
&self.sr
|
||||
}
|
||||
#[doc = "0x10 - Interrupt Register"]
|
||||
#[inline(always)]
|
||||
pub const fn int(&self) -> &Int {
|
||||
&self.int
|
||||
}
|
||||
#[doc = "0x20 - The Counter Register reflects the actual Value of the Timer/Counter"]
|
||||
#[inline(always)]
|
||||
pub const fn count(&self) -> &Count {
|
||||
&self.count
|
||||
}
|
||||
#[doc = "0x24 - The Match Register stores the compare Value for the MATCH condition"]
|
||||
#[inline(always)]
|
||||
pub const fn match_(&self) -> &Match {
|
||||
&self.match_
|
||||
}
|
||||
#[doc = "0x28 - The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"]
|
||||
#[inline(always)]
|
||||
pub const fn prescale_wr(&self) -> &PrescaleWr {
|
||||
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
|
||||
}
|
||||
#[doc = "0x28 - The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"]
|
||||
#[inline(always)]
|
||||
pub const fn prescale_rd(&self) -> &PrescaleRd {
|
||||
unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(40).cast() }
|
||||
}
|
||||
#[doc = "0x50..0x60 - The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met."]
|
||||
#[inline(always)]
|
||||
pub const fn reload(&self, n: usize) -> &Reload {
|
||||
&self.reload[n]
|
||||
}
|
||||
#[doc = "Iterator for array of:"]
|
||||
#[doc = "0x50..0x60 - The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met."]
|
||||
#[inline(always)]
|
||||
pub fn reload_iter(&self) -> impl Iterator<Item = &Reload> {
|
||||
self.reload.iter()
|
||||
}
|
||||
}
|
||||
#[doc = "CR (rw) register accessor: Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
|
||||
module"]
|
||||
#[doc(alias = "CR")]
|
||||
pub type Cr = crate::Reg<cr::CrSpec>;
|
||||
#[doc = "Control Register"]
|
||||
pub mod cr;
|
||||
#[doc = "SR (rw) register accessor: Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sr`]
|
||||
module"]
|
||||
#[doc(alias = "SR")]
|
||||
pub type Sr = crate::Reg<sr::SrSpec>;
|
||||
#[doc = "Status Register"]
|
||||
pub mod sr;
|
||||
#[doc = "INT (rw) register accessor: Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int`]
|
||||
module"]
|
||||
#[doc(alias = "INT")]
|
||||
pub type Int = crate::Reg<int::IntSpec>;
|
||||
#[doc = "Interrupt Register"]
|
||||
pub mod int;
|
||||
#[doc = "COUNT (rw) register accessor: The Counter Register reflects the actual Value of the Timer/Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`count::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@count`]
|
||||
module"]
|
||||
#[doc(alias = "COUNT")]
|
||||
pub type Count = crate::Reg<count::CountSpec>;
|
||||
#[doc = "The Counter Register reflects the actual Value of the Timer/Counter"]
|
||||
pub mod count;
|
||||
#[doc = "MATCH (rw) register accessor: The Match Register stores the compare Value for the MATCH condition\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@match_`]
|
||||
module"]
|
||||
#[doc(alias = "MATCH")]
|
||||
pub type Match = crate::Reg<match_::MatchSpec>;
|
||||
#[doc = "The Match Register stores the compare Value for the MATCH condition"]
|
||||
pub mod match_;
|
||||
#[doc = "PRESCALE_RD (r) register accessor: The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`read`](crate::Reg::read) this register and get [`prescale_rd::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prescale_rd`]
|
||||
module"]
|
||||
#[doc(alias = "PRESCALE_RD")]
|
||||
pub type PrescaleRd = crate::Reg<prescale_rd::PrescaleRdSpec>;
|
||||
#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"]
|
||||
pub mod prescale_rd;
|
||||
#[doc = "PRESCALE_WR (w) register accessor: The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prescale_wr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@prescale_wr`]
|
||||
module"]
|
||||
#[doc(alias = "PRESCALE_WR")]
|
||||
pub type PrescaleWr = crate::Reg<prescale_wr::PrescaleWrSpec>;
|
||||
#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value"]
|
||||
pub mod prescale_wr;
|
||||
#[doc = "RELOAD (rw) register accessor: The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@reload`]
|
||||
module"]
|
||||
#[doc(alias = "RELOAD")]
|
||||
pub type Reload = crate::Reg<reload::ReloadSpec>;
|
||||
#[doc = "The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met."]
|
||||
pub mod reload;
|
||||
@ -1,28 +0,0 @@
|
||||
#[doc = "Register `COUNT` reader"]
|
||||
pub type R = crate::R<CountSpec>;
|
||||
#[doc = "Register `COUNT` writer"]
|
||||
pub type W = crate::W<CountSpec>;
|
||||
#[cfg(feature = "debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Counter Register reflects the actual Value of the Timer/Counter\n\nYou can [`read`](crate::Reg::read) this register and get [`count::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`count::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct CountSpec;
|
||||
impl crate::RegisterSpec for CountSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`count::R`](R) reader structure"]
|
||||
impl crate::Readable for CountSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`count::W`](W) writer structure"]
|
||||
impl crate::Writable for CountSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets COUNT to value 0"]
|
||||
impl crate::Resettable for CountSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,173 +0,0 @@
|
||||
#[doc = "Register `INT` reader"]
|
||||
pub type R = crate::R<IntSpec>;
|
||||
#[doc = "Register `INT` writer"]
|
||||
pub type W = crate::W<IntSpec>;
|
||||
#[doc = "Interrupt Enable\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum En {
|
||||
#[doc = "0: Timer does not generate Interrupts"]
|
||||
Disabled = 0,
|
||||
#[doc = "1: Timer triggers the TIMERn Interrupt"]
|
||||
Enable = 1,
|
||||
}
|
||||
impl From<En> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: En) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `EN` reader - Interrupt Enable"]
|
||||
pub type EnR = crate::BitReader<En>;
|
||||
impl EnR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> En {
|
||||
match self.bits {
|
||||
false => En::Disabled,
|
||||
true => En::Enable,
|
||||
}
|
||||
}
|
||||
#[doc = "Timer does not generate Interrupts"]
|
||||
#[inline(always)]
|
||||
pub fn is_disabled(&self) -> bool {
|
||||
*self == En::Disabled
|
||||
}
|
||||
#[doc = "Timer triggers the TIMERn Interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn is_enable(&self) -> bool {
|
||||
*self == En::Enable
|
||||
}
|
||||
}
|
||||
#[doc = "Field `EN` writer - Interrupt Enable"]
|
||||
pub type EnW<'a, REG> = crate::BitWriter<'a, REG, En>;
|
||||
impl<'a, REG> EnW<'a, REG>
|
||||
where
|
||||
REG: crate::Writable + crate::RegisterSpec,
|
||||
{
|
||||
#[doc = "Timer does not generate Interrupts"]
|
||||
#[inline(always)]
|
||||
pub fn disabled(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(En::Disabled)
|
||||
}
|
||||
#[doc = "Timer triggers the TIMERn Interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn enable(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(En::Enable)
|
||||
}
|
||||
}
|
||||
#[doc = "Interrupt Mode, selects on which condition the Timer should generate an Interrupt\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
#[repr(u8)]
|
||||
pub enum Mode {
|
||||
#[doc = "0: Timer generates an Interrupt when the MATCH condition is hit"]
|
||||
Match = 0,
|
||||
#[doc = "1: Timer generates an Interrupt when it underflows"]
|
||||
Underflow = 1,
|
||||
#[doc = "2: Timer generates an Interrupt when it overflows"]
|
||||
Overflow = 2,
|
||||
}
|
||||
impl From<Mode> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: Mode) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
impl crate::FieldSpec for Mode {
|
||||
type Ux = u8;
|
||||
}
|
||||
impl crate::IsEnum for Mode {}
|
||||
#[doc = "Field `MODE` reader - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"]
|
||||
pub type ModeR = crate::FieldReader<Mode>;
|
||||
impl ModeR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Option<Mode> {
|
||||
match self.bits {
|
||||
0 => Some(Mode::Match),
|
||||
1 => Some(Mode::Underflow),
|
||||
2 => Some(Mode::Overflow),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
#[doc = "Timer generates an Interrupt when the MATCH condition is hit"]
|
||||
#[inline(always)]
|
||||
pub fn is_match(&self) -> bool {
|
||||
*self == Mode::Match
|
||||
}
|
||||
#[doc = "Timer generates an Interrupt when it underflows"]
|
||||
#[inline(always)]
|
||||
pub fn is_underflow(&self) -> bool {
|
||||
*self == Mode::Underflow
|
||||
}
|
||||
#[doc = "Timer generates an Interrupt when it overflows"]
|
||||
#[inline(always)]
|
||||
pub fn is_overflow(&self) -> bool {
|
||||
*self == Mode::Overflow
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MODE` writer - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"]
|
||||
pub type ModeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mode>;
|
||||
impl<'a, REG> ModeW<'a, REG>
|
||||
where
|
||||
REG: crate::Writable + crate::RegisterSpec,
|
||||
REG::Ux: From<u8>,
|
||||
{
|
||||
#[doc = "Timer generates an Interrupt when the MATCH condition is hit"]
|
||||
#[inline(always)]
|
||||
pub fn match_(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Mode::Match)
|
||||
}
|
||||
#[doc = "Timer generates an Interrupt when it underflows"]
|
||||
#[inline(always)]
|
||||
pub fn underflow(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Mode::Underflow)
|
||||
}
|
||||
#[doc = "Timer generates an Interrupt when it overflows"]
|
||||
#[inline(always)]
|
||||
pub fn overflow(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Mode::Overflow)
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Interrupt Enable"]
|
||||
#[inline(always)]
|
||||
pub fn en(&self) -> EnR {
|
||||
EnR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 4:6 - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn mode(&self) -> ModeR {
|
||||
ModeR::new(((self.bits >> 4) & 7) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 0 - Interrupt Enable"]
|
||||
#[inline(always)]
|
||||
pub fn en(&mut self) -> EnW<IntSpec> {
|
||||
EnW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 4:6 - Interrupt Mode, selects on which condition the Timer should generate an Interrupt"]
|
||||
#[inline(always)]
|
||||
pub fn mode(&mut self) -> ModeW<IntSpec> {
|
||||
ModeW::new(self, 4)
|
||||
}
|
||||
}
|
||||
#[doc = "Interrupt Register\n\nYou can [`read`](crate::Reg::read) this register and get [`int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct IntSpec;
|
||||
impl crate::RegisterSpec for IntSpec {
|
||||
type Ux = u16;
|
||||
}
|
||||
#[doc = "`read()` method returns [`int::R`](R) reader structure"]
|
||||
impl crate::Readable for IntSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`int::W`](W) writer structure"]
|
||||
impl crate::Writable for IntSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets INT to value 0"]
|
||||
impl crate::Resettable for IntSpec {
|
||||
const RESET_VALUE: u16 = 0;
|
||||
}
|
||||
@ -1,28 +0,0 @@
|
||||
#[doc = "Register `MATCH` reader"]
|
||||
pub type R = crate::R<MatchSpec>;
|
||||
#[doc = "Register `MATCH` writer"]
|
||||
pub type W = crate::W<MatchSpec>;
|
||||
#[cfg(feature = "debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Match Register stores the compare Value for the MATCH condition\n\nYou can [`read`](crate::Reg::read) this register and get [`match_::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`match_::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct MatchSpec;
|
||||
impl crate::RegisterSpec for MatchSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`match_::R`](R) reader structure"]
|
||||
impl crate::Readable for MatchSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`match_::W`](W) writer structure"]
|
||||
impl crate::Writable for MatchSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets MATCH to value 0"]
|
||||
impl crate::Resettable for MatchSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@ -1,19 +0,0 @@
|
||||
#[doc = "Register `PRESCALE_RD` reader"]
|
||||
pub type R = crate::R<PrescaleRdSpec>;
|
||||
#[cfg(feature = "debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`read`](crate::Reg::read) this register and get [`prescale_rd::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PrescaleRdSpec;
|
||||
impl crate::RegisterSpec for PrescaleRdSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`prescale_rd::R`](R) reader structure"]
|
||||
impl crate::Readable for PrescaleRdSpec {}
|
||||
#[doc = "`reset()` method sets PRESCALE_RD to value 0"]
|
||||
impl crate::Resettable for PrescaleRdSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@ -1,24 +0,0 @@
|
||||
#[doc = "Register `PRESCALE_WR` writer"]
|
||||
pub type W = crate::W<PrescaleWrSpec>;
|
||||
#[cfg(feature = "debug")]
|
||||
impl core::fmt::Debug for crate::generic::Reg<PrescaleWrSpec> {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||
write!(f, "(not readable)")
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Prescale Register stores the Value for the prescaler. The cont event gets divided by this value\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`prescale_wr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PrescaleWrSpec;
|
||||
impl crate::RegisterSpec for PrescaleWrSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`write(|w| ..)` method takes [`prescale_wr::W`](W) writer structure"]
|
||||
impl crate::Writable for PrescaleWrSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets PRESCALE_WR to value 0"]
|
||||
impl crate::Resettable for PrescaleWrSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@ -1,29 +0,0 @@
|
||||
#[doc = "Register `RELOAD[%s]` reader"]
|
||||
pub type R = crate::R<ReloadSpec>;
|
||||
#[doc = "Register `RELOAD[%s]` writer"]
|
||||
pub type W = crate::W<ReloadSpec>;
|
||||
#[cfg(feature = "debug")]
|
||||
impl core::fmt::Debug for R {
|
||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||
write!(f, "{}", self.bits())
|
||||
}
|
||||
}
|
||||
impl W {}
|
||||
#[doc = "The Reload Register stores the Value the COUNT Register gets reloaded on a when a condition was met.\n\nYou can [`read`](crate::Reg::read) this register and get [`reload::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`reload::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct ReloadSpec;
|
||||
impl crate::RegisterSpec for ReloadSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`reload::R`](R) reader structure"]
|
||||
impl crate::Readable for ReloadSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`reload::W`](W) writer structure"]
|
||||
impl crate::Writable for ReloadSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets RELOAD[%s]
|
||||
to value 0"]
|
||||
impl crate::Resettable for ReloadSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
@ -1,365 +0,0 @@
|
||||
#[doc = "Register `SR` reader"]
|
||||
pub type R = crate::R<SrSpec>;
|
||||
#[doc = "Register `SR` writer"]
|
||||
pub type W = crate::W<SrSpec>;
|
||||
#[doc = "Shows if Timer is running or not\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Run {
|
||||
#[doc = "0: Timer is not running"]
|
||||
Stopped = 0,
|
||||
#[doc = "1: Timer is running"]
|
||||
Running = 1,
|
||||
}
|
||||
impl From<Run> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: Run) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RUN` reader - Shows if Timer is running or not"]
|
||||
pub type RunR = crate::BitReader<Run>;
|
||||
impl RunR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Run {
|
||||
match self.bits {
|
||||
false => Run::Stopped,
|
||||
true => Run::Running,
|
||||
}
|
||||
}
|
||||
#[doc = "Timer is not running"]
|
||||
#[inline(always)]
|
||||
pub fn is_stopped(&self) -> bool {
|
||||
*self == Run::Stopped
|
||||
}
|
||||
#[doc = "Timer is running"]
|
||||
#[inline(always)]
|
||||
pub fn is_running(&self) -> bool {
|
||||
*self == Run::Running
|
||||
}
|
||||
}
|
||||
#[doc = "Shows if the MATCH was hit\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Match {
|
||||
#[doc = "0: The MATCH condition was not hit"]
|
||||
NoMatch = 0,
|
||||
#[doc = "1: The MATCH condition was hit"]
|
||||
MatchHit = 1,
|
||||
}
|
||||
impl From<Match> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: Match) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MATCH` reader - Shows if the MATCH was hit"]
|
||||
pub type MatchR = crate::BitReader<Match>;
|
||||
impl MatchR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Match {
|
||||
match self.bits {
|
||||
false => Match::NoMatch,
|
||||
true => Match::MatchHit,
|
||||
}
|
||||
}
|
||||
#[doc = "The MATCH condition was not hit"]
|
||||
#[inline(always)]
|
||||
pub fn is_no_match(&self) -> bool {
|
||||
*self == Match::NoMatch
|
||||
}
|
||||
#[doc = "The MATCH condition was hit"]
|
||||
#[inline(always)]
|
||||
pub fn is_match_hit(&self) -> bool {
|
||||
*self == Match::MatchHit
|
||||
}
|
||||
}
|
||||
#[doc = "Field `MATCH` writer - Shows if the MATCH was hit"]
|
||||
pub type MatchW<'a, REG> = crate::BitWriter<'a, REG, Match>;
|
||||
impl<'a, REG> MatchW<'a, REG>
|
||||
where
|
||||
REG: crate::Writable + crate::RegisterSpec,
|
||||
{
|
||||
#[doc = "The MATCH condition was not hit"]
|
||||
#[inline(always)]
|
||||
pub fn no_match(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Match::NoMatch)
|
||||
}
|
||||
#[doc = "The MATCH condition was hit"]
|
||||
#[inline(always)]
|
||||
pub fn match_hit(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Match::MatchHit)
|
||||
}
|
||||
}
|
||||
#[doc = "Shows if an underflow occured. This flag is sticky\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Un {
|
||||
#[doc = "0: No underflow occured since last clear"]
|
||||
NoUnderflow = 0,
|
||||
#[doc = "1: A minimum of one underflow occured since last clear"]
|
||||
Underflow = 1,
|
||||
}
|
||||
impl From<Un> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: Un) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `UN` reader - Shows if an underflow occured. This flag is sticky"]
|
||||
pub type UnR = crate::BitReader<Un>;
|
||||
impl UnR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Un {
|
||||
match self.bits {
|
||||
false => Un::NoUnderflow,
|
||||
true => Un::Underflow,
|
||||
}
|
||||
}
|
||||
#[doc = "No underflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn is_no_underflow(&self) -> bool {
|
||||
*self == Un::NoUnderflow
|
||||
}
|
||||
#[doc = "A minimum of one underflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn is_underflow(&self) -> bool {
|
||||
*self == Un::Underflow
|
||||
}
|
||||
}
|
||||
#[doc = "Field `UN` writer - Shows if an underflow occured. This flag is sticky"]
|
||||
pub type UnW<'a, REG> = crate::BitWriter<'a, REG, Un>;
|
||||
impl<'a, REG> UnW<'a, REG>
|
||||
where
|
||||
REG: crate::Writable + crate::RegisterSpec,
|
||||
{
|
||||
#[doc = "No underflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn no_underflow(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Un::NoUnderflow)
|
||||
}
|
||||
#[doc = "A minimum of one underflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn underflow(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Un::Underflow)
|
||||
}
|
||||
}
|
||||
#[doc = "Shows if an overflow occured. This flag is sticky\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Ov {
|
||||
#[doc = "0: No overflow occured since last clear"]
|
||||
NoOverflow = 0,
|
||||
#[doc = "1: A minimum of one overflow occured since last clear"]
|
||||
OverflowOccured = 1,
|
||||
}
|
||||
impl From<Ov> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: Ov) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `OV` reader - Shows if an overflow occured. This flag is sticky"]
|
||||
pub type OvR = crate::BitReader<Ov>;
|
||||
impl OvR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Ov {
|
||||
match self.bits {
|
||||
false => Ov::NoOverflow,
|
||||
true => Ov::OverflowOccured,
|
||||
}
|
||||
}
|
||||
#[doc = "No overflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn is_no_overflow(&self) -> bool {
|
||||
*self == Ov::NoOverflow
|
||||
}
|
||||
#[doc = "A minimum of one overflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn is_overflow_occured(&self) -> bool {
|
||||
*self == Ov::OverflowOccured
|
||||
}
|
||||
}
|
||||
#[doc = "Field `OV` writer - Shows if an overflow occured. This flag is sticky"]
|
||||
pub type OvW<'a, REG> = crate::BitWriter<'a, REG, Ov>;
|
||||
impl<'a, REG> OvW<'a, REG>
|
||||
where
|
||||
REG: crate::Writable + crate::RegisterSpec,
|
||||
{
|
||||
#[doc = "No overflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn no_overflow(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Ov::NoOverflow)
|
||||
}
|
||||
#[doc = "A minimum of one overflow occured since last clear"]
|
||||
#[inline(always)]
|
||||
pub fn overflow_occured(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Ov::OverflowOccured)
|
||||
}
|
||||
}
|
||||
#[doc = "Shows if Timer is in RESET state\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Rst {
|
||||
#[doc = "0: Timer is not in RESET state and can operate"]
|
||||
Ready = 0,
|
||||
#[doc = "1: Timer is in RESET state and can not operate"]
|
||||
InReset = 1,
|
||||
}
|
||||
impl From<Rst> for bool {
|
||||
#[inline(always)]
|
||||
fn from(variant: Rst) -> Self {
|
||||
variant as u8 != 0
|
||||
}
|
||||
}
|
||||
#[doc = "Field `RST` reader - Shows if Timer is in RESET state"]
|
||||
pub type RstR = crate::BitReader<Rst>;
|
||||
impl RstR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Rst {
|
||||
match self.bits {
|
||||
false => Rst::Ready,
|
||||
true => Rst::InReset,
|
||||
}
|
||||
}
|
||||
#[doc = "Timer is not in RESET state and can operate"]
|
||||
#[inline(always)]
|
||||
pub fn is_ready(&self) -> bool {
|
||||
*self == Rst::Ready
|
||||
}
|
||||
#[doc = "Timer is in RESET state and can not operate"]
|
||||
#[inline(always)]
|
||||
pub fn is_in_reset(&self) -> bool {
|
||||
*self == Rst::InReset
|
||||
}
|
||||
}
|
||||
#[doc = "Shows the currently active RELOAD Register\n\nValue on reset: 0"]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
#[repr(u8)]
|
||||
pub enum Reload {
|
||||
#[doc = "0: Reload Register number 0 is active"]
|
||||
Reload0 = 0,
|
||||
#[doc = "1: Reload Register number 1 is active"]
|
||||
Reload1 = 1,
|
||||
#[doc = "2: Reload Register number 2 is active"]
|
||||
Reload2 = 2,
|
||||
#[doc = "3: Reload Register number 3 is active"]
|
||||
Reload3 = 3,
|
||||
}
|
||||
impl From<Reload> for u8 {
|
||||
#[inline(always)]
|
||||
fn from(variant: Reload) -> Self {
|
||||
variant as _
|
||||
}
|
||||
}
|
||||
impl crate::FieldSpec for Reload {
|
||||
type Ux = u8;
|
||||
}
|
||||
impl crate::IsEnum for Reload {}
|
||||
#[doc = "Field `RELOAD` reader - Shows the currently active RELOAD Register"]
|
||||
pub type ReloadR = crate::FieldReader<Reload>;
|
||||
impl ReloadR {
|
||||
#[doc = "Get enumerated values variant"]
|
||||
#[inline(always)]
|
||||
pub const fn variant(&self) -> Reload {
|
||||
match self.bits {
|
||||
0 => Reload::Reload0,
|
||||
1 => Reload::Reload1,
|
||||
2 => Reload::Reload2,
|
||||
3 => Reload::Reload3,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
#[doc = "Reload Register number 0 is active"]
|
||||
#[inline(always)]
|
||||
pub fn is_reload0(&self) -> bool {
|
||||
*self == Reload::Reload0
|
||||
}
|
||||
#[doc = "Reload Register number 1 is active"]
|
||||
#[inline(always)]
|
||||
pub fn is_reload1(&self) -> bool {
|
||||
*self == Reload::Reload1
|
||||
}
|
||||
#[doc = "Reload Register number 2 is active"]
|
||||
#[inline(always)]
|
||||
pub fn is_reload2(&self) -> bool {
|
||||
*self == Reload::Reload2
|
||||
}
|
||||
#[doc = "Reload Register number 3 is active"]
|
||||
#[inline(always)]
|
||||
pub fn is_reload3(&self) -> bool {
|
||||
*self == Reload::Reload3
|
||||
}
|
||||
}
|
||||
impl R {
|
||||
#[doc = "Bit 0 - Shows if Timer is running or not"]
|
||||
#[inline(always)]
|
||||
pub fn run(&self) -> RunR {
|
||||
RunR::new((self.bits & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - Shows if the MATCH was hit"]
|
||||
#[inline(always)]
|
||||
pub fn match_(&self) -> MatchR {
|
||||
MatchR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - Shows if an underflow occured. This flag is sticky"]
|
||||
#[inline(always)]
|
||||
pub fn un(&self) -> UnR {
|
||||
UnR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 10 - Shows if an overflow occured. This flag is sticky"]
|
||||
#[inline(always)]
|
||||
pub fn ov(&self) -> OvR {
|
||||
OvR::new(((self.bits >> 10) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 12 - Shows if Timer is in RESET state"]
|
||||
#[inline(always)]
|
||||
pub fn rst(&self) -> RstR {
|
||||
RstR::new(((self.bits >> 12) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 14:15 - Shows the currently active RELOAD Register"]
|
||||
#[inline(always)]
|
||||
pub fn reload(&self) -> ReloadR {
|
||||
ReloadR::new(((self.bits >> 14) & 3) as u8)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bit 8 - Shows if the MATCH was hit"]
|
||||
#[inline(always)]
|
||||
pub fn match_(&mut self) -> MatchW<SrSpec> {
|
||||
MatchW::new(self, 8)
|
||||
}
|
||||
#[doc = "Bit 9 - Shows if an underflow occured. This flag is sticky"]
|
||||
#[inline(always)]
|
||||
pub fn un(&mut self) -> UnW<SrSpec> {
|
||||
UnW::new(self, 9)
|
||||
}
|
||||
#[doc = "Bit 10 - Shows if an overflow occured. This flag is sticky"]
|
||||
#[inline(always)]
|
||||
pub fn ov(&mut self) -> OvW<SrSpec> {
|
||||
OvW::new(self, 10)
|
||||
}
|
||||
}
|
||||
#[doc = "Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct SrSpec;
|
||||
impl crate::RegisterSpec for SrSpec {
|
||||
type Ux = u16;
|
||||
}
|
||||
#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
|
||||
impl crate::Readable for SrSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`sr::W`](W) writer structure"]
|
||||
impl crate::Writable for SrSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u16 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets SR to value 0"]
|
||||
impl crate::Resettable for SrSpec {
|
||||
const RESET_VALUE: u16 = 0;
|
||||
}
|
||||
Reference in New Issue
Block a user