rust/zynq7000-rs
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This commit is contained in:
Robin Müller
2025-02-26 15:42:57 +01:00
parent 884bc29146
commit e23f8cb81e
8 changed files with 189 additions and 42 deletions
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30
zynq7000-rt/src/bin/table-gen.rs
View File

@ -1,8 +1,8 @@
use std::fs::File;
use std::io::Write;
use std::process::Command;
pub use zynq7000_rt::mmu::segments::*;
use zynq7000_rt::mmu::ONE_MB;
pub use zynq7000_rt::mmu::segments::*;
fn main() {
let file_path = "src/mmu_table.rs";
@ -63,12 +63,22 @@ fn main() {
"// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
)
.unwrap();
writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_ddr
)
.unwrap();
offset += ONE_MB;
writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
for _ in 0..DDR_FULL_ACCESSIBLE {
writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_ddr
)
.unwrap();
offset += ONE_MB;
}
@ -163,7 +173,12 @@ fn main() {
writeln!(buf_writer, "// SRAM (0xE400_0000 - 0xE600_0000)").unwrap();
for _ in 0..SRAM {
writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_sram).unwrap();
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_sram
)
.unwrap();
offset += ONE_MB;
}
@ -214,7 +229,12 @@ fn main() {
writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
for _ in 0..QSPI_XIP {
writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_qspi).unwrap();
writeln!(
buf_writer,
"L1Section::new({}, {}).raw_value(),",
offset, attr_qspi
)
.unwrap();
offset += ONE_MB;
}

66
zynq7000-rt/src/mmu_table.rs
View File

@ -1,5 +1,5 @@
//! This file was auto-generated by table-gen.rs
use crate::mmu::{section_attrs, L1Table};
use crate::mmu::{L1Table, section_attrs};
use cortex_ar::mmu::L1Section;
/// MMU Level 1 Page table.
@ -3664,38 +3664,38 @@ pub const MMU_L1_PAGE_TABLE: L1Table = L1Table([
L1Section::new(3823108096, section_attrs::SHAREABLE_DEVICE).raw_value(),
L1Section::new(3824156672, section_attrs::SHAREABLE_DEVICE).raw_value(),
// SRAM (0xE400_0000 - 0xE600_0000)
L1Section::new(3825205248, section_attrs::SRAM).0,
L1Section::new(3826253824, section_attrs::SRAM).0,
L1Section::new(3827302400, section_attrs::SRAM).0,
L1Section::new(3828350976, section_attrs::SRAM).0,
L1Section::new(3829399552, section_attrs::SRAM).0,
L1Section::new(3830448128, section_attrs::SRAM).0,
L1Section::new(3831496704, section_attrs::SRAM).0,
L1Section::new(3832545280, section_attrs::SRAM).0,
L1Section::new(3833593856, section_attrs::SRAM).0,
L1Section::new(3834642432, section_attrs::SRAM).0,
L1Section::new(3835691008, section_attrs::SRAM).0,
L1Section::new(3836739584, section_attrs::SRAM).0,
L1Section::new(3837788160, section_attrs::SRAM).0,
L1Section::new(3838836736, section_attrs::SRAM).0,
L1Section::new(3839885312, section_attrs::SRAM).0,
L1Section::new(3840933888, section_attrs::SRAM).0,
L1Section::new(3841982464, section_attrs::SRAM).0,
L1Section::new(3843031040, section_attrs::SRAM).0,
L1Section::new(3844079616, section_attrs::SRAM).0,
L1Section::new(3845128192, section_attrs::SRAM).0,
L1Section::new(3846176768, section_attrs::SRAM).0,
L1Section::new(3847225344, section_attrs::SRAM).0,
L1Section::new(3848273920, section_attrs::SRAM).0,
L1Section::new(3849322496, section_attrs::SRAM).0,
L1Section::new(3850371072, section_attrs::SRAM).0,
L1Section::new(3851419648, section_attrs::SRAM).0,
L1Section::new(3852468224, section_attrs::SRAM).0,
L1Section::new(3853516800, section_attrs::SRAM).0,
L1Section::new(3854565376, section_attrs::SRAM).0,
L1Section::new(3855613952, section_attrs::SRAM).0,
L1Section::new(3856662528, section_attrs::SRAM).0,
L1Section::new(3857711104, section_attrs::SRAM).0,
L1Section::new(3825205248, section_attrs::SRAM).raw_value(),
L1Section::new(3826253824, section_attrs::SRAM).raw_value(),
L1Section::new(3827302400, section_attrs::SRAM).raw_value(),
L1Section::new(3828350976, section_attrs::SRAM).raw_value(),
L1Section::new(3829399552, section_attrs::SRAM).raw_value(),
L1Section::new(3830448128, section_attrs::SRAM).raw_value(),
L1Section::new(3831496704, section_attrs::SRAM).raw_value(),
L1Section::new(3832545280, section_attrs::SRAM).raw_value(),
L1Section::new(3833593856, section_attrs::SRAM).raw_value(),
L1Section::new(3834642432, section_attrs::SRAM).raw_value(),
L1Section::new(3835691008, section_attrs::SRAM).raw_value(),
L1Section::new(3836739584, section_attrs::SRAM).raw_value(),
L1Section::new(3837788160, section_attrs::SRAM).raw_value(),
L1Section::new(3838836736, section_attrs::SRAM).raw_value(),
L1Section::new(3839885312, section_attrs::SRAM).raw_value(),
L1Section::new(3840933888, section_attrs::SRAM).raw_value(),
L1Section::new(3841982464, section_attrs::SRAM).raw_value(),
L1Section::new(3843031040, section_attrs::SRAM).raw_value(),
L1Section::new(3844079616, section_attrs::SRAM).raw_value(),
L1Section::new(3845128192, section_attrs::SRAM).raw_value(),
L1Section::new(3846176768, section_attrs::SRAM).raw_value(),
L1Section::new(3847225344, section_attrs::SRAM).raw_value(),
L1Section::new(3848273920, section_attrs::SRAM).raw_value(),
L1Section::new(3849322496, section_attrs::SRAM).raw_value(),
L1Section::new(3850371072, section_attrs::SRAM).raw_value(),
L1Section::new(3851419648, section_attrs::SRAM).raw_value(),
L1Section::new(3852468224, section_attrs::SRAM).raw_value(),
L1Section::new(3853516800, section_attrs::SRAM).raw_value(),
L1Section::new(3854565376, section_attrs::SRAM).raw_value(),
L1Section::new(3855613952, section_attrs::SRAM).raw_value(),
L1Section::new(3856662528, section_attrs::SRAM).raw_value(),
L1Section::new(3857711104, section_attrs::SRAM).raw_value(),
// Unassigned/Reserved (0xE600_0000 - 0xF800_0000)
L1Section::new(3858759680, section_attrs::UNASSIGNED_RESERVED).raw_value(),
L1Section::new(3859808256, section_attrs::UNASSIGNED_RESERVED).raw_value(),

2
zynq7000-rt/src/rt.rs
View File

@ -4,7 +4,7 @@
//! [provided by Xilinx](https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexa9/gcc/boot.S)
//! as possible. The boot routine includes stack, MMU, cache and .bss/.data section initialization.
use cortex_a_rt as _;
use cortex_r_a::register::{cpsr::ProcessorMode, Cpsr};
use cortex_ar::register::{Cpsr, cpsr::ProcessorMode};
// Start-up code for Armv7-A
//