IT WORKS

Cargo.lock

@@ -138,6 +138,7 @@ name = "zynq-examples"
 version = "0.1.0"
 dependencies = [
  "cortex-ar",
+ "zynq7000",
  "zynq7000-rt",
 ]
 

zynq-examples/Cargo.toml

@@ -13,3 +13,4 @@ categories = ["embedded", "no-std", "hardware-support"]
 [dependencies]
 cortex-ar = { path = "../../cortex-ar/cortex-ar" }
 zynq7000-rt = { path = "../zynq7000-rt" }
+zynq7000 = { path = "../zynq7000" }

zynq-examples/src/main.rs

@@ -2,9 +2,12 @@
 #![no_main]
 
 use core::panic::PanicInfo;
-use cortex_r_a::asm::nop;
+use cortex_ar::asm::nop;
 use zynq7000_rt as _;
 
+/// One user LED is MIO7
+const ZEDBOARD_LED_MASK: u32 = 1 << 7;
+
 /// Entry point (not called like a normal main function)
 #[unsafe(no_mangle)]
 pub extern "C" fn boot_core(cpu_id: u32) -> ! {
@@ -16,8 +19,14 @@ pub extern "C" fn boot_core(cpu_id: u32) -> ! {
 
 #[unsafe(export_name = "main")]
 pub fn main() -> ! {
+    let mut gpio = unsafe { zynq7000::Gpio::new_mmio_fixed() };
+    gpio.write_xgpiops_dirm_offset(ZEDBOARD_LED_MASK);
+    gpio.write_xgpiops_outen_offset(ZEDBOARD_LED_MASK);
     loop {
-        nop();
+        gpio.modify_xgpiops_data_offset(|v| v ^ ZEDBOARD_LED_MASK);
+        for _ in 0..1_000_000 {
+            nop();
+        }
     }
 }
 

zynq7000-rt/src/bin/table-gen.rs

@@ -1,8 +1,8 @@
 use std::fs::File;
 use std::io::Write;
 use std::process::Command;
-pub use zynq7000_rt::mmu::segments::*;
 use zynq7000_rt::mmu::ONE_MB;
+pub use zynq7000_rt::mmu::segments::*;
 
 fn main() {
     let file_path = "src/mmu_table.rs";
@@ -63,12 +63,22 @@ fn main() {
         "// First DDR segment, OCM memory (0x0000_0000 - 0x0010_0000)"
     )
     .unwrap();
-    writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
+    writeln!(
+        buf_writer,
+        "L1Section::new({}, {}).raw_value(),",
+        offset, attr_ddr
+    )
+    .unwrap();
 
     offset += ONE_MB;
     writeln!(buf_writer, "// DDR memory (0x00100000 - 0x4000_0000)").unwrap();
     for _ in 0..DDR_FULL_ACCESSIBLE {
-        writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_ddr).unwrap();
+        writeln!(
+            buf_writer,
+            "L1Section::new({}, {}).raw_value(),",
+            offset, attr_ddr
+        )
+        .unwrap();
         offset += ONE_MB;
     }
 
@@ -163,7 +173,12 @@ fn main() {
 
     writeln!(buf_writer, "// SRAM (0xE400_0000 - 0xE600_0000)").unwrap();
     for _ in 0..SRAM {
-        writeln!(buf_writer, "L1Section::new({}, {}).0,", offset, attr_sram).unwrap();
+        writeln!(
+            buf_writer,
+            "L1Section::new({}, {}).raw_value(),",
+            offset, attr_sram
+        )
+        .unwrap();
         offset += ONE_MB;
     }
 
@@ -214,7 +229,12 @@ fn main() {
 
     writeln!(buf_writer, "// QSPI XIP (0xFC00_0000 - 0xFE00_0000)").unwrap();
     for _ in 0..QSPI_XIP {
-        writeln!(buf_writer, "L1Section::new({}, {}).raw_value(),", offset, attr_qspi).unwrap();
+        writeln!(
+            buf_writer,
+            "L1Section::new({}, {}).raw_value(),",
+            offset, attr_qspi
+        )
+        .unwrap();
         offset += ONE_MB;
     }
 

zynq7000-rt/src/mmu_table.rs

@@ -1,5 +1,5 @@
 //! This file was auto-generated by table-gen.rs
-use crate::mmu::{section_attrs, L1Table};
+use crate::mmu::{L1Table, section_attrs};
 use cortex_ar::mmu::L1Section;
 
 /// MMU Level 1 Page table.
@@ -3664,38 +3664,38 @@ pub const MMU_L1_PAGE_TABLE: L1Table = L1Table([
     L1Section::new(3823108096, section_attrs::SHAREABLE_DEVICE).raw_value(),
     L1Section::new(3824156672, section_attrs::SHAREABLE_DEVICE).raw_value(),
     // SRAM (0xE400_0000 - 0xE600_0000)
-    L1Section::new(3825205248, section_attrs::SRAM).0,
+    L1Section::new(3825205248, section_attrs::SRAM).raw_value(),
-    L1Section::new(3826253824, section_attrs::SRAM).0,
+    L1Section::new(3826253824, section_attrs::SRAM).raw_value(),
-    L1Section::new(3827302400, section_attrs::SRAM).0,
+    L1Section::new(3827302400, section_attrs::SRAM).raw_value(),
-    L1Section::new(3828350976, section_attrs::SRAM).0,
+    L1Section::new(3828350976, section_attrs::SRAM).raw_value(),
-    L1Section::new(3829399552, section_attrs::SRAM).0,
+    L1Section::new(3829399552, section_attrs::SRAM).raw_value(),
-    L1Section::new(3830448128, section_attrs::SRAM).0,
+    L1Section::new(3830448128, section_attrs::SRAM).raw_value(),
-    L1Section::new(3831496704, section_attrs::SRAM).0,
+    L1Section::new(3831496704, section_attrs::SRAM).raw_value(),
-    L1Section::new(3832545280, section_attrs::SRAM).0,
+    L1Section::new(3832545280, section_attrs::SRAM).raw_value(),
-    L1Section::new(3833593856, section_attrs::SRAM).0,
+    L1Section::new(3833593856, section_attrs::SRAM).raw_value(),
-    L1Section::new(3834642432, section_attrs::SRAM).0,
+    L1Section::new(3834642432, section_attrs::SRAM).raw_value(),
-    L1Section::new(3835691008, section_attrs::SRAM).0,
+    L1Section::new(3835691008, section_attrs::SRAM).raw_value(),
-    L1Section::new(3836739584, section_attrs::SRAM).0,
+    L1Section::new(3836739584, section_attrs::SRAM).raw_value(),
-    L1Section::new(3837788160, section_attrs::SRAM).0,
+    L1Section::new(3837788160, section_attrs::SRAM).raw_value(),
-    L1Section::new(3838836736, section_attrs::SRAM).0,
+    L1Section::new(3838836736, section_attrs::SRAM).raw_value(),
-    L1Section::new(3839885312, section_attrs::SRAM).0,
+    L1Section::new(3839885312, section_attrs::SRAM).raw_value(),
-    L1Section::new(3840933888, section_attrs::SRAM).0,
+    L1Section::new(3840933888, section_attrs::SRAM).raw_value(),
-    L1Section::new(3841982464, section_attrs::SRAM).0,
+    L1Section::new(3841982464, section_attrs::SRAM).raw_value(),
-    L1Section::new(3843031040, section_attrs::SRAM).0,
+    L1Section::new(3843031040, section_attrs::SRAM).raw_value(),
-    L1Section::new(3844079616, section_attrs::SRAM).0,
+    L1Section::new(3844079616, section_attrs::SRAM).raw_value(),
-    L1Section::new(3845128192, section_attrs::SRAM).0,
+    L1Section::new(3845128192, section_attrs::SRAM).raw_value(),
-    L1Section::new(3846176768, section_attrs::SRAM).0,
+    L1Section::new(3846176768, section_attrs::SRAM).raw_value(),
-    L1Section::new(3847225344, section_attrs::SRAM).0,
+    L1Section::new(3847225344, section_attrs::SRAM).raw_value(),
-    L1Section::new(3848273920, section_attrs::SRAM).0,
+    L1Section::new(3848273920, section_attrs::SRAM).raw_value(),
-    L1Section::new(3849322496, section_attrs::SRAM).0,
+    L1Section::new(3849322496, section_attrs::SRAM).raw_value(),
-    L1Section::new(3850371072, section_attrs::SRAM).0,
+    L1Section::new(3850371072, section_attrs::SRAM).raw_value(),
-    L1Section::new(3851419648, section_attrs::SRAM).0,
+    L1Section::new(3851419648, section_attrs::SRAM).raw_value(),
-    L1Section::new(3852468224, section_attrs::SRAM).0,
+    L1Section::new(3852468224, section_attrs::SRAM).raw_value(),
-    L1Section::new(3853516800, section_attrs::SRAM).0,
+    L1Section::new(3853516800, section_attrs::SRAM).raw_value(),
-    L1Section::new(3854565376, section_attrs::SRAM).0,
+    L1Section::new(3854565376, section_attrs::SRAM).raw_value(),
-    L1Section::new(3855613952, section_attrs::SRAM).0,
+    L1Section::new(3855613952, section_attrs::SRAM).raw_value(),
-    L1Section::new(3856662528, section_attrs::SRAM).0,
+    L1Section::new(3856662528, section_attrs::SRAM).raw_value(),
-    L1Section::new(3857711104, section_attrs::SRAM).0,
+    L1Section::new(3857711104, section_attrs::SRAM).raw_value(),
     // Unassigned/Reserved (0xE600_0000 - 0xF800_0000)
     L1Section::new(3858759680, section_attrs::UNASSIGNED_RESERVED).raw_value(),
     L1Section::new(3859808256, section_attrs::UNASSIGNED_RESERVED).raw_value(),

zynq7000-rt/src/rt.rs

@@ -4,7 +4,7 @@
 //! [provided by Xilinx](https://github.com/Xilinx/embeddedsw/blob/master/lib/bsp/standalone/src/arm/cortexa9/gcc/boot.S)
 //! as possible. The boot routine includes stack, MMU, cache and .bss/.data section initialization.
 use cortex_a_rt as _;
-use cortex_r_a::register::{cpsr::ProcessorMode, Cpsr};
+use cortex_ar::register::{Cpsr, cpsr::ProcessorMode};
 
 // Start-up code for Armv7-A
 //

zynq7000/build.rs

@@ -1,4 +1,3 @@
-
 fn main() {
     println!("cargo:rerun-if-changed=build.rs");
 }

zynq7000/src/lib.rs

@@ -1,2 +1,119 @@
 //! Rust peripheral acess crate to the AMD Zynq 7000 SoCs
 #![no_std]
+
+#[derive(derive_mmio::Mmio)]
+#[repr(C)]
+pub struct Gpio {
+    /// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
+    xgpiops_data_lsw_offset: u32,
+    /// Maskable output data (GPIO bank 0, MIO, upper 16 bits)
+    xgpiops_data_msw_offset: u32,
+    /// Maskable output data (GPIO bank 1, MIO, lower 16 bits)
+    mask_data_1_lsw: u32,
+    /// Maskable output data (GPIO bank 1, MIO, upper 16 bits)
+    mask_data_1_msw: u32,
+    /// Maskable output data (GPIO bank 2, EMIO, lower 16 bits)
+    mask_data_2_lsw: u32,
+    /// Maskable output data (GPIO bank 2, EMIO, upper 16 bits)
+    mask_data_2_msw: u32,
+    /// Maskable output data (GPIO bank 3, EMIO, lower 16 bits)
+    mask_data_3_lsw: u32,
+    /// Maskable output data (GPIO bank 3, EMIO, upper 16 bits)
+    mask_data_3_msw: u32,
+    _reserved_0: [u32; 8],
+    /// Output data (GPIO bank 0, MIO)
+    xgpiops_data_offset: u32,
+    /// Output data (GPIO bank 1, MIO)
+    data_1: u32,
+    /// Output data (GPIO bank 2, EMIO)
+    data_2: u32,
+    /// Output data (GPIO bank 3, EMIO)
+    data_3: u32,
+
+    _reserved_1: [u32; 4],
+
+    /// Input data (GPIO bank 0, MIO)
+    data_0_ro: u32,
+    /// Input data (GPIO bank 1, MIO)
+    data_1_ro: u32,
+    /// Input data (GPIO bank 2, EMIO)
+    data_2_ro: u32,
+    /// Input data (GPIO bank 3, EMIO)
+    data_3_ro: u32,
+
+    _reserved_2: [u32; 101],
+
+    /// Direction mode (GPIO bank 0, MIO)
+    xgpiops_dirm_offset: u32,
+    /// Output enable (GPIO bank 0, MIO)
+    xgpiops_outen_offset: u32,
+    /// Interrupt mask status (GPIO bank 0, MIO)
+    xgpiops_intmask_offset: u32,
+    /// Interrupt enable/unmask (GPIO bank 0, MIO)
+    xgpiops_inten_offset: u32,
+    /// Interrupt disable/mask (GPIO bank 0, MIO)
+    xgpiops_intdis_offset: u32,
+    /// Interrupt status (GPIO bank 0, MIO)
+    xgpiops_intsts_offset: u32,
+    /// Interrupt type (GPIO bank 0, MIO)
+    xgpiops_inttype_offset: u32,
+    /// Interrupt polarity (GPIO bank 0, MIO)
+    xgpiops_intpol_offset: u32,
+    /// Interrupt any edge sensitivity (GPIO bank 0, MIO)
+    xgpiops_intany_offset: u32,
+
+    _reserved_3: [u32; 8],
+
+    /// Direction mode (GPIO bank 1, MIO)
+    dirm_1: u32,
+    /// Output enable (GPIO bank 1, MIO)
+    outen_1: u32,
+    /// Interrupt mask status (GPIO bank 1, MIO)
+    int_mask_1: u32,
+    /// Interrupt enable/unmask (GPIO bank 1, MIO)
+    int_en_1: u32,
+    /// Interrupt disable/mask (GPIO bank 1, MIO)
+    int_dis_1: u32,
+    /// Interrupt status (GPIO bank 1, MIO)
+    int_sts_1: u32,
+    /// Interrupt type (GPIO bank 1, MIO)
+    int_type_1: u32,
+    /// Interrupt polarity (GPIO bank 1, MIO)
+    int_pol_1: u32,
+    /// Interrupt any edge sensitivity (GPIO bank 1, MIO)
+    int_any_1: u32,
+
+    _reserved_4: [u32; 8],
+
+    /// Direction mode (GPIO bank 2, MIO)
+    dirm_2: u32,
+    /// Output enable (GPIO bank 2, MIO)
+    outen_2: u32,
+    /// Interrupt mask status (GPIO bank 2, MIO)
+    int_mask_2: u32,
+    /// Interrupt enable/unmask (GPIO bank 2, MIO)
+    int_en_2: u32,
+    /// Interrupt disable/mask (GPIO bank 2, MIO)
+    int_dis_2: u32,
+    /// Interrupt status (GPIO bank 2, MIO)
+    int_sts_2: u32,
+    /// Interrupt type (GPIO bank 2, MIO)
+    int_type_2: u32,
+    /// Interrupt polarity (GPIO bank 2, MIO)
+    int_pol_2: u32,
+    /// Interrupt any edge sensitivity (GPIO bank 2, MIO)
+    int_any_2: u32,
+}
+
+impl Gpio {
+    /// Create a new XGPIOPS GPIO MMIO instance.
+    ///
+    /// # Safety
+    ///
+    /// This API can be used to potentially create a driver to the same peripheral structure
+    /// from multiple threads. The user must ensure that concurrent accesses are safe and do not
+    /// interfere with each other.
+    pub unsafe fn new_mmio_fixed() -> MmioGpio {
+        unsafe { Self::new_mmio_at(0xE000A000) }
+    }
+}