Merge pull request 'improve HAL docs' (#18) from improve-hal-docs into main

Reviewed-on: #18

.gitignore

@@ -1,7 +1,7 @@
 target
+xsct-output.log
+app.map
 
-/app.map
-/xsct-output.log
 /.vscode
 /Cargo.lock
 /.cargo/config.toml

README.md

@@ -111,7 +111,8 @@ target = "armv7a-none-eabihf"
 You can build the blinky example app using
 
 ```sh
-cargo build --example simple
+cd zynq
+cargo build --bin blinky
 ```
 
 

zynq/zedboard-bsp/src/ddrc_config_autogen.rs

@@ -1,7 +1,7 @@
 #![doc = r"This file was auto-generated by the [zynq7000-ps7init-extract](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/tools/zynq7000-ps7init-extract) program."]
 #![doc = r""]
 #![doc = r"This configuration file contains static DDR configuration parameters extracted from the"]
-#![doc = r"AMD ps7init.tcl file"]
+#![doc = r"AMD ps7init.tcl file. It was generated for the MT41K128M16JT-125 DDR chip."]
 use zynq7000::ddrc::regs;
 use zynq7000_hal::ddr::DdrcConfigSet;
 pub const DDRC_CONFIG_ZEDBOARD: DdrcConfigSet = DdrcConfigSet {

zynq/zedboard-bsp/src/ddriob_config_autogen.rs

@@ -1,7 +1,7 @@
 #![doc = r"This file was auto-generated by the [zynq7000-ps7init-extract](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/tools/zynq7000-ps7init-extract) program."]
 #![doc = r""]
 #![doc = r"This configuration file contains static DDRIOB configuration parameters extracted from the"]
-#![doc = r"AMD ps7init.tcl file"]
+#![doc = r"AMD ps7init.tcl file. It was generated for the MT41K128M16JT-125 DDR chip."]
 use zynq7000::ddrc::regs;
 use zynq7000_hal::ddr::DdriobConfigSet;
 pub const DDRIOB_CONFIG_SET_ZEDBOARD: DdriobConfigSet = DdriobConfigSet {

zynq/zynq7000-embassy/CHANGELOG.md

@@ -8,7 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # [unreleased]
 
-# [v0.1.0] 2025-10-08
+# [v0.1.0] 2025-10-09
 
 Initial release
 

zynq/zynq7000-hal/CHANGELOG.md

@@ -8,9 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # [unreleased]
 
+# [v0.1.1] 2025-10-10
+
+Documentation fixes.
+
 # [v0.1.0] 2025-10-09
 
 Initial release
 
 [unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-hal-v0.1.0...HEAD
+[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-hal-v0.1.0...zynq7000-hal-v0.1.1
 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tag/zynq7000-hal-v0.1.0

zynq/zynq7000-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "zynq7000-hal"
-version = "0.1.0"
+version = "0.1.1"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2024"
 description = "Hardware Abstraction Layer (HAL) for the Zynq7000 family of SoCs"
@@ -52,4 +52,6 @@ approx = "0.5"
 
 [package.metadata.docs.rs]
 features = ["alloc"]
+targets = ["armv7a-none-eabihf"]
+cargo-args = ["-Z", "build-std=core,alloc"]
 rustdoc-args = ["--generate-link-to-definition"]

zynq/zynq7000-hal/src/cache.rs

@@ -1,3 +1,7 @@
+//! # Cache management module
+//!
+//! A lot of cache maintenance operations for this SoC have to be performed on both the L1 and the
+//! L2 cache in the correct order. This module provides commonly required operations.
 use core::sync::atomic::compiler_fence;
 
 use cortex_ar::{

zynq/zynq7000-hal/src/clocks/mod.rs

@@ -1,4 +1,8 @@
-//! Clock module.
+//! # Clock module
+//!
+//! ## Examples
+//!
+//! - PLL initialization in [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::{prelude::*, u6};
 
 pub mod pll;

zynq/zynq7000-hal/src/ddr/mod.rs

@@ -1,3 +1,8 @@
+//! # DDR module
+//!
+//! ## Examples
+//!
+//! - [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
 use arbitrary_int::u6;
 use zynq7000::ddrc::MmioDdrController;
 

zynq/zynq7000-hal/src/devcfg.rs

@@ -1,3 +1,4 @@
+//! # Device Configuration Module
 #[derive(Debug, thiserror::Error)]
 #[error("unaligned address: {0}")]
 pub struct UnalignedAddrError(usize);

zynq/zynq7000-hal/src/eth/mod.rs

@@ -1,3 +1,8 @@
+//! # Ethernet module
+//!
+//! ## Examples
+//!
+//! - [Zedboard Ethernet](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/ethernet.rs)
 use arbitrary_int::{u2, u3};
 pub use zynq7000::eth::MdcClockDivisor;
 use zynq7000::eth::{

zynq/zynq7000-hal/src/gic.rs

@@ -1,4 +1,4 @@
-//! Global Interrupt Controller (GIC) module.
+//! # Global Interrupt Controller (GIC) module
 //!
 //! The primary interface to configure and allow handling the interrupts are the
 //! [GicConfigurator] and the [GicInterruptHelper] structures.
@@ -191,9 +191,9 @@ pub struct InvalidSgiInterruptId(pub usize);
 ///
 /// The flow of using this controller is as follows:
 ///
-/// 1. Create the controller using [Self::new_with_init]. You can use the [zynq7000::PsPeripherals]
+/// 1. Create the controller using [Self::new_with_init]. You can use the [zynq7000::Peripherals]
 ///    structure or the [zynq7000::gic::GicCpuInterface::new_mmio] and [zynq7000::gic::GicDistributor::new_mmio]
-///    functions  to create the MMIO instances. The constructor configures all PL interrupts
+///    functions to retrieve the MMIO instances. The constructor configures all PL interrupts
 ///    sensivities to high-level sensitivity and configures all sensitivities which are expected
 ///    to have a certain value. It also sets the priority mask to 0xff by calling
 ///    [Self::set_priority_mask] to prevent masking of the interrupts.

zynq/zynq7000-hal/src/gpio/mod.rs

@@ -1,12 +1,12 @@
-//! GPIO support module for the Zynq7000 SoC.
+//! # GPIO module
 //!
 //! This module contains a MIO and EMIO pin resource managements singleton as well as abstractions
 //! to use these pins as GPIOs.
 //!
 //! # Examples
 //!
-//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/main.rs)
-//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/logger.rs)
+//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/main.rs)
+//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
 //!   which uses MIO pins for the UART.
 pub mod emio;
 pub mod ll;

zynq/zynq7000-hal/src/gtc.rs

@@ -1,9 +1,9 @@
-//! Global timer counter driver module.
+//! # Global timer counter driver module
 //!
-//! # Examples
+//! ## Examples
 //!
-//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
-//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq7000-embassy/src/lib.rs)
+//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/gtc-ticks.rs)
+//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zynq7000-embassy/src/lib.rs)
 use zynq7000::gtc::MmioGlobalTimerCounter;
 
 use crate::{clocks::ArmClocks, time::Hertz};

zynq/zynq7000-hal/src/i2c.rs

@@ -1,3 +1,4 @@
+//! # I2C module
 use arbitrary_int::{u2, u3, u6};
 use embedded_hal::i2c::NoAcknowledgeSource;
 use zynq7000::{

zynq/zynq7000-hal/src/l2_cache.rs

@@ -1,3 +1,4 @@
+//! # L2 cache module
 use core::sync::atomic::compiler_fence;
 
 use arbitrary_int::{u2, u3};

zynq/zynq7000-hal/src/lib.rs

@@ -7,6 +7,11 @@
 //! raw PAC. This crate also implements traits specified by the
 //! [embedded-hal](https://github.com/rust-embedded/embedded-hal) project, making it compatible with
 //! various drivers in the embedded rust ecosystem.
+//!
+//! ## Examples
+//!
+//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples)
+//! of the project
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_cfg))]
 

zynq/zynq7000-hal/src/log.rs

@@ -1,4 +1,9 @@
-//! # Simple logging providers.
+//! # Simple logging providers
+//!
+//! ## Examples
+//!
+//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
+//!   which uses MIO pins for the UART.
 
 use core::sync::atomic::{AtomicBool, AtomicU8};
 

zynq/zynq7000-hal/src/priv_tim.rs

@@ -1,3 +1,8 @@
+//! # CPU private timer module
+//!
+//! ## Examples
+//!
+//! - Private timer as delay provider in [blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/blinky.rs)
 use core::{marker::PhantomData, sync::atomic::AtomicBool};
 
 use zynq7000::priv_tim::InterruptStatus;

zynq/zynq7000-hal/src/qspi/mod.rs

@@ -1,3 +1,8 @@
+//! # QSPI module
+//!
+//! ## Examples
+//!
+//! - [Zedboard QSPI](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/qspi.rs)
 use core::ops::{Deref, DerefMut};
 
 use arbitrary_int::{prelude::*, u2, u3, u6};

zynq/zynq7000-hal/src/slcr.rs

@@ -1,4 +1,4 @@
-//! # System Level Control Register (SLCR) module.
+//! # System Level Control Register (SLCR) module
 use zynq7000::slcr::MmioSlcr;
 
 pub const LOCK_KEY: u32 = 0x767B;

zynq/zynq7000-hal/src/spi/mod.rs

@@ -1,4 +1,8 @@
-//! PS SPI HAL driver.
+//! SPI module
+//!
+//! ## Examples
+//!
+//! - [L3GD20H SPI sensor](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs)
 use core::convert::Infallible;
 
 use crate::clocks::Clocks;

zynq/zynq7000-hal/src/time.rs

@@ -1,4 +1,4 @@
-//! Time units
+//! # Time units
 
 // Frequency based
 

zynq/zynq7000-hal/src/ttc.rs

@@ -1,6 +1,10 @@
-//! Triple-timer counter (TTC) high-level driver.
+//! # Triple-timer counter (TTC) high-level driver
 //!
 //! This module also contains support for PWM and output waveform generation.
+//!
+//! ## Examples
+//!
+//! - [PWM](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/embassy/src/bin/pwm.rs)
 
 use core::convert::Infallible;
 

zynq/zynq7000-hal/src/uart/mod.rs

@@ -1,6 +1,12 @@
-//! # UART module.
+//! # UART module
 //!
 //! Support for the processing system UARTs.
+//!
+//! ## Examples
+//!
+//! - [Logger through UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
+//! - [Zedboard Blocking UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/uart-blocking.rs)
+//! - [Zedboard Non-Blocking UART](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/uart-non-blocking.rs)
 use core::convert::Infallible;
 
 use arbitrary_int::u3;

zynq/zynq7000-mmu/CHANGELOG.md

@@ -8,9 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # [unreleased]
 
+# [v0.1.1] 2025-10-10
+
+Documentation fixes.
+
 # [v0.1.0] 2025-10-09
 
 Initial release
 
 [unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-mmu-v0.1.0...HEAD
+[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-mmu-v0.1.0...zynq7000-mmu-v0.1.1
 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tag/zynq7000-mmu-v0.1.0

zynq/zynq7000-mmu/Cargo.toml

@@ -1,7 +1,7 @@
 [package]
 name = "zynq7000-mmu"
 description = "Zynq7000 MMU structures"
-version = "0.1.0"
+version = "0.1.1"
 edition = "2024"
 license = "MIT OR Apache-2.0"
 homepage = "https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs"
@@ -13,5 +13,13 @@ categories = ["embedded", "no-std", "hardware-support"]
 thiserror = { version = "2", default-features = false }
 cortex-ar = { version = "0.3" }
 
+[build-dependencies]
+arm-targets = { version = "0.3" }
+
 [features]
 tools = []
+
+[package.metadata.docs.rs]
+targets = ["armv7a-none-eabihf"]
+cargo-args = ["-Z", "build-std=core"]
+rustdoc-args = ["--generate-link-to-definition"]

zynq/zynq7000-mmu/README.md

@@ -1,3 +1,7 @@
+[![Crates.io](https://img.shields.io/crates/v/zynq7000-mmu)](https://crates.io/crates/zynq7000-mmu)
+[![docs.rs](https://img.shields.io/docsrs/zynq7000-mmu)](https://docs.rs/zynq7000-mmu)
+[![ci](https://github.com/us-irs/zynq7000-rs/actions/workflows/ci.yml/badge.svg?branch=main)](https://github.com/us-irs/zynq7000-rs/actions/workflows/ci.yml)
+
 Zynq7000 Memory Management Unit (MMU) library
 =========
 

zynq/zynq7000-mmu/build.rs

@@ -0,0 +1,3 @@
+fn main() {
+    arm_targets::process();
+}

zynq/zynq7000-mmu/src/lib.rs

@@ -1,4 +1,4 @@
-//! # Zynq7000 Memory Management Unit (MMU) 
+//! # Zynq7000 Memory Management Unit (MMU)
 //!
 //! Dedicated shared crate for Zynq7000 MMU abstractions which can be used by Zynq
 //! runtime crates, PACs and HALs.
@@ -7,7 +7,7 @@
 
 use core::cell::UnsafeCell;
 use cortex_ar::mmu::L1Section;
-#[cfg(not(feature = "tools"))]
+#[cfg(all(not(feature = "tools"), arm_profile = "a"))]
 use cortex_ar::{
     asm::{dsb, isb},
     cache::clean_and_invalidate_l1_data_cache,
@@ -39,7 +39,7 @@ impl L1TableRaw {
         self.0.as_mut_ptr() as *mut _
     }
 
-    #[cfg(not(feature = "tools"))]
+    #[cfg(all(not(feature = "tools"), arm_profile = "a"))]
     pub fn update(
         &mut self,
         addr: u32,
@@ -92,7 +92,7 @@ impl<'a> L1TableWrapper<'a> {
 }
 
 impl L1TableWrapper<'_> {
-    #[cfg(not(feature = "tools"))]
+    #[cfg(all(not(feature = "tools"), arm_profile = "a"))]
     pub fn update(
         &mut self,
         addr: u32,

zynq/zynq7000-rt/CHANGELOG.md

@@ -8,9 +8,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 # [unreleased]
 
+# [v0.1.1] 2025-10-10
+
+Documentation fixes.
+
 # [v0.1.0] 2025-10-09
 
 Initial release
 
 [unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.0...HEAD
+[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-rt-v0.1.0...zynq7000-rt-v0.1.1
 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/tag/zynq7000-rt-v0.1.0

zynq/zynq7000-rt/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "zynq7000-rt"
-version = "0.1.0"
+version = "0.1.1"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2024"
 description = "Run-time support for the Zynq7000 family of SoCs for running bare-metal applications"
@@ -16,9 +16,14 @@ cortex-ar = { version = "0.3" }
 arbitrary-int = "2"
 zynq7000-mmu = { path = "../zynq7000-mmu", version = "0.1" }
 
+[build-dependencies]
+arm-targets = { version = "0.3" }
+
 [features]
 default = ["rt"]
 rt = ["dep:cortex-a-rt"]
 
 [package.metadata.docs.rs]
+targets = ["armv7a-none-eabihf"]
+cargo-args = ["-Z", "build-std=core"]
 rustdoc-args = ["--generate-link-to-definition"]

zynq/zynq7000-rt/build.rs

@@ -0,0 +1,3 @@
+fn main() {
+    arm_targets::process();
+}

zynq/zynq7000-rt/src/lib.rs

@@ -9,20 +9,20 @@
 //! - Modification to the stack setup code, because a different linker script is used.
 #![no_std]
 #![cfg_attr(docsrs, feature(doc_cfg))]
-#[cfg(feature = "rt")]
+#[cfg(all(feature = "rt", arm_profile = "a"))]
 pub use cortex_a_rt::*;
 
 #[cfg(feature = "rt")]
 use zynq7000_mmu::L1TableWrapper;
 
 pub mod mmu;
-#[cfg(feature = "rt")]
+#[cfg(all(feature = "rt", arm_profile = "a"))]
 mod mmu_table;
-#[cfg(feature = "rt")]
+#[cfg(all(feature = "rt", arm_profile = "a"))]
 pub mod rt;
 
 /// Retrieves a mutable reference to the MMU L1 page table.
-#[cfg(feature = "rt")]
+#[cfg(all(feature = "rt", arm_profile = "a"))]
 pub fn mmu_l1_table_mut() -> L1TableWrapper<'static> {
     let mmu_table = mmu_table::MMU_L1_PAGE_TABLE.0.get();
     // Safety: We retrieve a reference to the MMU page table singleton.

zynq/zynq7000/CHANGELOG.md

@@ -17,5 +17,5 @@ Documentation fix
 Initial release
 
 [unreleased]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.1...HEAD
-[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.0...zynq7000-0.1.1
+[v0.1.1]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/compare/zynq7000-v0.1.0...zynq7000-v0.1.1
 [v0.1.0]: https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/tag/zynq7000-v0.1.0

zynq/zynq7000/Cargo.toml

@@ -23,4 +23,6 @@ once_cell = { version = "1", default-features = false, features = ["critical-sec
 approx = "0.5"
 
 [package.metadata.docs.rs]
+targets = ["armv7a-none-eabihf"]
+cargo-args = ["-Z", "build-std=core"]
 rustdoc-args = ["--generate-link-to-definition"]

zynq/zynq7000/src/ddrc.rs

@@ -725,6 +725,7 @@ pub mod regs {
 
 use regs::*;
 
+/// DDR controller register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DdrController {

zynq/zynq7000/src/devcfg.rs

@@ -257,6 +257,7 @@ pub struct Status {
     efuse_jtag_disabled: bool,
 }
 
+/// Device configuration register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct DevCfg {

zynq/zynq7000/src/eth.rs

@@ -418,7 +418,7 @@ pub struct MatchRegister {
     type_id: u16,
 }
 
-/// Gigabit Ethernet Controller (GEM) registers for Zynq-7000
+/// Gigabit Ethernet Controller (GEM) register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ethernet {
@@ -477,7 +477,7 @@ pub struct Ethernet {
 
 static_assertions::const_assert_eq!(core::mem::size_of::<Ethernet>(), 0x294);
 
-/// GEM statistics registers
+/// Ethernet statistics registers
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Statistics {

zynq/zynq7000/src/gpio.rs

@@ -35,6 +35,7 @@ pub struct BankControl {
     int_any: u32,
 }
 
+/// GPIO register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Gpio {

zynq/zynq7000/src/gtc.rs

@@ -22,7 +22,7 @@ pub struct InterruptStatus {
     event_flag: bool,
 }
 
-/// Global timer counter.
+/// Global timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct GlobalTimerCounter {

zynq/zynq7000/src/i2c.rs

@@ -156,6 +156,7 @@ pub struct TransferSize {
     size: u8,
 }
 
+/// I2C register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct I2c {

zynq/zynq7000/src/l2_cache.rs

@@ -184,6 +184,7 @@ pub struct InterruptControl {
     event_counter_overflow_increment: bool,
 }
 
+/// L2 Cache register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct L2Cache {

zynq/zynq7000/src/mpcore.rs

@@ -44,6 +44,7 @@ impl SnoopControlUnit {
 
 const_assert_eq!(core::mem::size_of::<SnoopControlUnit>(), 0x58);
 
+/// MP Core register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct MpCore {

zynq/zynq7000/src/priv_tim.rs

@@ -21,6 +21,7 @@ pub struct InterruptStatus {
     event_flag: bool,
 }
 
+/// CPU private timer register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct CpuPrivateTimer {

zynq/zynq7000/src/qspi.rs

@@ -220,6 +220,7 @@ pub struct LinearQspiStatus {
     axi_write_command_received: bool,
 }
 
+/// QSPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Qspi {

zynq/zynq7000/src/slcr/mod.rs

@@ -91,7 +91,7 @@ pub struct LevelShifterRegister {
     user_lvl_shftr_en: Option<LevelShifterConfig>,
 }
 
-/// System Level Control Registers
+/// System Level Control Registers access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Slcr {

zynq/zynq7000/src/spi.rs

@@ -178,7 +178,7 @@ pub struct DelayControl {
     cs_to_first_bit: u8,
 }
 
-/// Register block specification for both PS SPIs.
+/// SPI register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Spi {

zynq/zynq7000/src/ttc.rs

@@ -142,7 +142,7 @@ pub struct EventCount {
     count: u16,
 }
 
-/// Triple-timer counter
+/// Triple-timer counter register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Ttc {

zynq/zynq7000/src/uart.rs

@@ -278,6 +278,7 @@ impl InterruptStatus {
     }
 }
 
+/// UART register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct Uart {

zynq/zynq7000/src/xadc.rs

@@ -1,5 +1,6 @@
 pub const XADC_BASE_ADDR: usize = 0xF8007100;
 
+/// XADC register access.
 #[derive(derive_mmio::Mmio)]
 #[repr(C)]
 pub struct XAdc {