improve repository structure #36
@@ -13,7 +13,7 @@ aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
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zynq7000-rt = { path = "../zynq7000-rt" }
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zynq7000 = { path = "../zynq7000" }
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zynq7000-hal = { path = "../zynq7000-hal" }
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zynq7000-boot-image = { path = "../../zynq7000-boot-image" }
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zynq7000-boot-image = { path = "../../host/zynq7000-boot-image" }
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zedboard-bsp = { path = "../zedboard-bsp" }
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embedded-io = "0.7"
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embedded-hal = "1"
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@@ -8,7 +8,7 @@ aarch32-cpu = { version = "0.1", features = ["critical-section-single-core"] }
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zynq7000-rt = { path = "../zynq7000-rt" }
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zynq7000 = { path = "../zynq7000" }
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zynq7000-hal = { path = "../zynq7000-hal" }
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zynq7000-boot-image = { path = "../../zynq7000-boot-image" }
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zynq7000-boot-image = { path = "../../host/zynq7000-boot-image" }
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zedboard-bsp = { path = "../zedboard-bsp" }
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embedded-io = "0.7"
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embedded-hal = "1"
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@@ -1,8 +1,4 @@
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//! # Clock module
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//!
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//! ## Examples
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//!
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//! - PLL initialization in [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
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use arbitrary_int::{prelude::*, u6};
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pub mod pll;
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@@ -1,3 +1,4 @@
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//! # PLL support module
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use core::sync::atomic::AtomicBool;
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use arbitrary_int::{u4, u7, u10};
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@@ -1,8 +1,4 @@
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//! # DDR module
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//!
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//! ## Examples
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//!
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//! - [Zedboard FSBL](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zedboard-fsbl)
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use arbitrary_int::u6;
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use zynq7000::ddrc::MmioRegisters;
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@@ -1,8 +1,4 @@
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//! # Ethernet module
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//!
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//! ## Examples
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//!
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//! - [Zedboard Ethernet](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/ethernet.rs)
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use arbitrary_int::{u2, u3};
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pub use zynq7000::eth::MdcClockDivisor;
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use zynq7000::eth::{
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@@ -2,10 +2,6 @@
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//!
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//! The primary interface to configure and allow handling the interrupts are the
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//! [GicConfigurator] and the [GicInterruptHelper] structures.
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//!
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//! # Examples
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//!
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//! - [GTC ticks](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/examples/simple/src/bin/gtc-ticks.rs)
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#![deny(missing_docs)]
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use arbitrary_int::prelude::*;
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@@ -314,7 +310,7 @@ pub struct InvalidSgiInterruptId(pub usize);
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/// to have a certain value. It also sets the priority mask to 0xff by calling
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/// [Self::set_priority_mask] to prevent masking of the interrupts.
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/// 2. Perform the configuration of the interrupt targets and the interrupt sensitivities.
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/// The CPU targets are encoded with [TargetCpu] while the sensitivities are encoded by
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/// The CPU targets are encoded with [TargetCpus] while the sensitivities are encoded by
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/// the [SpiSensitivity] enum. You can use the following (helper) API to configure the
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/// interrupts:
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///
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@@ -2,12 +2,6 @@
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//!
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//! This module contains a MIO and EMIO pin resource managements singleton as well as abstractions
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//! to use these pins as GPIOs.
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//!
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//! # Examples
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//!
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//! - [Blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/main.rs)
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//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
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//! which uses MIO pins for the UART.
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pub mod emio;
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pub mod ll;
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pub mod mio;
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@@ -1,9 +1,4 @@
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//! # Global timer counter driver module
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//!
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//! ## Examples
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//!
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//! - [GTC ticks example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/gtc-ticks.rs)
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//! - [Embassy Timer Driver](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/zynq7000-embassy/src/lib.rs)
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#![deny(missing_docs)]
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use zynq7000::gtc::MmioRegisters;
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@@ -10,8 +10,8 @@
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//!
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//! ## Examples
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//!
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//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples)
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//! of the project
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//! All exaples can be found inside the [examples folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/firmware/examples)
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//! and [firmware folder](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/firmware) of the project
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#![no_std]
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#![cfg_attr(docsrs, feature(doc_cfg))]
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@@ -1,9 +1,4 @@
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//! # Simple logging providers
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//!
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//! ## Examples
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//!
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//! - [Logger example](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/logger.rs)
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//! which uses MIO pins for the UART.
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use core::sync::atomic::{AtomicBool, AtomicU8};
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@@ -1,8 +1,4 @@
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//! # CPU private timer module
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//!
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//! ## Examples
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//!
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//! - Private timer as delay provider in [blinky](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/simple/src/bin/blinky.rs)
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#![deny(missing_docs)]
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use core::{marker::PhantomData, sync::atomic::AtomicBool};
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@@ -1,8 +1,4 @@
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//! # QSPI module
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//!
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//! ## Examples
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//!
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//! - [Zedboard QSPI](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/qspi.rs)
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use core::ops::{Deref, DerefMut};
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use arbitrary_int::{prelude::*, u2, u3, u6};
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@@ -1,8 +1,4 @@
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//! SPI module
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//!
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//! ## Examples
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//!
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//! - [L3GD20H SPI sensor](https://egit.irs.uni-stuttgart.de/rust/zynq7000-rs/src/branch/main/zynq/examples/zedboard/src/bin/l3gd20h-spi-mio.rs)
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use core::convert::Infallible;
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use crate::clocks::Clocks;
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