rust/zynq7000-rs
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bugfix for PL programming routine #38

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muellerr merged 1 commits from pl-programming-bugfix into main 2026-02-07 01:36:05 +01:00
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+7 -3
1 changed files with 7 additions and 3 deletions
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firmware/zynq7000-hal/src/devcfg.rs
+7 -3
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@@ -53,10 +53,14 @@ pub fn configure_bitstream_non_secure(
val.set_pcap_rate_enable(false);
val
});
devcfg.write_dma_source_addr(bitstream.as_ptr() as u32);
// As specified in the TMR,
// Setting the two LSBs of the source and destination address to 2'b01 indicates to the DevC
// DMA module the last DMA command of an overall transfer
devcfg.write_dma_source_addr(bitstream.as_ptr() as u32 | 0b01);
devcfg.write_dma_dest_addr(0xFFFF_FFFF);
devcfg.write_dma_source_len(bitstream.len() as u32);
devcfg.write_dma_dest_len(bitstream.len() as u32);
devcfg.write_dma_source_len(bitstream.len() as u32 / 4);
devcfg.write_dma_dest_len(bitstream.len() as u32 / 4);
while !devcfg.read_interrupt_status().dma_done() {}
// TODO: Check for errors.