firmware/zynq7000-hal/CHANGELOG.md

@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   interrupts without clearing other CPU target.
 - Do not reset the UART on TX future creation anymore, which lead to glitches and invalid data.
 - Robustness improvements for the asynchronous UART TX module.
+- SPI1 AMBA clock control bits are now enabled and disabled properly
 
 ## Changed
 

firmware/zynq7000-hal/src/lib.rs

@@ -208,7 +208,7 @@ pub fn enable_amba_peripheral_clock(select: PeriphSelect) {
                     PeriphSelect::Can1 => val.set_can_1_1x_clk_act(true),
                     PeriphSelect::Can0 => val.set_can_0_1x_clk_act(true),
                     PeriphSelect::Spi1 => val.set_spi_1_1x_clk_act(true),
-                    PeriphSelect::Spi0 => val.set_spi_1_1x_clk_act(true),
+                    PeriphSelect::Spi0 => val.set_spi_0_1x_clk_act(true),
                     PeriphSelect::Sdio1 => val.set_sdio_1_1x_clk_act(true),
                     PeriphSelect::Sdio0 => val.set_sdio_0_1x_clk_act(true),
                     PeriphSelect::Gem1 => val.set_gem_1_1x_clk_act(true),
@@ -241,7 +241,7 @@ pub fn disable_amba_periph_clk(select: PeriphSelect) {
                     PeriphSelect::Can1 => val.set_can_1_1x_clk_act(false),
                     PeriphSelect::Can0 => val.set_can_0_1x_clk_act(false),
                     PeriphSelect::Spi1 => val.set_spi_1_1x_clk_act(false),
-                    PeriphSelect::Spi0 => val.set_spi_1_1x_clk_act(false),
+                    PeriphSelect::Spi0 => val.set_spi_0_1x_clk_act(false),
                     PeriphSelect::Sdio1 => val.set_sdio_1_1x_clk_act(false),
                     PeriphSelect::Sdio0 => val.set_sdio_0_1x_clk_act(false),
                     PeriphSelect::Gem1 => val.set_gem_1_1x_clk_act(false),