rust/zynq7000-rs
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improve register names #79

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muellerr merged 1 commits from improve-register-names into main 2026-05-08 16:48:14 +02:00
Conversation 0 Commits 1 Files Changed 10
+54 -55
10 changed files with 54 additions and 55 deletions
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firmware/zynq7000-hal/src/gtc.rs
+8 -8
View File
@@ -75,13 +75,13 @@ impl GlobalTimerCounter {
/// Set the comparator which can be used to trigger an interrupt in the future.
#[inline]
pub fn set_comparator(&mut self, comparator: u64) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_comparator_enable(false);
ctrl
});
self.regs.write_comparator_upper((comparator >> 32) as u32);
self.regs.write_comparator_lower(comparator as u32);
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_comparator_enable(true);
ctrl
});
@@ -112,7 +112,7 @@ impl GlobalTimerCounter {
/// Enable the GTC.
#[inline]
pub fn enable(&mut self) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_enable(true);
ctrl
});
@@ -121,7 +121,7 @@ impl GlobalTimerCounter {
/// Enable auto-increment.
#[inline]
pub fn enable_auto_increment(&mut self) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_auto_increment(true);
ctrl
});
@@ -130,7 +130,7 @@ impl GlobalTimerCounter {
/// Set a pre-scaler.
#[inline]
pub fn set_prescaler(&mut self, prescaler: u8) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_prescaler(prescaler);
ctrl
});
@@ -139,7 +139,7 @@ impl GlobalTimerCounter {
/// Disable the GTC.
#[inline]
pub fn disable(&mut self) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_enable(false);
ctrl
});
@@ -148,7 +148,7 @@ impl GlobalTimerCounter {
/// Enable the comparator interrupt.
#[inline]
pub fn enable_interrupt(&mut self) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_irq_enable(true);
ctrl
});
@@ -157,7 +157,7 @@ impl GlobalTimerCounter {
/// Disable the comparator interrupt.
#[inline]
pub fn disable_interrupt(&mut self) {
self.regs.modify_ctrl(|mut ctrl| {
self.regs.modify_control(|mut ctrl| {
ctrl.set_irq_enable(false);
ctrl
});
firmware/zynq7000-hal/src/i2c.rs
+19 -20
View File
@@ -353,8 +353,7 @@ impl I2c {
I2cId::I2c1 => crate::PeriphSelect::I2c1,
};
enable_amba_peripheral_clock(periph_sel);
//reset(id);
regs.write_cr(
regs.write_control(
Control::builder()
.with_div_a(u2::new(clk_cfg.div_a()))
.with_div_b(u6::new(clk_cfg.div_b()))
@@ -379,7 +378,7 @@ impl I2c {
#[inline]
pub fn set_hold_bit(&mut self) {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_hold_bus(true);
cr
});
@@ -387,7 +386,7 @@ impl I2c {
#[inline]
pub fn clear_hold_bit(&mut self) {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_hold_bus(false);
cr
});
@@ -399,7 +398,7 @@ impl I2c {
data: &[u8],
generate_stop: bool,
) -> Result<(), I2cTxError> {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_acken(true);
cr.set_mode(zynq7000::i2c::Mode::Master);
cr.set_clear_fifo(true);
@@ -413,7 +412,7 @@ impl I2c {
let mut addr_set = false;
let mut written = 0;
// Clear the interrupt status register before using it to monitor the transfer.
self.regs.modify_isr(|isr| isr);
self.regs.modify_interrupt_status(|isr| isr);
loop {
let bytes_to_write = core::cmp::min(
FIFO_DEPTH - self.regs.read_transfer_size().size() as usize,
@@ -430,13 +429,13 @@ impl I2c {
self.start_transfer(addr);
addr_set = true;
}
let mut status = self.regs.read_sr();
let mut status = self.regs.read_status();
// While the hardware is busy sending out data, we poll for errors.
while status.tx_busy() {
let isr = self.regs.read_isr();
let isr = self.regs.read_interrupt_status();
self.check_and_handle_tx_errors(isr, first_write_cycle, bytes_to_write)?;
// Re-read for next check.
status = self.regs.read_sr();
status = self.regs.read_status();
}
first_write_cycle = false;
// Just need to poll to completion now.
@@ -445,8 +444,8 @@ impl I2c {
}
}
// Poll to completion.
while !self.regs.read_isr().complete() {
let isr = self.regs.read_isr();
while !self.regs.read_interrupt_status().complete() {
let isr = self.regs.read_interrupt_status();
self.check_and_handle_tx_errors(isr, first_write_cycle, data.len())?;
}
if generate_stop {
@@ -490,7 +489,7 @@ impl I2c {
}
pub fn clean_up_after_transfer_or_on_error(&mut self) {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_acken(false);
cr.set_clear_fifo(true);
cr
@@ -498,7 +497,7 @@ impl I2c {
}
pub fn read_transfer_blocking(&mut self, addr: u8, data: &mut [u8]) -> Result<(), I2cRxError> {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_acken(true);
cr.set_mode(zynq7000::i2c::Mode::Master);
cr.set_clear_fifo(true);
@@ -513,23 +512,23 @@ impl I2c {
return Err(I2cRxError::ReadDataLenTooLarge);
}
// Clear the interrupt status register before using it to monitor the transfer.
self.regs.modify_isr(|isr| isr);
self.regs.modify_interrupt_status(|isr| isr);
self.regs
.write_transfer_size(TransferSize::new_with_raw_value(data.len() as u32));
self.start_transfer(addr);
loop {
let mut status = self.regs.read_sr();
let mut status = self.regs.read_status();
loop {
let isr = self.regs.read_isr();
let isr = self.regs.read_interrupt_status();
self.check_and_handle_rx_errors(read, isr)?;
if status.rx_valid() {
break;
}
// Re-read for next check.
status = self.regs.read_sr();
status = self.regs.read_status();
}
// Data to be read.
while self.regs.read_sr().rx_valid() {
while self.regs.read_status().rx_valid() {
data[read] = self.regs.read_data().data();
read += 1;
}
@@ -545,8 +544,8 @@ impl I2c {
}
// Poll to completion.
while !self.regs.read_isr().complete() {
let isr = self.regs.read_isr();
while !self.regs.read_interrupt_status().complete() {
let isr = self.regs.read_interrupt_status();
self.check_and_handle_rx_errors(read, isr)?
}
self.clear_hold_bit();
firmware/zynq7000-hal/src/uart/mod.rs
+5 -5
View File
@@ -567,7 +567,7 @@ impl Uart {
};
enable_amba_peripheral_clock(periph_sel);
reset(uart_id);
reg_block.modify_cr(|mut v| {
reg_block.modify_control(|mut v| {
v.set_tx_dis(true);
v.set_rx_dis(true);
v
@@ -593,7 +593,7 @@ impl Uart {
})
.with_clksel(cfg.clk_sel)
.build();
reg_block.write_mr(mode);
reg_block.write_mode(mode);
reg_block.write_baudgen(
Baudgen::builder()
.with_cd(cfg.raw_clk_config().cd())
@@ -605,7 +605,7 @@ impl Uart {
.build(),
);
// Soft reset for both TX and RX.
reg_block.modify_cr(|mut v| {
reg_block.modify_control(|mut v| {
v.set_tx_rst(true);
v.set_rx_rst(true);
v
@@ -617,7 +617,7 @@ impl Uart {
));
// Enable TX and RX.
reg_block.modify_cr(|mut v| {
reg_block.modify_control(|mut v| {
v.set_tx_dis(false);
v.set_rx_dis(false);
v.set_tx_en(true);
@@ -640,7 +640,7 @@ impl Uart {
/// Set character mode.
#[inline]
pub fn set_mode(&mut self, mode: ChMode) {
self.regs().modify_mr(|mut mr| {
self.regs().modify_mode(|mut mr| {
mr.set_chmode(mode);
mr
});
firmware/zynq7000-hal/src/uart/rx.rs
+3 -3
View File
@@ -99,11 +99,11 @@ impl Rx {
/// Perform a soft-reset of the RX side of the UART.
#[inline]
pub fn soft_reset(&mut self) {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_rx_rst(true);
cr
});
while self.regs.read_cr().rx_rst() {}
while self.regs.read_control().rx_rst() {}
}
/// Helper function to start the interrupt driven reception of data.
@@ -203,7 +203,7 @@ impl Rx {
}
// Handle timeout event.
if isr.rx_timeout() && reset_rx_timeout {
self.regs.modify_cr(|mut cr| {
self.regs.modify_control(|mut cr| {
cr.set_rstto(true);
cr
});
firmware/zynq7000-hal/src/uart/tx.rs
+4 -4
View File
@@ -61,7 +61,7 @@ impl Tx {
if with_reset {
self.soft_reset();
}
self.regs.modify_cr(|mut val| {
self.regs.modify_control(|mut val| {
val.set_tx_en(true);
val.set_tx_dis(false);
val
@@ -71,7 +71,7 @@ impl Tx {
/// Disables TX side of the UART.
#[inline]
pub fn disable(&mut self) {
self.regs.modify_cr(|mut val| {
self.regs.modify_control(|mut val| {
val.set_tx_en(false);
val.set_tx_dis(true);
val
@@ -81,12 +81,12 @@ impl Tx {
/// Performs a soft-reset of the TX side of the UART.
#[inline]
pub fn soft_reset(&mut self) {
self.regs.modify_cr(|mut val| {
self.regs.modify_control(|mut val| {
val.set_tx_rst(true);
val
});
loop {
if !self.regs.read_cr().tx_rst() {
if !self.regs.read_control().tx_rst() {
break;
}
}
firmware/zynq7000/CHANGELOG.md
+1 -1
View File
@@ -8,7 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
# [unreleased]
- Better names for interrupt registers for UART and SPI
- Better names for various registers. Replaced abbreviations like SR, MR, CR, IER, IMR etc.
# [v0.2.0] 2026-04-01
firmware/zynq7000/src/gtc.rs
+3 -3
View File
@@ -3,7 +3,7 @@
pub const GTC_BASE_ADDR: usize = super::mpcore::MPCORE_BASE_ADDR + 0x0000_0200;
#[bitbybit::bitfield(u32, debug, forbid_overlaps, defmt_bitfields(feature = "defmt"))]
pub struct GtcControl {
pub struct Control {
#[bits(8..=15, rw)]
prescaler: u8,
#[bit(3, rw)]
@@ -31,10 +31,10 @@ pub struct Registers {
/// Count register 1, upper 32 bits
count_upper: u32,
/// Control register
ctrl: GtcControl,
control: Control,
/// Interrupt status register
#[mmio(PureRead, Write)]
isr: InterruptStatus,
interrupt_status: InterruptStatus,
/// Comparator 0, lower 32 bits
comparator_lower: u32,
/// Comparator 1, upper 32 bits
firmware/zynq7000/src/i2c.rs
+6 -6
View File
@@ -162,23 +162,23 @@ pub struct TransferSize {
#[derive(derive_mmio::Mmio)]
#[repr(C)]
pub struct Registers {
cr: Control,
control: Control,
#[mmio(PureRead)]
sr: Status,
status: Status,
addr: Address,
#[mmio(Read, Write)]
data: Fifo,
#[mmio(PureRead, Write, Modify)]
isr: InterruptStatus,
interrupt_status: InterruptStatus,
transfer_size: TransferSize,
slave_pause: u32,
timeout: Timeout,
#[mmio(PureRead)]
imr: InterruptMask,
enabled_interrupts: InterruptMask,
#[mmio(Write)]
ier: InterruptControl,
interrupt_enable: InterruptControl,
#[mmio(Write)]
idr: InterruptControl,
interrupt_disable: InterruptControl,
}
static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x2C);
firmware/zynq7000/src/ttc.rs
+3 -3
View File
@@ -189,9 +189,9 @@ pub struct Registers {
match_value_1: [RwValue; 3],
match_value_2: [RwValue; 3],
#[mmio(Read)]
isr: [InterruptStatus; 3],
ier: [InterruptControl; 3],
event_cntrl: [EventControl; 3],
interrupt_status: [InterruptStatus; 3],
interrupt_enable: [InterruptControl; 3],
event_control: [EventControl; 3],
#[mmio(PureRead)]
event_reg: [EventCount; 3],
}
firmware/zynq7000/src/uart.rs
+2 -2
View File
@@ -325,9 +325,9 @@ impl InterruptStatus {
#[repr(C)]
pub struct Registers {
/// Control Register
cr: Control,
control: Control,
/// Mode register
mr: Mode,
mode: Mode,
/// Interrupt enable register
#[mmio(Write)]
interrupt_enable: InterruptControl,